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package/gcc: bump to version 8.2.0

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Remove upstream patches.

Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This commit is contained in:
Romain Naour 2018-07-26 23:30:11 +02:00 committed by Thomas Petazzoni
parent c83f2c14f8
commit b338fb7429
8 changed files with 3 additions and 764 deletions
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101
package/gcc/8.1.0/0004-xtensa-fix-PR-target-65416.patch
View file

@ -1,101 +0,0 @@
From 87fda0741d210727672cba5e54a37a189e8ac04e Mon Sep 17 00:00:00 2001
From: Max Filippov <jcmvbkbc@gmail.com>
Date: Sun, 17 Jun 2018 21:18:39 -0700
Subject: [PATCH] xtensa: fix PR target/65416
The issue is caused by reordering of stack pointer update after stack
space allocation with instructions that write to the allocated stack
space. In windowed ABI register spill area for the previous call frame
is located just below the stack pointer and may be reloaded back into
the register file on movsp.
Implement allocate_stack pattern for windowed ABI configuration and
insert an instruction that prevents reordering of frame memory access
and stack pointer update.
gcc/
2018-06-19 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa.md (UNSPEC_FRAME_BLOCKAGE): New unspec
constant.
(allocate_stack, frame_blockage, *frame_blockage): New patterns.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Backported from: r261755
---
gcc/config/xtensa/xtensa.md | 46 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 84967dbedc08..209f839cfb0f 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -38,6 +38,7 @@
(UNSPEC_MEMW 11)
(UNSPEC_LSETUP_START 12)
(UNSPEC_LSETUP_END 13)
+ (UNSPEC_FRAME_BLOCKAGE 14)
(UNSPECV_SET_FP 1)
(UNSPECV_ENTRY 2)
@@ -1676,6 +1677,32 @@
;; Miscellaneous instructions.
+;; In windowed ABI stack pointer adjustment must happen before any access
+;; to the space allocated on stack is allowed, otherwise register spill
+;; area may be clobbered. That's what frame blockage is supposed to enforce.
+
+(define_expand "allocate_stack"
+ [(set (match_operand 0 "nonimmed_operand")
+ (minus (reg A1_REG) (match_operand 1 "add_operand")))
+ (set (reg A1_REG)
+ (minus (reg A1_REG) (match_dup 1)))]
+ "TARGET_WINDOWED_ABI"
+{
+ if (CONST_INT_P (operands[1]))
+ {
+ rtx neg_op0 = GEN_INT (-INTVAL (operands[1]));
+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
+ }
+ else
+ {
+ emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
+ operands[1]));
+ }
+ emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
+ emit_insn (gen_frame_blockage ());
+ DONE;
+})
+
(define_expand "prologue"
[(const_int 0)]
""
@@ -1767,6 +1794,25 @@
[(set_attr "length" "0")
(set_attr "type" "nop")])
+;; Do not schedule instructions accessing memory before this point.
+
+(define_expand "frame_blockage"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 1)] UNSPEC_FRAME_BLOCKAGE))]
+ ""
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+ operands[1] = stack_pointer_rtx;
+})
+
+(define_insn "*frame_blockage"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_operand:SI 1 "" "")] UNSPEC_FRAME_BLOCKAGE))]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
(define_insn "trap"
[(trap_if (const_int 1) (const_int 0))]
""
--
2.11.0

305
package/gcc/8.1.0/0005-arm-PR-target-81497-Fix-arm_acle.h-for-C.patch
View file

@ -1,305 +0,0 @@
From 4f147efb77e565d28a23c493986b57e2de15443e Mon Sep 17 00:00:00 2001
From: ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Fri, 8 Jun 2018 08:18:43 +0000
Subject: [PATCH] [arm] PR target/81497: Fix arm_acle.h for C++
Backport from mainline
2018-06-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/81497
* config/arm/arm-builtins.c (arm_type_qualifiers): Add
qualifier_void_pointer and qualifier_const_void_pointer.
(arm_ldc_qualifiers, arm_stc_qualifiers): Use the above.
(arm_init_builtins): Handle the above.
* config/arm/arm_acle.h (__arm_cdp, __arm_ldc, __arm_ldcl, __arm_stc,
__arm_stcl, __arm_mcr, __arm_cdp2, __arm_ldc2, __arm_ldcl2, __arm_stc2,
__arm_stcl2,__arm_mcr2, __arm_mcrr, __arm_mcrr2): Remove return for
void intrinsics.
* g++.target/arm/arm.exp: New file.
* g++.target/arm/pr81497.C: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-8-branch@261305 138bc75d-0d04-0410-961f-82ee72b054a4
Upstream-Status: Backport (gcc-8-branch)
Signed-off-by: Gaël PORTAY <gael.portay@savoirfairelinux.com>
[gportay: drop gcc/{,testsuite/}ChangeLog changes]
---
gcc/config/arm/arm-builtins.c | 42 +++++++++++++---------
gcc/config/arm/arm_acle.h | 28 +++++++--------
gcc/testsuite/g++.target/arm/arm.exp | 50 ++++++++++++++++++++++++++
gcc/testsuite/g++.target/arm/pr81497.C | 9 +++++
4 files changed, 99 insertions(+), 30 deletions(-)
create mode 100644 gcc/testsuite/g++.target/arm/arm.exp
create mode 100644 gcc/testsuite/g++.target/arm/pr81497.C
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 7fde7a04672..183a7b907f6 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -78,7 +78,11 @@ enum arm_type_qualifiers
/* Lane indices - must be within range of previous argument = a vector. */
qualifier_lane_index = 0x200,
/* Lane indices for single lane structure loads and stores. */
- qualifier_struct_load_store_lane_index = 0x400
+ qualifier_struct_load_store_lane_index = 0x400,
+ /* A void pointer. */
+ qualifier_void_pointer = 0x800,
+ /* A const void pointer. */
+ qualifier_const_void_pointer = 0x802
};
/* The qualifier_internal allows generation of a unary builtin from
@@ -202,7 +206,7 @@ arm_cdp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
static enum arm_type_qualifiers
arm_ldc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_unsigned_immediate,
- qualifier_unsigned_immediate, qualifier_const_pointer };
+ qualifier_unsigned_immediate, qualifier_const_void_pointer };
#define LDC_QUALIFIERS \
(arm_ldc_qualifiers)
@@ -210,7 +214,7 @@ arm_ldc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
static enum arm_type_qualifiers
arm_stc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_unsigned_immediate,
- qualifier_unsigned_immediate, qualifier_pointer };
+ qualifier_unsigned_immediate, qualifier_void_pointer };
#define STC_QUALIFIERS \
(arm_stc_qualifiers)
@@ -1095,19 +1099,25 @@ arm_init_builtin (unsigned int fcode, arm_builtin_datum *d,
if (qualifiers & qualifier_pointer && VECTOR_MODE_P (op_mode))
op_mode = GET_MODE_INNER (op_mode);
- eltype = arm_simd_builtin_type
- (op_mode,
- (qualifiers & qualifier_unsigned) != 0,
- (qualifiers & qualifier_poly) != 0);
- gcc_assert (eltype != NULL);
-
- /* Add qualifiers. */
- if (qualifiers & qualifier_const)
- eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
-
- if (qualifiers & qualifier_pointer)
- eltype = build_pointer_type (eltype);
-
+ /* For void pointers we already have nodes constructed by the midend. */
+ if (qualifiers & qualifier_void_pointer)
+ eltype = qualifiers & qualifier_const
+ ? const_ptr_type_node : ptr_type_node;
+ else
+ {
+ eltype
+ = arm_simd_builtin_type (op_mode,
+ (qualifiers & qualifier_unsigned) != 0,
+ (qualifiers & qualifier_poly) != 0);
+ gcc_assert (eltype != NULL);
+
+ /* Add qualifiers. */
+ if (qualifiers & qualifier_const)
+ eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
+
+ if (qualifiers & qualifier_pointer)
+ eltype = build_pointer_type (eltype);
+ }
/* If we have reached arg_num == 0, we are at a non-void
return type. Otherwise, we are still processing
arguments. */
diff --git a/gcc/config/arm/arm_acle.h b/gcc/config/arm/arm_acle.h
index 9a2f0ba30dc..c0f6ea2d156 100644
--- a/gcc/config/arm/arm_acle.h
+++ b/gcc/config/arm/arm_acle.h
@@ -38,35 +38,35 @@ __arm_cdp (const unsigned int __coproc, const unsigned int __opc1,
const unsigned int __CRd, const unsigned int __CRn,
const unsigned int __CRm, const unsigned int __opc2)
{
- return __builtin_arm_cdp (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
+ __builtin_arm_cdp (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
__arm_ldc (const unsigned int __coproc, const unsigned int __CRd,
const void * __p)
{
- return __builtin_arm_ldc (__coproc, __CRd, __p);
+ __builtin_arm_ldc (__coproc, __CRd, __p);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
__arm_ldcl (const unsigned int __coproc, const unsigned int __CRd,
const void * __p)
{
- return __builtin_arm_ldcl (__coproc, __CRd, __p);
+ __builtin_arm_ldcl (__coproc, __CRd, __p);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
__arm_stc (const unsigned int __coproc, const unsigned int __CRd,
void * __p)
{
- return __builtin_arm_stc (__coproc, __CRd, __p);
+ __builtin_arm_stc (__coproc, __CRd, __p);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
__arm_stcl (const unsigned int __coproc, const unsigned int __CRd,
void * __p)
{
- return __builtin_arm_stcl (__coproc, __CRd, __p);
+ __builtin_arm_stcl (__coproc, __CRd, __p);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
@@ -74,7 +74,7 @@ __arm_mcr (const unsigned int __coproc, const unsigned int __opc1,
uint32_t __value, const unsigned int __CRn, const unsigned int __CRm,
const unsigned int __opc2)
{
- return __builtin_arm_mcr (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
+ __builtin_arm_mcr (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
}
__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
@@ -90,35 +90,35 @@ __arm_cdp2 (const unsigned int __coproc, const unsigned int __opc1,
const unsigned int __CRd, const unsigned int __CRn,
const unsigned int __CRm, const unsigned int __opc2)
{
- return __builtin_arm_cdp2 (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
+ __builtin_arm_cdp2 (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
__arm_ldc2 (const unsigned int __coproc, const unsigned int __CRd,
const void * __p)
{
- return __builtin_arm_ldc2 (__coproc, __CRd, __p);
+ __builtin_arm_ldc2 (__coproc, __CRd, __p);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
__arm_ldc2l (const unsigned int __coproc, const unsigned int __CRd,
const void * __p)
{
- return __builtin_arm_ldc2l (__coproc, __CRd, __p);
+ __builtin_arm_ldc2l (__coproc, __CRd, __p);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
__arm_stc2 (const unsigned int __coproc, const unsigned int __CRd,
void * __p)
{
- return __builtin_arm_stc2 (__coproc, __CRd, __p);
+ __builtin_arm_stc2 (__coproc, __CRd, __p);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
__arm_stc2l (const unsigned int __coproc, const unsigned int __CRd,
void * __p)
{
- return __builtin_arm_stc2l (__coproc, __CRd, __p);
+ __builtin_arm_stc2l (__coproc, __CRd, __p);
}
__extension__ static __inline void __attribute__ ((__always_inline__))
@@ -126,7 +126,7 @@ __arm_mcr2 (const unsigned int __coproc, const unsigned int __opc1,
uint32_t __value, const unsigned int __CRn,
const unsigned int __CRm, const unsigned int __opc2)
{
- return __builtin_arm_mcr2 (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
+ __builtin_arm_mcr2 (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
}
__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
@@ -143,7 +143,7 @@ __extension__ static __inline void __attribute__ ((__always_inline__))
__arm_mcrr (const unsigned int __coproc, const unsigned int __opc1,
uint64_t __value, const unsigned int __CRm)
{
- return __builtin_arm_mcrr (__coproc, __opc1, __value, __CRm);
+ __builtin_arm_mcrr (__coproc, __opc1, __value, __CRm);
}
__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
@@ -159,7 +159,7 @@ __extension__ static __inline void __attribute__ ((__always_inline__))
__arm_mcrr2 (const unsigned int __coproc, const unsigned int __opc1,
uint64_t __value, const unsigned int __CRm)
{
- return __builtin_arm_mcrr2 (__coproc, __opc1, __value, __CRm);
+ __builtin_arm_mcrr2 (__coproc, __opc1, __value, __CRm);
}
__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
diff --git a/gcc/testsuite/g++.target/arm/arm.exp b/gcc/testsuite/g++.target/arm/arm.exp
new file mode 100644
index 00000000000..1a169d2f220
--- /dev/null
+++ b/gcc/testsuite/g++.target/arm/arm.exp
@@ -0,0 +1,50 @@
+# Specific regression driver for arm.
+# Copyright (C) 2009-2018 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>. */
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an arm target.
+if {![istarget arm*-*-*] } then {
+ return
+}
+
+# Load support procs.
+load_lib g++-dg.exp
+
+global DEFAULT_CXXFLAGS
+if ![info exists DEFAULT_CXXFLAGS] then {
+ set DEFAULT_CXXFLAGS " -pedantic-errors"
+}
+
+
+global dg_runtest_extra_prunes
+set dg_runtest_extra_prunes ""
+lappend dg_runtest_extra_prunes "warning: switch -m(cpu|arch)=.* conflicts with -m(cpu|arch)=.* switch"
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] \
+ "" $DEFAULT_CXXFLAGS
+
+# All done.
+set dg_runtest_extra_prunes ""
+dg-finish
+
diff --git a/gcc/testsuite/g++.target/arm/pr81497.C b/gcc/testsuite/g++.target/arm/pr81497.C
new file mode 100644
index 00000000000..0519a3a3045
--- /dev/null
+++ b/gcc/testsuite/g++.target/arm/pr81497.C
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+#include <arm_acle.h>
+
+int main ()
+{
+ return 0;
+}
--
2.17.1

355
package/gcc/8.1.0/0006-ARC-Reimplement-return-padding-operation-for-ARC700.patch
View file

@ -1,355 +0,0 @@
From d8d716f49c0057e239f2b64e7d902046b92d244f Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Fri, 24 Mar 2017 11:55:54 +0100
Subject: [PATCH] [ARC] Reimplement return padding operation for ARC700.
For ARC700, adding padding if necessary to avoid a mispredict. A
return could happen immediately after the function start. A
call/return and return/return must be 6 bytes apart to avoid
mispredict.
The old implementation was doing this operation very late in the
compilation process, and the additional nop instructions and/or
forcing some other instruction to take their long form was not taken
into account when generating brcc instructions. Thus, wrong code could
be generated.
gcc/
2017-03-24 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-protos.h (arc_pad_return): Remove.
* config/arc/arc.c (machine_function): Remove force_short_suffix
and size_reason.
(arc_print_operand): Adjust printing of '&'.
(arc_verify_short): Remove conditional printing of short suffix.
(arc_final_prescan_insn): Remove reference to size_reason.
(pad_return): New function.
(arc_reorg): Call pad_return.
(arc_pad_return): Remove.
(arc_init_machine_status): Remove reference to force_short_suffix.
* config/arc/arc.md (vunspec): Add VUNSPEC_ARC_BLOCKAGE.
(attr length): When attribute iscompact is true force to 2
regardless; in the case of maybe check if we want to force the
instruction to have 4 bytes length.
(nopv): Change it to generate 4 byte long nop as well.
(blockage): New pattern.
(simple_return): Remove call to arc_pad_return.
(p_return_i): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@261542 138bc75d-0d04-0410-961f-82ee72b054a4
Upstream-Status: Backport (trunk)
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
---
gcc/config/arc/arc-protos.h | 1 -
gcc/config/arc/arc.c | 156 +++++++++-----------
gcc/config/arc/arc.md | 26 +++-
4 files changed, 128 insertions(+), 93 deletions(-)
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index 67f3b4e3226b..ce4b6f84749e 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -89,7 +89,6 @@ extern void arc_clear_unalign (void);
extern void arc_toggle_unalign (void);
extern void split_addsi (rtx *);
extern void split_subsi (rtx *);
-extern void arc_pad_return (void);
extern void arc_split_move (rtx *);
extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
extern rtx arc_regno_use_in (unsigned int, rtx);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index b1a09d82b72e..22f1442a027c 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -2648,8 +2648,6 @@ typedef struct GTY (()) machine_function
struct arc_frame_info frame_info;
/* To keep track of unalignment caused by short insns. */
int unalign;
- int force_short_suffix; /* Used when disgorging return delay slot insns. */
- const char *size_reason;
struct arc_ccfsm ccfsm_current;
/* Map from uid to ccfsm state during branch shortening. */
rtx ccfsm_current_insn;
@@ -4307,7 +4305,7 @@ arc_print_operand (FILE *file, rtx x, int code)
}
break;
case '&':
- if (TARGET_ANNOTATE_ALIGN && cfun->machine->size_reason)
+ if (TARGET_ANNOTATE_ALIGN)
fprintf (file, "; unalign: %d", cfun->machine->unalign);
return;
case '+':
@@ -4980,7 +4978,6 @@ static int
arc_verify_short (rtx_insn *insn, int, int check_attr)
{
enum attr_iscompact iscompact;
- struct machine_function *machine;
if (check_attr > 0)
{
@@ -4988,10 +4985,6 @@ arc_verify_short (rtx_insn *insn, int, int check_attr)
if (iscompact == ISCOMPACT_FALSE)
return 0;
}
- machine = cfun->machine;
-
- if (machine->force_short_suffix >= 0)
- return machine->force_short_suffix;
return (get_attr_length (insn) & 2) != 0;
}
@@ -5030,8 +5023,6 @@ arc_final_prescan_insn (rtx_insn *insn, rtx *opvec ATTRIBUTE_UNUSED,
cfun->machine->prescan_initialized = 1;
}
arc_ccfsm_advance (insn, &arc_ccfsm_current);
-
- cfun->machine->size_reason = 0;
}
/* Given FROM and TO register numbers, say whether this elimination is allowed.
@@ -7673,6 +7664,76 @@ jli_call_scan (void)
}
}
+/* Add padding if necessary to avoid a mispredict. A return could
+ happen immediately after the function start. A call/return and
+ return/return must be 6 bytes apart to avoid mispredict. */
+
+static void
+pad_return (void)
+{
+ rtx_insn *insn;
+ long offset;
+
+ if (!TARGET_PAD_RETURN)
+ return;
+
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ {
+ rtx_insn *prev0 = prev_active_insn (insn);
+ bool wantlong = false;
+
+ if (!INSN_P (insn) || GET_CODE (PATTERN (insn)) != SIMPLE_RETURN)
+ continue;
+
+ if (!prev0)
+ {
+ prev0 = emit_insn_before (gen_nopv (), insn);
+ /* REG_SAVE_NOTE is used by Haifa scheduler, we are in reorg
+ so it is safe to reuse it for forcing a particular length
+ for an instruction. */
+ add_reg_note (prev0, REG_SAVE_NOTE, GEN_INT (1));
+ emit_insn_before (gen_nopv (), insn);
+ continue;
+ }
+ offset = get_attr_length (prev0);
+
+ if (get_attr_length (prev0) == 2
+ && get_attr_iscompact (prev0) != ISCOMPACT_TRUE)
+ {
+ /* Force long version of the insn. */
+ wantlong = true;
+ offset += 2;
+ }
+
+ rtx_insn *prev = prev_active_insn (prev0);
+ if (prev)
+ offset += get_attr_length (prev);
+
+ prev = prev_active_insn (prev);
+ if (prev)
+ offset += get_attr_length (prev);
+
+ switch (offset)
+ {
+ case 2:
+ prev = emit_insn_before (gen_nopv (), insn);
+ add_reg_note (prev, REG_SAVE_NOTE, GEN_INT (1));
+ break;
+ case 4:
+ emit_insn_before (gen_nopv (), insn);
+ break;
+ default:
+ continue;
+ }
+
+ if (wantlong)
+ add_reg_note (prev0, REG_SAVE_NOTE, GEN_INT (1));
+
+ /* Emit a blockage to avoid delay slot scheduling. */
+ emit_insn_before (gen_blockage(), insn);
+ }
+}
+
static int arc_reorg_in_progress = 0;
/* ARC's machince specific reorg function. */
@@ -7698,6 +7759,7 @@ arc_reorg (void)
workaround_arc_anomaly ();
jli_call_scan ();
+ pad_return ();
/* FIXME: should anticipate ccfsm action, generate special patterns for
to-be-deleted branches that have no delay slot and have at least the
@@ -9256,79 +9318,6 @@ arc_branch_size_unknown_p (void)
return !optimize_size && arc_reorg_in_progress;
}
-/* We are about to output a return insn. Add padding if necessary to avoid
- a mispredict. A return could happen immediately after the function
- start, but after a call we know that there will be at least a blink
- restore. */
-
-void
-arc_pad_return (void)
-{
- rtx_insn *insn = current_output_insn;
- rtx_insn *prev = prev_active_insn (insn);
- int want_long;
-
- if (!prev)
- {
- fputs ("\tnop_s\n", asm_out_file);
- cfun->machine->unalign ^= 2;
- want_long = 1;
- }
- /* If PREV is a sequence, we know it must be a branch / jump or a tailcall,
- because after a call, we'd have to restore blink first. */
- else if (GET_CODE (PATTERN (prev)) == SEQUENCE)
- return;
- else
- {
- want_long = (get_attr_length (prev) == 2);
- prev = prev_active_insn (prev);
- }
- if (!prev
- || ((NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
- ? CALL_ATTR (as_a <rtx_sequence *> (PATTERN (prev))->insn (0),
- NON_SIBCALL)
- : CALL_ATTR (prev, NON_SIBCALL)))
- {
- if (want_long)
- cfun->machine->size_reason
- = "call/return and return/return must be 6 bytes apart to avoid mispredict";
- else if (TARGET_UNALIGN_BRANCH && cfun->machine->unalign)
- {
- cfun->machine->size_reason
- = "Long unaligned jump avoids non-delay slot penalty";
- want_long = 1;
- }
- /* Disgorge delay insn, if there is any, and it may be moved. */
- if (final_sequence
- /* ??? Annulled would be OK if we can and do conditionalize
- the delay slot insn accordingly. */
- && !INSN_ANNULLED_BRANCH_P (insn)
- && (get_attr_cond (insn) != COND_USE
- || !reg_set_p (gen_rtx_REG (CCmode, CC_REG),
- XVECEXP (final_sequence, 0, 1))))
- {
- prev = as_a <rtx_insn *> (XVECEXP (final_sequence, 0, 1));
- gcc_assert (!prev_real_insn (insn)
- || !arc_hazard (prev_real_insn (insn), prev));
- cfun->machine->force_short_suffix = !want_long;
- rtx save_pred = current_insn_predicate;
- final_scan_insn (prev, asm_out_file, optimize, 1, NULL);
- cfun->machine->force_short_suffix = -1;
- prev->set_deleted ();
- current_output_insn = insn;
- current_insn_predicate = save_pred;
- }
- else if (want_long)
- fputs ("\tnop\n", asm_out_file);
- else
- {
- fputs ("\tnop_s\n", asm_out_file);
- cfun->machine->unalign ^= 2;
- }
- }
- return;
-}
-
/* The usual; we set up our machine_function data. */
static struct machine_function *
@@ -9337,7 +9326,6 @@ arc_init_machine_status (void)
struct machine_function *machine;
machine = ggc_cleared_alloc<machine_function> ();
machine->fn_type = ARC_FUNCTION_UNKNOWN;
- machine->force_short_suffix = -1;
return machine;
}
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 5610bab694c6..2401926f08df 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -162,6 +162,7 @@
VUNSPEC_ARC_CAS
VUNSPEC_ARC_SC
VUNSPEC_ARC_LL
+ VUNSPEC_ARC_BLOCKAGE
])
(define_constants
@@ -385,13 +386,18 @@
;; and insn lengths: insns with shimm values cannot be conditionally executed.
(define_attr "length" ""
(cond
- [(eq_attr "iscompact" "true,maybe")
+ [(eq_attr "iscompact" "true")
+ (const_int 2)
+
+ (eq_attr "iscompact" "maybe")
(cond
[(eq_attr "type" "sfunc")
(cond [(match_test "GET_CODE (PATTERN (insn)) == COND_EXEC")
(const_int 12)]
(const_int 10))
- (match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 4)]
+ (match_test "GET_CODE (PATTERN (insn)) == COND_EXEC") (const_int 4)
+ (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (1))")
+ (const_int 4)]
(const_int 2))
(eq_attr "iscompact" "true_limm")
@@ -4447,8 +4453,16 @@ archs4x, archs4xd, archs4xd_slow"
""
"nop%?"
[(set_attr "type" "misc")
- (set_attr "iscompact" "true")
- (set_attr "length" "2")])
+ (set_attr "iscompact" "maybe")
+ (set_attr "length" "*")])
+
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] VUNSPEC_ARC_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")
+ (set_attr "type" "block")]
+)
;; Split up troublesome insns for better scheduling.
@@ -4993,8 +5007,6 @@ archs4x, archs4xd, archs4xd_slow"
{
return \"rtie\";
}
- if (TARGET_PAD_RETURN)
- arc_pad_return ();
output_asm_insn (\"j%!%* [%0]%&\", &reg);
return \"\";
}
@@ -5038,8 +5050,6 @@ archs4x, archs4xd, archs4xd_slow"
arc_return_address_register (arc_compute_function_type
(cfun)));
- if (TARGET_PAD_RETURN)
- arc_pad_return ();
output_asm_insn (\"j%d0%!%# [%1]%&\", xop);
/* record the condition in case there is a delay insn. */
arc_ccfsm_record_condition (xop[0], false, insn, 0);
--
2.17.1

0
package/gcc/8.1.0/0001-uclibc-conf.patch → package/gcc/8.2.0/0001-uclibc-conf.patch
View file

0
package/gcc/8.1.0/0002-arm-softfloat-libgcc.patch → package/gcc/8.2.0/0002-arm-softfloat-libgcc.patch
View file

0
package/gcc/8.1.0/0003-remove-selftests.patch → package/gcc/8.2.0/0003-remove-selftests.patch
View file

2
package/gcc/Config.in.host
View file

@ -80,7 +80,7 @@ config BR2_GCC_VERSION
default "5.5.0" if BR2_GCC_VERSION_5_X
default "6.4.0" if BR2_GCC_VERSION_6_X
default "7.3.0" if BR2_GCC_VERSION_7_X
default "8.1.0" if BR2_GCC_VERSION_8_X
default "8.2.0" if BR2_GCC_VERSION_8_X
default "arc-2018.03" if BR2_GCC_VERSION_ARC
default "or1k-musl-5.4.0-20170218" if BR2_GCC_VERSION_OR1K

4
package/gcc/gcc.hash
View file

@ -6,8 +6,8 @@ sha512 670ff52c2ae12c7852c12987e91798c5aa8bd6daf21f0d6e0cd57a4aa59cc4f06a837fe7
sha512 02c60e54527c7adf584798d5251f8a0b80c93d5deafce82501b2c28e6692e0bd783927bbfc4bc527a863c0cccc025150a34740a9e29badb02d4b48e56a8aba90 gcc-6.4.0.tar.xz
# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-7.3.0/sha512.sum
sha512 ad41a7e4584e40e92cdf860bc0288500fbaf5dfb7e8c3fcabe9eba809c87bcfa85b46c19c19921b0cdf6d05483faede8287bb9ea120c0d1559449a70e602c8d4 gcc-7.3.0.tar.xz
# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-8.1.0/sha512.sum
sha512 c96246f34a7aeb404c4525b754dc7f7708a18e06271aadb2b32fef00e6e0940f584e52430bfe2ab01e699c93e3cb418adc113d2622fa826facbec0ec8ce3eb2c gcc-8.1.0.tar.xz
# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-8.2.0/sha512.sum
sha512 64898a165f67e136d802a92e7633bf1b06c85266027e52127ea025bf5fc2291b5e858288aac0bdba246e6cdf7c6ec88bc8e0e7f3f6f1985f4297710cafde56ed gcc-8.2.0.tar.xz
# Locally calculated (fetched from Github)
sha512 7c6555d629957d154c9c0524fc2c82301c9ab9192f5b9175c47b1f2dde298ac032e86360d91866c3c4d001cf8e191a90dc88f3c900ebfc367c5888ab7bf2ce79 gcc-arc-2018.03.tar.gz