configs/andes_ae350_45: enable RISC-V atomic extension
Let's select the RVA option as Andes 45-series CPUs support IMAFDC extensions. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>MyCruft^2
parent
be5e4a1708
commit
f5573b8a04
|
@ -1,6 +1,7 @@
|
|||
BR2_riscv=y
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_RVM=y
|
||||
BR2_RISCV_ISA_RVA=y
|
||||
BR2_RISCV_ISA_RVF=y
|
||||
BR2_RISCV_ISA_RVD=y
|
||||
BR2_RISCV_ISA_RVC=y
|
||||
|
|
Loading…
Reference in New Issue