![Alistair Francis](/assets/img/avatar_default.png)
Update libaio from 0.3.108 to 0.3.110. This adds AArch64 support. The 0001-arches.patch is simplified to only add MIPS definitions: the SPARC support has been merged upstream, and we don't need the m68k and parisc support. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> [Thomas: - respect alphabetic ordering in the definition of BR2_PACKAGE_LIBAIO_ARCH_SUPPORTS - add more details in the commit log.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
250 lines
7.6 KiB
Diff
250 lines
7.6 KiB
Diff
Patch borrowed from OpenEmbedded, available at
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/meta/recipes-extended/libaio/libaio/00_arches.patch in their source
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tree. This patch has been modified to only add the MIPS definitions.
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The patch adds MIPS specific definitions (syscall number and macros).
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Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
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Index: libaio-0.3.110/src/syscall.h
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===================================================================
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--- libaio-0.3.110.orig/src/syscall.h
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+++ libaio-0.3.110/src/syscall.h
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@@ -28,6 +28,8 @@
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#include "syscall-sparc.h"
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#elif defined(__aarch64__)
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#include "syscall-arm64.h"
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+#elif defined(__mips__)
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+#include "syscall-mips.h"
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#else
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#warning "using generic syscall method"
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#include "syscall-generic.h"
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Index: libaio-0.3.110/src/syscall-mips.h
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===================================================================
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--- /dev/null
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+++ libaio-0.3.110/src/syscall-mips.h
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@@ -0,0 +1,223 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
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+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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+ *
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+ * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
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+ * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
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+ */
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+
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+#ifndef _MIPS_SIM_ABI32
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+#define _MIPS_SIM_ABI32 1
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+#define _MIPS_SIM_NABI32 2
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+#define _MIPS_SIM_ABI64 3
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+#endif
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+
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+#if _MIPS_SIM == _MIPS_SIM_ABI32
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+
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+/*
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+ * Linux o32 style syscalls are in the range from 4000 to 4999.
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+ */
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+#define __NR_Linux 4000
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+#define __NR_io_setup (__NR_Linux + 241)
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+#define __NR_io_destroy (__NR_Linux + 242)
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+#define __NR_io_getevents (__NR_Linux + 243)
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+#define __NR_io_submit (__NR_Linux + 244)
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+#define __NR_io_cancel (__NR_Linux + 245)
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+
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+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
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+
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+#if _MIPS_SIM == _MIPS_SIM_ABI64
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+
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+/*
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+ * Linux 64-bit syscalls are in the range from 5000 to 5999.
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+ */
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+#define __NR_Linux 5000
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+#define __NR_io_setup (__NR_Linux + 200)
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+#define __NR_io_destroy (__NR_Linux + 201)
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+#define __NR_io_getevents (__NR_Linux + 202)
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+#define __NR_io_submit (__NR_Linux + 203)
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+#define __NR_io_cancel (__NR_Linux + 204)
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+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
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+
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+#if _MIPS_SIM == _MIPS_SIM_NABI32
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+
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+/*
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+ * Linux N32 syscalls are in the range from 6000 to 6999.
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+ */
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+#define __NR_Linux 6000
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+#define __NR_io_setup (__NR_Linux + 200)
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+#define __NR_io_destroy (__NR_Linux + 201)
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+#define __NR_io_getevents (__NR_Linux + 202)
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+#define __NR_io_submit (__NR_Linux + 203)
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+#define __NR_io_cancel (__NR_Linux + 204)
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+#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
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+
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+#define io_syscall1(type,fname,sname,atype,a) \
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+type fname(atype a) \
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+{ \
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+ register unsigned long __a0 asm("$4") = (unsigned long) a; \
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+ register unsigned long __a3 asm("$7"); \
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+ unsigned long __v0; \
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+ \
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+ __asm__ volatile ( \
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+ ".set\tnoreorder\n\t" \
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+ "li\t$2, %3\t\t\t# " #fname "\n\t" \
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+ "syscall\n\t" \
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+ "move\t%0, $2\n\t" \
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+ ".set\treorder" \
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+ : "=&r" (__v0), "=r" (__a3) \
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+ : "r" (__a0), "i" (__NR_##sname) \
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+ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
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+ "memory"); \
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+ \
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+ if (__a3 == 0) \
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+ return (type) __v0; \
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+ return (type) -1; \
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+}
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+
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+#define io_syscall2(type,fname,sname,atype,a,btype,b) \
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+type fname(atype a, btype b) \
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+{ \
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+ register unsigned long __a0 asm("$4") = (unsigned long) a; \
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+ register unsigned long __a1 asm("$5") = (unsigned long) b; \
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+ register unsigned long __a3 asm("$7"); \
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+ unsigned long __v0; \
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+ \
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+ __asm__ volatile ( \
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+ ".set\tnoreorder\n\t" \
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+ "li\t$2, %4\t\t\t# " #fname "\n\t" \
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+ "syscall\n\t" \
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+ "move\t%0, $2\n\t" \
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+ ".set\treorder" \
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+ : "=&r" (__v0), "=r" (__a3) \
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+ : "r" (__a0), "r" (__a1), "i" (__NR_##sname) \
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+ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
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+ "memory"); \
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+ \
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+ if (__a3 == 0) \
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+ return (type) __v0; \
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+ return (type) -1; \
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+}
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+
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+#define io_syscall3(type,fname,sname,atype,a,btype,b,ctype,c) \
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+type fname(atype a, btype b, ctype c) \
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+{ \
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+ register unsigned long __a0 asm("$4") = (unsigned long) a; \
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+ register unsigned long __a1 asm("$5") = (unsigned long) b; \
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+ register unsigned long __a2 asm("$6") = (unsigned long) c; \
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+ register unsigned long __a3 asm("$7"); \
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+ unsigned long __v0; \
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+ \
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+ __asm__ volatile ( \
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+ ".set\tnoreorder\n\t" \
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+ "li\t$2, %5\t\t\t# " #fname "\n\t" \
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+ "syscall\n\t" \
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+ "move\t%0, $2\n\t" \
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+ ".set\treorder" \
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+ : "=&r" (__v0), "=r" (__a3) \
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+ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \
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+ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
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+ "memory"); \
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+ \
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+ if (__a3 == 0) \
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+ return (type) __v0; \
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+ return (type) -1; \
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+}
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+
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+#define io_syscall4(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d) \
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+type fname(atype a, btype b, ctype c, dtype d) \
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+{ \
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+ register unsigned long __a0 asm("$4") = (unsigned long) a; \
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+ register unsigned long __a1 asm("$5") = (unsigned long) b; \
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+ register unsigned long __a2 asm("$6") = (unsigned long) c; \
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+ register unsigned long __a3 asm("$7") = (unsigned long) d; \
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+ unsigned long __v0; \
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+ \
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+ __asm__ volatile ( \
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+ ".set\tnoreorder\n\t" \
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+ "li\t$2, %5\t\t\t# " #fname "\n\t" \
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+ "syscall\n\t" \
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+ "move\t%0, $2\n\t" \
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+ ".set\treorder" \
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+ : "=&r" (__v0), "+r" (__a3) \
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+ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \
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+ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
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+ "memory"); \
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+ \
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+ if (__a3 == 0) \
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+ return (type) __v0; \
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+ return (type) -1; \
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+}
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+
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+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
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+
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+/*
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+ * Using those means your brain needs more than an oil change ;-)
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+ */
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+
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+#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
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+type fname(atype a, btype b, ctype c, dtype d, etype e) \
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+{ \
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+ register unsigned long __a0 asm("$4") = (unsigned long) a; \
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+ register unsigned long __a1 asm("$5") = (unsigned long) b; \
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+ register unsigned long __a2 asm("$6") = (unsigned long) c; \
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+ register unsigned long __a3 asm("$7") = (unsigned long) d; \
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+ unsigned long __v0; \
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+ \
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+ __asm__ volatile ( \
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+ ".set\tnoreorder\n\t" \
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+ "lw\t$2, %6\n\t" \
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+ "subu\t$29, 32\n\t" \
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+ "sw\t$2, 16($29)\n\t" \
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+ "li\t$2, %5\t\t\t# " #fname "\n\t" \
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+ "syscall\n\t" \
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+ "move\t%0, $2\n\t" \
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+ "addiu\t$29, 32\n\t" \
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+ ".set\treorder" \
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+ : "=&r" (__v0), "+r" (__a3) \
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+ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname), \
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+ "m" ((unsigned long)e) \
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+ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
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+ "memory"); \
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+ \
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+ if (__a3 == 0) \
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+ return (type) __v0; \
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+ return (type) -1; \
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+}
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+
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+#endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */
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+
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+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
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+
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+#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
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+type fname (atype a,btype b,ctype c,dtype d,etype e) \
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+{ \
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+ register unsigned long __a0 asm("$4") = (unsigned long) a; \
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+ register unsigned long __a1 asm("$5") = (unsigned long) b; \
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+ register unsigned long __a2 asm("$6") = (unsigned long) c; \
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+ register unsigned long __a3 asm("$7") = (unsigned long) d; \
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+ register unsigned long __a4 asm("$8") = (unsigned long) e; \
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+ unsigned long __v0; \
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+ \
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+ __asm__ volatile ( \
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+ ".set\tnoreorder\n\t" \
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+ "li\t$2, %6\t\t\t# " #fname "\n\t" \
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+ "syscall\n\t" \
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+ "move\t%0, $2\n\t" \
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+ ".set\treorder" \
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+ : "=&r" (__v0), "+r" (__a3) \
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+ : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "i" (__NR_##sname) \
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+ : "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
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+ "memory"); \
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+ \
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+ if (__a3 == 0) \
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+ return (type) __v0; \
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+ return (type) -1; \
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+}
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+
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+#endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */
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+
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