![Bernd Kuhls](/assets/img/avatar_default.png)
Although this PR is still discussed upstream it Fixes: http://autobuild.buildroot.net/results/081/081c0426dde94015f5391e612454fc0b86888943/ Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
386 lines
12 KiB
Diff
386 lines
12 KiB
Diff
From 576b64d6a4253f900d4846503df55dba051063ab Mon Sep 17 00:00:00 2001
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From: gxw <guxiwei-hf@loongson.cn>
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Date: Tue, 22 Oct 2019 19:20:19 +0800
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Subject: [PATCH] Adjust the mmi/msa detection mode for mips platform.
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Using mips-simd-check.sh to test the current compiler support mmi/msa
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or not before make. If supported, enable mmi/msa.
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According to the model name in /proc/cpuinfo to test the current
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cpu support mmi/msa or not for runtime detection.
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Now We can use the following make instructions on mips platform:
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1. make (automatic detection mmi/msa)
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2. make ENABLE_MMI=No (disable mmi)
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3. make ENABLE_MSA=No (disable msa)
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4. make ENABLE_MMI=No ENABLE_MSA=No (disable mmi and msa)
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Change-Id: Ibd348ebc11912d7fca1b548c76838675d69b7c40
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Downloaded from upstream PR:
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https://github.com/cisco/openh264/pull/3175
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Signed-off-by: gxw <guxiwei-hf@loongson.cn>
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[Bernd: rebased on top of patch 0001]
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Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de>
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---
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Makefile | 2 ++
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build/arch.mk | 18 ++++++++++++----
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build/mips-simd-check.sh | 32 +++++++++++++++++++++++++++
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build/mktargets.py | 43 ++++++++++++++++++++++++++-----------
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codec/common/inc/cpu_core.h | 1 +
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codec/common/src/cpu.cpp | 37 +++++++++++++++++++++++++------
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codec/common/targets.mk | 18 ++++++++++++----
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codec/decoder/targets.mk | 18 ++++++++++++----
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codec/encoder/targets.mk | 18 ++++++++++++----
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codec/processing/targets.mk | 18 ++++++++++++----
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10 files changed, 166 insertions(+), 39 deletions(-)
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create mode 100755 build/mips-simd-check.sh
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diff --git a/Makefile b/Makefile
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index 74ff029d9..65d13630b 100644
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--- a/Makefile
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+++ b/Makefile
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@@ -35,6 +35,8 @@ GTEST_VER=release-1.8.1
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STATIC_LDFLAGS=-lstdc++
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STRIP ?= strip
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USE_STACK_PROTECTOR = Yes
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+ENABLE_MMI=Yes
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+ENABLE_MSA=Yes
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SHAREDLIB_MAJORVERSION=5
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FULL_VERSION := 2.0.0
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diff --git a/build/arch.mk b/build/arch.mk
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index 8ac3e70a5..555e4afec 100644
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--- a/build/arch.mk
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+++ b/build/arch.mk
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@@ -30,14 +30,24 @@ CFLAGS += -DHAVE_NEON_AARCH64
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endif
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endif
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-#for loongson
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+#for mips
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ifneq ($(filter mips mips64, $(ARCH)),)
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ifeq ($(USE_ASM), Yes)
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ASM_ARCH = mips
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ASMFLAGS += -I$(SRC_PATH)codec/common/mips/
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-LOONGSON3A = $(shell g++ -dM -E - < /dev/null | grep '_MIPS_TUNE ' | cut -f 3 -d " ")
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-ifeq ($(LOONGSON3A), "loongson3a")
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-CFLAGS += -DHAVE_MMI
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+#mmi
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+ifeq ($(ENABLE_MMI), Yes)
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+ENABLE_MMI = $(shell $(SRC_PATH)build/mips-simd-check.sh $(CC) mmi)
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+ifeq ($(ENABLE_MMI), Yes)
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+CFLAGS += -march=loongson3a -DHAVE_MMI
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+endif
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+endif
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+#msa
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+ifeq ($(ENABLE_MSA), Yes)
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+ENABLE_MSA = $(shell $(SRC_PATH)build/mips-simd-check.sh $(CC) msa)
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+ifeq ($(ENABLE_MSA), Yes)
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+CFLAGS += -mmsa -DHAVE_MSA
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+endif
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endif
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endif
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endif
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diff --git a/build/mips-simd-check.sh b/build/mips-simd-check.sh
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new file mode 100755
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index 000000000..cbc29e3d3
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--- /dev/null
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+++ b/build/mips-simd-check.sh
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@@ -0,0 +1,32 @@
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+#!/bin/bash
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+#**********************************************************************************
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+# This script is using in build/arch.mk for mips to detect the simd instructions:
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+# mmi, msa (maybe more in the future).
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+#
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+# --usage:
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+# ./mips-simd-check.sh $(CC) mmi
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+# or ./mips-simd-check.sh $(CC) msa
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+#
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+# date: 10/17/2019 Created
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+#**********************************************************************************
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+
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+TMPC=$(mktemp test.XXXXXX.c)
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+TMPO=$(mktemp test.XXXXXX.o)
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+if [ $2 == "mmi" ]
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+then
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+ echo "void main(void){ __asm__ volatile(\"punpcklhw \$f0, \$f0, \$f0\"); }" > $TMPC
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+ $1 -march=loongson3a $TMPC -o $TMPO &> /dev/null
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+ if test -s $TMPO
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+ then
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+ echo "Yes"
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+ fi
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+elif [ $2 == "msa" ]
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+then
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+ echo "void main(void){ __asm__ volatile(\"addvi.b \$w0, \$w1, 1\"); }" > $TMPC
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+ $1 -mmsa $TMPC -o $TMPO &> /dev/null
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+ if test -s $TMPO
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+ then
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+ echo "Yes"
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+ fi
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+fi
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+rm -f $TMPC $TMPO
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diff --git a/build/mktargets.py b/build/mktargets.py
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index 593280c09..518909d3d 100755
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--- a/build/mktargets.py
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+++ b/build/mktargets.py
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@@ -119,9 +119,9 @@ def find_sources():
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armfiles.append(file)
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mipsfiles = []
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for file in cfiles:
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- c = file.split('/')
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- if 'mips' in c:
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- mipsfiles.append(file)
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+ c = file.split('/')
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+ if 'mips' in c:
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+ mipsfiles.append(file)
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cfiles = [x for x in cfiles if x not in mipsfiles]
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@@ -181,15 +181,34 @@ def find_sources():
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f.write("OBJS += $(%s_OBJSARM64)\n\n"%(PREFIX))
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if len(mipsfiles) > 0:
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- f.write("%s_ASM_MIPS_SRCS=\\\n"%(PREFIX))
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- for c in mipsfiles:
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- f.write("\t$(%s_SRCDIR)/%s\\\n"%(PREFIX, c))
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- f.write("\n")
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- f.write("%s_OBJSMIPS += $(%s_ASM_MIPS_SRCS:.c=.$(OBJ))\n"%(PREFIX, PREFIX))
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- f.write("ifeq ($(ASM_ARCH), mips)\n")
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- f.write("%s_OBJS += $(%s_OBJSMIPS)\n"%(PREFIX,PREFIX))
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- f.write("endif\n")
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- f.write("OBJS += $(%s_OBJSMIPS)\n\n"%(PREFIX))
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+ mmifiles = []
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+ for file in mipsfiles:
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+ if '_mmi' in file:
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+ mmifiles.append(file)
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+ f.write("%s_ASM_MIPS_MMI_SRCS=\\\n"%(PREFIX))
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+ for c in mmifiles:
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+ f.write("\t$(%s_SRCDIR)/%s\\\n"%(PREFIX, c))
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+ f.write("\n")
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+ f.write("%s_OBJSMIPS_MMI += $(%s_ASM_MIPS_MMI_SRCS:.c=.$(OBJ))\n\n"%(PREFIX, PREFIX))
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+ msafiles = []
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+ for file in mipsfiles:
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+ if '_msa' in file:
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+ msafiles.append(file)
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+ f.write("%s_ASM_MIPS_MSA_SRCS=\\\n"%(PREFIX))
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+ for c in msafiles:
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+ f.write("\t$(%s_SRCDIR)/%s\\\n"%(PREFIX, c))
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+ f.write("\n")
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+ f.write("%s_OBJSMIPS_MSA += $(%s_ASM_MIPS_MSA_SRCS:.c=.$(OBJ))\n"%(PREFIX, PREFIX))
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+ f.write("ifeq ($(ASM_ARCH), mips)\n")
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+ f.write("ifeq ($(ENABLE_MMI), Yes)\n")
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+ f.write("%s_OBJS += $(%s_OBJSMIPS_MMI)\n"%(PREFIX,PREFIX))
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+ f.write("endif\n")
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+ f.write("ifeq ($(ENABLE_MSA), Yes)\n")
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+ f.write("%s_OBJS += $(%s_OBJSMIPS_MSA)\n"%(PREFIX,PREFIX))
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+ f.write("endif\n")
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+ f.write("endif\n")
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+ f.write("OBJS += $(%s_OBJSMIPS_MMI)\n"%(PREFIX))
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+ f.write("OBJS += $(%s_OBJSMIPS_MSA)\n\n"%(PREFIX))
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f.write("OBJS += $(%s_OBJS)\n\n"%(PREFIX))
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write_cpp_rule_pattern(f)
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diff --git a/codec/common/inc/cpu_core.h b/codec/common/inc/cpu_core.h
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index e5906c62b..f25787b04 100644
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--- a/codec/common/inc/cpu_core.h
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+++ b/codec/common/inc/cpu_core.h
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@@ -86,6 +86,7 @@
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/* For loongson */
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#define WELS_CPU_MMI 0x00000001 /* mmi */
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+#define WELS_CPU_MSA 0x00000002 /* msa */
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/*
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* Interfaces for CPU core feature detection as below
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diff --git a/codec/common/src/cpu.cpp b/codec/common/src/cpu.cpp
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index a39fd0645..94bb2d5d3 100644
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--- a/codec/common/src/cpu.cpp
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+++ b/codec/common/src/cpu.cpp
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@@ -309,12 +309,37 @@ uint32_t WelsCPUFeatureDetect (int32_t* pNumberOfLogicProcessors) {
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#elif defined(mips)
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/* for loongson */
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+static uint32_t get_cpu_flags_from_cpuinfo(void)
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+{
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+ uint32_t flags = 0;
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+
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+# ifdef __linux__
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+ FILE* fp = fopen("/proc/cpuinfo", "r");
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+ if (!fp)
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+ return flags;
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+
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+ char buf[200];
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+ memset(buf, 0, sizeof(buf));
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+ while (fgets(buf, sizeof(buf), fp)) {
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+ if (!strncmp(buf, "model name", strlen("model name"))) {
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+ if (strstr(buf, "3A4000")) {
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+ flags |= WELS_CPU_MSA | WELS_CPU_MMI;
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+ } else if (strstr(buf, "2K1000")) {
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+ flags |= WELS_CPU_MSA | WELS_CPU_MMI;
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+ } else if (strstr(buf, "Loongson-3A") || strstr(buf, "Loongson-3B")) {
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+ flags |= WELS_CPU_MMI;
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+ }
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+ break;
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+ }
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+ }
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+ fclose(fp);
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+# endif
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+
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+ return flags;
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+}
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+
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uint32_t WelsCPUFeatureDetect (int32_t* pNumberOfLogicProcessors) {
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-#if defined(HAVE_MMI)
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- return WELS_CPU_MMI;
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-#else
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- return 0;
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-#endif
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+ return get_cpu_flags_from_cpuinfo();
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}
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#else /* Neither X86_ASM, HAVE_NEON, HAVE_NEON_AARCH64 nor mips */
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@@ -324,5 +349,3 @@ uint32_t WelsCPUFeatureDetect (int32_t* pNumberOfLogicProcessors) {
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}
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#endif
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-
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-
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diff --git a/codec/common/targets.mk b/codec/common/targets.mk
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index 96843cd9d..f2cd192fd 100644
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--- a/codec/common/targets.mk
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+++ b/codec/common/targets.mk
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@@ -66,18 +66,28 @@ COMMON_OBJS += $(COMMON_OBJSARM64)
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endif
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OBJS += $(COMMON_OBJSARM64)
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-COMMON_ASM_MIPS_SRCS=\
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+COMMON_ASM_MIPS_MMI_SRCS=\
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$(COMMON_SRCDIR)/mips/copy_mb_mmi.c\
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$(COMMON_SRCDIR)/mips/deblock_mmi.c\
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$(COMMON_SRCDIR)/mips/expand_picture_mmi.c\
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$(COMMON_SRCDIR)/mips/intra_pred_com_mmi.c\
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$(COMMON_SRCDIR)/mips/satd_sad_mmi.c\
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-COMMON_OBJSMIPS += $(COMMON_ASM_MIPS_SRCS:.c=.$(OBJ))
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+COMMON_OBJSMIPS_MMI += $(COMMON_ASM_MIPS_MMI_SRCS:.c=.$(OBJ))
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+
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+COMMON_ASM_MIPS_MSA_SRCS=\
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+
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+COMMON_OBJSMIPS_MSA += $(COMMON_ASM_MIPS_MSA_SRCS:.c=.$(OBJ))
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ifeq ($(ASM_ARCH), mips)
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-COMMON_OBJS += $(COMMON_OBJSMIPS)
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+ifeq ($(ENABLE_MMI), Yes)
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+COMMON_OBJS += $(COMMON_OBJSMIPS_MMI)
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+endif
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+ifeq ($(ENABLE_MSA), Yes)
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+COMMON_OBJS += $(COMMON_OBJSMIPS_MSA)
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+endif
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endif
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-OBJS += $(COMMON_OBJSMIPS)
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+OBJS += $(COMMON_OBJSMIPS_MMI)
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+OBJS += $(COMMON_OBJSMIPS_MSA)
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OBJS += $(COMMON_OBJS)
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diff --git a/codec/decoder/targets.mk b/codec/decoder/targets.mk
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index c01618411..88dc5afb1 100644
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--- a/codec/decoder/targets.mk
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+++ b/codec/decoder/targets.mk
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@@ -57,14 +57,24 @@ DECODER_OBJS += $(DECODER_OBJSARM64)
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endif
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OBJS += $(DECODER_OBJSARM64)
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-DECODER_ASM_MIPS_SRCS=\
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+DECODER_ASM_MIPS_MMI_SRCS=\
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$(DECODER_SRCDIR)/core/mips/dct_mmi.c\
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-DECODER_OBJSMIPS += $(DECODER_ASM_MIPS_SRCS:.c=.$(OBJ))
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+DECODER_OBJSMIPS_MMI += $(DECODER_ASM_MIPS_MMI_SRCS:.c=.$(OBJ))
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+
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+DECODER_ASM_MIPS_MSA_SRCS=\
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+
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+DECODER_OBJSMIPS_MSA += $(DECODER_ASM_MIPS_MSA_SRCS:.c=.$(OBJ))
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ifeq ($(ASM_ARCH), mips)
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-DECODER_OBJS += $(DECODER_OBJSMIPS)
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+ifeq ($(ENABLE_MMI), Yes)
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+DECODER_OBJS += $(DECODER_OBJSMIPS_MMI)
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+endif
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+ifeq ($(ENABLE_MSA), Yes)
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+DECODER_OBJS += $(DECODER_OBJSMIPS_MSA)
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+endif
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endif
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-OBJS += $(DECODER_OBJSMIPS)
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+OBJS += $(DECODER_OBJSMIPS_MMI)
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+OBJS += $(DECODER_OBJSMIPS_MSA)
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OBJS += $(DECODER_OBJS)
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diff --git a/codec/encoder/targets.mk b/codec/encoder/targets.mk
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index 1f053280e..4fb2e690e 100644
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--- a/codec/encoder/targets.mk
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+++ b/codec/encoder/targets.mk
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@@ -82,16 +82,26 @@ ENCODER_OBJS += $(ENCODER_OBJSARM64)
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endif
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OBJS += $(ENCODER_OBJSARM64)
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-ENCODER_ASM_MIPS_SRCS=\
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+ENCODER_ASM_MIPS_MMI_SRCS=\
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$(ENCODER_SRCDIR)/core/mips/dct_mmi.c\
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$(ENCODER_SRCDIR)/core/mips/quant_mmi.c\
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$(ENCODER_SRCDIR)/core/mips/score_mmi.c\
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-ENCODER_OBJSMIPS += $(ENCODER_ASM_MIPS_SRCS:.c=.$(OBJ))
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+ENCODER_OBJSMIPS_MMI += $(ENCODER_ASM_MIPS_MMI_SRCS:.c=.$(OBJ))
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+
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+ENCODER_ASM_MIPS_MSA_SRCS=\
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+
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+ENCODER_OBJSMIPS_MSA += $(ENCODER_ASM_MIPS_MSA_SRCS:.c=.$(OBJ))
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ifeq ($(ASM_ARCH), mips)
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-ENCODER_OBJS += $(ENCODER_OBJSMIPS)
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+ifeq ($(ENABLE_MMI), Yes)
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+ENCODER_OBJS += $(ENCODER_OBJSMIPS_MMI)
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+endif
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+ifeq ($(ENABLE_MSA), Yes)
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+ENCODER_OBJS += $(ENCODER_OBJSMIPS_MSA)
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+endif
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endif
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-OBJS += $(ENCODER_OBJSMIPS)
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+OBJS += $(ENCODER_OBJSMIPS_MMI)
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+OBJS += $(ENCODER_OBJSMIPS_MSA)
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OBJS += $(ENCODER_OBJS)
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diff --git a/codec/processing/targets.mk b/codec/processing/targets.mk
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index 300de2d80..0f8873335 100644
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--- a/codec/processing/targets.mk
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+++ b/codec/processing/targets.mk
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@@ -58,14 +58,24 @@ PROCESSING_OBJS += $(PROCESSING_OBJSARM64)
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endif
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OBJS += $(PROCESSING_OBJSARM64)
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-PROCESSING_ASM_MIPS_SRCS=\
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+PROCESSING_ASM_MIPS_MMI_SRCS=\
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$(PROCESSING_SRCDIR)/src/mips/vaa_mmi.c\
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-PROCESSING_OBJSMIPS += $(PROCESSING_ASM_MIPS_SRCS:.c=.$(OBJ))
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+PROCESSING_OBJSMIPS_MMI += $(PROCESSING_ASM_MIPS_MMI_SRCS:.c=.$(OBJ))
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+
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+PROCESSING_ASM_MIPS_MSA_SRCS=\
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+
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+PROCESSING_OBJSMIPS_MSA += $(PROCESSING_ASM_MIPS_MSA_SRCS:.c=.$(OBJ))
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ifeq ($(ASM_ARCH), mips)
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-PROCESSING_OBJS += $(PROCESSING_OBJSMIPS)
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+ifeq ($(ENABLE_MMI), Yes)
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+PROCESSING_OBJS += $(PROCESSING_OBJSMIPS_MMI)
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+endif
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+ifeq ($(ENABLE_MSA), Yes)
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+PROCESSING_OBJS += $(PROCESSING_OBJSMIPS_MSA)
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+endif
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endif
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-OBJS += $(PROCESSING_OBJSMIPS)
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+OBJS += $(PROCESSING_OBJSMIPS_MMI)
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+OBJS += $(PROCESSING_OBJSMIPS_MSA)
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OBJS += $(PROCESSING_OBJS)
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