Refactor and simplify the CpuInfo class to a stripped down version that only works out the flags it needs to know
JackWright347
parent
93a93b3d17
commit
947bbcc09b
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@ -79,7 +79,7 @@ endif
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# sse41 = yes/no --- -msse4.1 --- Use Intel Streaming SIMD Extensions 4.1
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# avx2 = yes/no --- -mavx2 --- Use Intel Advanced Vector Extensions 2
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# avx512 = yes/no --- -mavx512bw --- Use Intel Advanced Vector Extensions 512
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# vnni256 = yes/no --- -mavx256vnni --- Use Intel Vector Neural Network Instructions 256
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# vnni256 = yes/no --- -mavx512vnni --- Use Intel Vector Neural Network Instructions 256
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# vnni512 = yes/no --- -mavx512vnni --- Use Intel Vector Neural Network Instructions 512
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# neon = yes/no --- -DUSE_NEON --- Use ARM SIMD architecture
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#
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@ -326,7 +326,7 @@ endif
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ifeq ($(COMP),gcc)
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comp=gcc
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CXX=g++
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CXXFLAGS += -pedantic -Wextra -Wshadow -mxsave
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CXXFLAGS += -pedantic -Wextra -Wshadow
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ifeq ($(arch),$(filter $(arch),armv7 armv8))
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ifeq ($(OS),Android)
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@ -368,7 +368,7 @@ ifeq ($(COMP),mingw)
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CXX=g++
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endif
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CXXFLAGS += -Wextra -Wshadow -mxsave
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CXXFLAGS += -Wextra -Wshadow
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LDFLAGS += -static
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endif
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@ -33,10 +33,6 @@ const CpuInfo::CpuId Stockfish::CpuInfo::CPUID;
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__cpuidex(out, eax, ecx);
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}
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uint64_t CpuInfo::xgetbv(unsigned int x) {
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return _xgetbv(x);
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}
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# elif defined(__GNUC__) || defined(__clang__)
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#include <cpuid.h>
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@ -45,12 +41,6 @@ const CpuInfo::CpuId Stockfish::CpuInfo::CPUID;
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__cpuid_count(eax, ecx, out[0], out[1], out[2], out[3]);
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}
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uint64_t CpuInfo::xgetbv(unsigned int index) {
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uint32_t eax, edx;
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__asm__ __volatile__("xgetbv" : "=a"(eax), "=d"(edx) : "c"(index));
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return ((uint64_t)edx << 32) | eax;
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}
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#else
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# message "No CPU-ID intrinsic defined for compiler."
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#endif
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@ -58,82 +48,67 @@ const CpuInfo::CpuId Stockfish::CpuInfo::CPUID;
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# message "No CPU-ID intrinsic defined for processor architecture (currently only x86-32/64 is supported)."
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#endif
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#ifndef _XCR_XFEATURE_ENABLED_MASK
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#define _XCR_XFEATURE_ENABLED_MASK 0
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#endif
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bool CpuInfo::OS_AVX() {
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bool CpuInfo::osAVX() {
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if (OSXSAVE() && AVX())
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{
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const uint64_t xcrFeatureMask = xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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// check for OS-support of YMM state. Necessary for AVX and AVX2.
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return (xcrFeatureMask & 0x06) == 0x06;
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// Check OS has enabled both XMM and YMM state support. Necessary for AVX and AVX2.
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return (xcrFeatureMask() & 0x06) == 0x06;
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}
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return false;
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}
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bool CpuInfo::OS_AVX2() {
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if (OS_AVX())
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bool CpuInfo::osAVX2() {
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if (osAVX())
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{
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return AVX2();
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}
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return false;
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}
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bool CpuInfo::OS_AVX512() {
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if (OS_AVX() && AVX512F() && AVX512DQ() && AVX512CD() && AVX512BW() && AVX512VL())
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bool CpuInfo::osAVX512() {
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if (osAVX() && AVX512F() && AVX512BW())
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{
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const uint64_t xcrFeatureMask = xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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// Check for OS-support of ZMM and YMM state. Necessary for AVX-512.
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return (xcrFeatureMask & 0xE6) == 0xE6;
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return (xcrFeatureMask() & 0xE6) == 0xE6;
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}
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return false;
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}
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std::string CpuInfo::get_info_string() {
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std::string CpuInfo::infoString() {
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std::string s;
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s += "\nVendor: ";
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s += Vendor();
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s += vendor();
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s += ", Family: ";
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s += std::to_string(CPUID._family);
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s += ", Model: ";
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s += std::to_string(CPUID._model);
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s += ", Stepping: ";
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s += std::to_string(CPUID._stepping);
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s += "\n";
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s += "Brand: ";
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s += Brand();
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s += brand();
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s += "\n";
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s += "Hardware Features: ";
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if (X64()) s += "64bit ";
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if (MMX()) s += "MMX ";
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if (ABM()) s += "ABM ";
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if (RDRAND()) s += "RDRAND ";
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if (RDSEED()) s += "RDSEED ";
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if (BMI1()) s += "BMI1 ";
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if (BMI2()) s += "BMI2 ";
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if (ADX()) s += "ADX ";
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if (MPX()) s += "MPX ";
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if (PREFETCHWT1()) s += "PREFETCHWT1 ";
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if (RDPID()) s += "RDPID ";
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if (GFNI()) s += "GFNI ";
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if (VAES()) s += "VAES ";
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if (SSE()) s += "SSE ";
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if (SSE2()) s += "SSE2 ";
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if (SSE3()) s += "SSE3 ";
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if (SSSE3()) s += "SSSE3 ";
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if (SSE4a()) s += "SSE4a ";
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if (SSE41()) s += "SSE4.1 ";
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if (SSE42()) s += "SSE4.2 ";
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if (AES()) s += "AES-NI ";
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if (SHA()) s += "SHA ";
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if (POPCNT()) s += "POPCNT ";
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if (AVX()) s += "AVX ";
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if (AVX2()) s += "AVX2 ";
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if (BMI2()) s += "BMI2 ";
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s += "\n";
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s += "OS + Hardware Features: ";
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(OS_AVX()) ? s += "AVX = yes, " : s += "AVX = no, ";
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(OS_AVX2()) ? s += "AVX2 = yes, " : s += "AVX2 = no, ";
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(OS_AVX512()) ? s += "AVX-512 = yes" : s += "AVX-512 = no";
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s += "OS Supported Features: ";
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(osAVX()) ? s += "AVX = yes, " : s += "AVX = no, ";
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(osAVX2()) ? s += "AVX2 = yes, " : s += "AVX2 = no, ";
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(osAVX512()) ? s += "AVX-512 = yes" : s += "AVX-512 = no";
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s += "\n";
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return s;
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225
src/cpuinfo.h
225
src/cpuinfo.h
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@ -33,89 +33,39 @@ namespace Stockfish {
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class CpuId;
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public:
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static std::string Vendor() { return CPUID._vendor; }
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static std::string Brand() { return CPUID._brand; }
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static std::string get_info_string();
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static std::string vendor() { return CPUID._vendor; }
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static std::string brand() { return CPUID._brand; }
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static std::string infoString();
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static bool isIntel() { return CPUID._isIntel; }
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static bool isAMD() { return CPUID._isAMD; }
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static bool isAMDZen3() { return CPUID._isAMD && CPUID._family > 24; }
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static bool OS_AVX();
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static bool OS_AVX2();
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static bool OS_AVX512();
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static bool isIntel() { return CPUID._isIntel; }
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static bool isAMD() { return CPUID._isAMD; }
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static bool isAMDZen3() { return CPUID._isAMD && CPUID._family > 24; }
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static bool osAVX();
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static bool osAVX2();
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static bool osAVX512();
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// flags reported by function 0x01
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static bool SSE3() { return CPUID._f1_ECX[0]; } // -msse3
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static bool SSSE3() { return CPUID._f1_ECX[9]; } // -DUSE_SSSE3 -mssse3
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static bool SSE41() { return CPUID._f1_ECX[19]; } // -DUSE_SSE41 -msse4.1
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static bool POPCNT() { return CPUID._f1_ECX[23]; } // -DUSE_POPCNT -mpopcnt
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static bool OSXSAVE() { return CPUID._f1_ECX[27]; } // OS uses XSAVE/XRSTOR
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static bool AVX() { return CPUID._f1_ECX[28]; } // AVX supported by CPU
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static bool MMX() { return CPUID._f1_EDX[23]; } // -DUSE_MMX -mmmx
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static bool SSE() { return CPUID._f1_EDX[25]; } // -msse
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static bool SSE2() { return CPUID._f1_EDX[26]; } // -DUSE_SSE2 -msse2
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// flags reported by function 0x07
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static bool AVX2() { return CPUID._f7_EBX[5]; } // -mavx2
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static bool BMI2() { return CPUID._f7_EBX[8]; } // -DUSE_PEXT -mbmi2
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static bool AVX512F() { return CPUID._f7_EBX[16]; } // -mavx512f
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static bool AVX512DQ() { return CPUID._f7_EBX[17]; } // -mavx512dq
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static bool AVX512BW() { return CPUID._f7_EBX[30]; } // -mavx512bw
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static bool AVX512VL() { return CPUID._f7_EBX[31]; } // -mavx512vl
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static bool AVX512VNNI() { return CPUID._f7_ECX[11]; } // -mavx512vnni
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// flags reported by function 0x0D
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// flags reported by function 0x00000001
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static bool SSE3() { return CPUID._f1_ECX[0]; }
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static bool PCLMULQDQ() { return CPUID._f1_ECX[1]; }
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static bool MONITOR() { return CPUID._f1_ECX[3]; }
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static bool SSSE3() { return CPUID._f1_ECX[9]; }
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static bool FMA3() { return CPUID._f1_ECX[12]; }
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static bool CMPXCHG16B() { return CPUID._f1_ECX[13]; }
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static bool SSE41() { return CPUID._f1_ECX[19]; }
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static bool SSE42() { return CPUID._f1_ECX[20]; }
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static bool MOVBE() { return CPUID._f1_ECX[22]; }
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static bool POPCNT() { return CPUID._f1_ECX[23]; }
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static bool AES() { return CPUID._f1_ECX[25]; }
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static bool XSAVE() { return CPUID._f1_ECX[26]; }
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static bool OSXSAVE() { return CPUID._f1_ECX[27]; }
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static bool AVX() { return CPUID._f1_ECX[28]; }
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static bool F16C() { return CPUID._f1_ECX[29]; }
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static bool RDRAND() { return CPUID._f1_ECX[30]; }
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static bool MSR() { return CPUID._f1_EDX[5]; }
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static bool CX8() { return CPUID._f1_EDX[8]; }
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static bool SEP() { return CPUID._f1_EDX[11]; }
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static bool CMOV() { return CPUID._f1_EDX[15]; }
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static bool CLFSH() { return CPUID._f1_EDX[19]; }
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static bool MMX() { return CPUID._f1_EDX[23]; }
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static bool FXSR() { return CPUID._f1_EDX[24]; }
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static bool SSE() { return CPUID._f1_EDX[25]; }
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static bool SSE2() { return CPUID._f1_EDX[26]; }
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// flags reported by function 0x00000007
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static bool FSGSBASE() { return CPUID._f7_EBX[0]; }
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static bool BMI1() { return CPUID._f7_EBX[3]; }
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static bool HLE() { return CPUID._isIntel && CPUID._f7_EBX[4]; }
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static bool AVX2() { return CPUID._f7_EBX[5]; }
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static bool BMI2() { return CPUID._f7_EBX[8]; }
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static bool ERMS() { return CPUID._f7_EBX[9]; }
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static bool INVPCID() { return CPUID._f7_EBX[10]; }
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static bool RTM() { return CPUID._isIntel && CPUID._f7_EBX[11]; }
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static bool MPX() { return CPUID._f7_EBX[14]; }
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static bool AVX512F() { return CPUID._f7_EBX[16]; }
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static bool AVX512DQ() { return CPUID._f7_EBX[17]; }
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static bool RDSEED() { return CPUID._f7_EBX[18]; }
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static bool ADX() { return CPUID._f7_EBX[19]; }
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static bool AVX512IFMA() { return CPUID._f7_EBX[21]; }
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static bool AVX512PF() { return CPUID._f7_EBX[26]; }
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static bool AVX512ER() { return CPUID._f7_EBX[27]; }
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static bool AVX512CD() { return CPUID._f7_EBX[28]; }
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static bool SHA() { return CPUID._f7_EBX[29]; }
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static bool AVX512BW() { return CPUID._f7_EBX[30]; }
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static bool AVX512VL() { return CPUID._f7_EBX[31]; }
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static bool PREFETCHWT1() { return CPUID._f7_ECX[0]; }
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static bool AVX512VBMI() { return CPUID._f7_ECX[1]; }
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static bool AVX512VBMI2() { return CPUID._f7_ECX[6]; }
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static bool GFNI() { return CPUID._f7_ECX[8]; }
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static bool VAES() { return CPUID._f7_ECX[9]; }
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static bool AVX512VPCLMUL() { return CPUID._f7_ECX[10]; }
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static bool AVX512VNNI() { return CPUID._f7_ECX[11]; }
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static bool AVX512BITALG() { return CPUID._f7_ECX[12]; }
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static bool AVX512VPOPCNTDQ() { return CPUID._f7_ECX[14]; }
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static bool RDPID() { return CPUID._f7_ECX[22]; }
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static bool AVX5124FMAPS() { return CPUID._f7_EDX[2]; }
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static bool AVX5124VNNIW() { return CPUID._f7_EDX[3]; }
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// flags reported by extended function 0x80000001
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static bool LAHF() { return CPUID._f81_ECX[0]; }
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static bool ABM() { return CPUID._f81_ECX[5]; }
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static bool SSE4a() { return CPUID._f81_ECX[6]; }
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static bool XOP() { return CPUID._f81_ECX[11]; }
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static bool FMA4() { return CPUID._f81_ECX[16]; }
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static bool TBM() { return CPUID._f81_ECX[21]; }
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static bool SYSCALL() { return CPUID._isIntel && CPUID._f81_EDX[11]; }
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static bool MMXEXT() { return CPUID._isAMD && CPUID._f81_EDX[22]; }
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static bool RDTSCP() { return CPUID._isIntel && CPUID._f81_EDX[27]; }
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static bool X64() { return CPUID._isIntel && CPUID._f81_EDX[29]; }
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static bool _3DNOWEXT() { return CPUID._isAMD && CPUID._f81_EDX[30]; }
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static bool _3DNOW() { return CPUID._isAMD && CPUID._f81_EDX[31]; }
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static bool X64() { return CPUID._f81_EDX[29]; } // -DIS_64BIT
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private:
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static const CpuId CPUID;
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@ -129,23 +79,19 @@ namespace Stockfish {
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_isIntel{ false },
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_isAMD{ false },
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_f1_EAX{ 0 },
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_f1_EBX{ 0 },
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_f1_ECX{ 0 },
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_f1_EDX{ 0 },
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_f7_EAX{ 0 },
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_f7_EBX{ 0 },
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_f7_ECX{ 0 },
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_f7_EDX{ 0 },
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_f81_EAX{ 0 },
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_f81_EBX{ 0 },
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_f81_ECX{ 0 },
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_fD_EAX{ 0 },
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_fD_EDX{ 0 },
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_f81_EDX{ 0 },
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_data{},
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_dataExt{},
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_family{ 0 },
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_model{ 0 },
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_ext_family{ 0 },
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_ext_model{ 0 }
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_stepping{ 0 }
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{
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std::array<int32_t, 4> info;
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@ -176,24 +122,29 @@ namespace Stockfish {
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_isAMD = true;
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}
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// load bitset with flags for function 0x00000001
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if (_idMax >= 1)
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// load bitsets with flags for function 0x01
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if (_idMax >= 0x01)
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{
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_f1_EAX = _data[1][0];
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_f1_EBX = _data[1][1];
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_f1_ECX = _data[1][2];
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_f1_EDX = _data[1][3];
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}
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// load bitset with flags for function 0x00000007
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if (_idMax >= 7)
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// load bitsets with flags for function 0x07
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if (_idMax >= 0x07)
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{
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_f7_EAX = _data[7][0];
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_f7_EBX = _data[7][1];
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_f7_ECX = _data[7][2];
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_f7_EDX = _data[7][3];
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}
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// load output of function 0x0D
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if (_idMax >= 0x0D)
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{
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_fD_EAX = _data[13][0];
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_fD_EDX = _data[13][3];
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}
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// calling cpuid with 0x80000000
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// gets the number of the highest valid extended function ID
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cpuid(info.data(), 0x80000000, 0);
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@ -208,9 +159,6 @@ namespace Stockfish {
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// load bitset with flags for extended function 0x80000001
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if (_idExtMax >= 0x80000001)
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{
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_f81_EAX = _dataExt[1][0];
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_f81_EBX = _dataExt[1][1];
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_f81_ECX = _dataExt[1][2];
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_f81_EDX = _dataExt[1][3];
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}
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@ -225,69 +173,60 @@ namespace Stockfish {
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}
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// compute X86 Family and Model
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const int32_t signature = _data[1][0];
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_family = (signature >> 8) & 0x0F;
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_model = (signature >> 4) & 0x0F;
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_ext_family = 0;
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_ext_model = 0;
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// The "Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2A"
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// specifies the Extended Model is defined only when the Base Family is
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// 06h or 0Fh.
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// The "AMD CPUID Specification" specifies that the Extended Model is
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// defined only when Base Family is 0Fh.
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// Both manuals define the display model as
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// {ExtendedModel[3:0],BaseModel[3:0]} in that case.
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_family = (_f1_EAX >> 8) & 0x0F;
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_model = (_f1_EAX >> 4) & 0x0F;
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_stepping = _f1_EAX & 0x0F;
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int32_t ext_family = 0;
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int32_t ext_model = 0;
|
||||
// The "Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2A" specifies the Extended Model
|
||||
// is defined only when the Base Family is 06h or 0Fh.
|
||||
// The "AMD CPUID Specification" specifies that the Extended Model is defined only when Base Family is 0Fh.
|
||||
// Both manuals define the display model as {ExtendedModel[3:0],BaseModel[3:0]} in that case.
|
||||
if (_family == 0x0F || (_family == 0x06 && _isIntel))
|
||||
{
|
||||
_ext_model = (signature >> 16) & 0x0F;
|
||||
_model += _ext_model << 4;
|
||||
ext_model = (_f1_EAX >> 16) & 0x0F;
|
||||
_model += ext_model << 4;
|
||||
}
|
||||
// Both the "Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2A"
|
||||
// and the "AMD CPUID Specification" specify that the Extended Family is
|
||||
// defined only when the Base Family is 0Fh.
|
||||
// Both manuals define the display family as {0000b,BaseFamily[3:0]} +
|
||||
// ExtendedFamily[7:0] in that case.
|
||||
// Both the "Intel 64 and IA-32 Architectures Developer's Manual: Vol. 2A" and the "AMD CPUID Specification"
|
||||
// specify that the Extended Family is defined only when the Base Family is 0Fh.
|
||||
// Both manuals define the display family as {0000b,BaseFamily[3:0]} + ExtendedFamily[7:0] in that case.
|
||||
if (_family == 0x0F)
|
||||
{
|
||||
_ext_family = (signature >> 20) & 0xFF;
|
||||
_family += _ext_family;
|
||||
ext_family = (_f1_EAX >> 20) & 0xFF;
|
||||
_family += ext_family;
|
||||
}
|
||||
};
|
||||
|
||||
uint32_t _idMax;
|
||||
uint32_t _idExtMax;
|
||||
bool _isIntel;
|
||||
bool _isAMD;
|
||||
|
||||
std::bitset<32> _f1_EAX;
|
||||
std::bitset<32> _f1_EBX;
|
||||
std::bitset<32> _f1_ECX;
|
||||
std::bitset<32> _f1_EDX;
|
||||
|
||||
std::bitset<32> _f7_EAX;
|
||||
std::bitset<32> _f7_EBX;
|
||||
std::bitset<32> _f7_ECX;
|
||||
std::bitset<32> _f7_EDX;
|
||||
|
||||
std::bitset<32> _f81_EAX;
|
||||
std::bitset<32> _f81_EBX;
|
||||
std::bitset<32> _f81_ECX;
|
||||
std::bitset<32> _f81_EDX;
|
||||
|
||||
std::vector<std::array<int32_t, 4>> _data;
|
||||
std::vector<std::array<int32_t, 4>> _dataExt;
|
||||
|
||||
std::string _vendor;
|
||||
std::string _brand;
|
||||
|
||||
bool _isIntel;
|
||||
bool _isAMD;
|
||||
|
||||
int32_t _family;
|
||||
int32_t _model;
|
||||
int32_t _ext_family;
|
||||
int32_t _ext_model;
|
||||
int32_t _stepping;
|
||||
|
||||
int32_t _f1_EAX;
|
||||
std::bitset<32> _f1_ECX;
|
||||
std::bitset<32> _f1_EDX;
|
||||
std::bitset<32> _f7_EBX;
|
||||
std::bitset<32> _f7_ECX;
|
||||
std::bitset<32> _f7_EDX;
|
||||
int32_t _fD_EAX;
|
||||
int32_t _fD_EDX;
|
||||
std::bitset<32> _f81_EDX;
|
||||
|
||||
private:
|
||||
uint32_t _idMax;
|
||||
uint32_t _idExtMax;
|
||||
std::vector<std::array<int32_t, 4>> _data;
|
||||
std::vector<std::array<int32_t, 4>> _dataExt;
|
||||
};
|
||||
|
||||
private:
|
||||
static void cpuid(int32_t out[4], int32_t eax, int32_t ecx);
|
||||
static uint64_t xgetbv(unsigned int x);
|
||||
static inline uint64_t xcrFeatureMask() { return ((uint64_t)CPUID._fD_EDX << 32) | CPUID._fD_EAX; } // XCR0 XFEATURE_ENABLED_MASK
|
||||
};
|
||||
} // namespace Stockfish
|
||||
|
||||
|
|
|
|||
|
|
@ -278,7 +278,7 @@ void UCI::loop(int argc, char* argv[]) {
|
|||
else if (token == "d") sync_cout << pos << sync_endl;
|
||||
else if (token == "eval") trace_eval(pos);
|
||||
else if (token == "compiler") sync_cout << compiler_info() << sync_endl;
|
||||
else if (token == "cpu") sync_cout << CpuInfo::get_info_string() << sync_endl;
|
||||
else if (token == "cpu") sync_cout << CpuInfo::infoString() << sync_endl;
|
||||
else if (token == "export_net")
|
||||
{
|
||||
std::optional<std::string> filename;
|
||||
|
|
|
|||
Loading…
Reference in New Issue