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stm32/boards: Add STM32L432KC chip configuration files. 

The pin alternate function information is derived from ST's datasheet
https://www.st.com/resource/en/datasheet/stm32l432kc.pdf
In the datasheet, the line 2 of AF4 includes I2C2 but actually the chip
does not have I2C2 so it is removed.
pull/1/head
boochow 2018-12-01 09:26:04 +09:00 committed by Damien George
parent 52bec93755
commit 1a8baad7ca
2 changed files with 55 additions and 0 deletions
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27
ports/stm32/boards/stm32l432.ld 100644
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/*
GNU linker script for STM32L432KC
*/
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 256K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K
SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 16K
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 16K;
/* Define the top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_start = _ebss; /* heap starts just after statically allocated memory */
_heap_end = 0x2000A800; /* room for a 6k stack */

28
ports/stm32/boards/stm32l432_af.csv 100644
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Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,,,
,,SYS_AF,TIM1/TIM2/LPTIM1,TIM1/TIM2,USART2,I2C1/I2C2/I2C3,SPI1/SPI2,SPI3,USART1/USART2/USART3,LPUART1,CAN1/TSC,USB/QUADSPI,,COMP1/COMP2/SWPMI1,SAI1,TIM2/TIM15/TIM16/LPTIM2,EVENTOUT,ADC,COMP,DAC
PortA,PA0,,TIM2_CH1,,,,,,USART2_CTS,,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT,ADC1_IN5,COMP1_INM,
PortA,PA1,,TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS/USART2_DE,,,,,,,TIM15_CH1N,EVENTOUT,ADC1_IN6,COMP1_INP,
PortA,PA2,,TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,TIM15_CH1,EVENTOUT,ADC1_IN7,COMP2_INM,
PortA,PA3,,TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT,ADC1_IN8,COMP2_INP,
PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT,ADC1_IN9,COMP1_INM/COMP2_INM,DAC1_OUT1
PortA,PA5,,TIM2_CH1,TIM2_ETR,,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT,ADC1_IN10,COMP1_INM/COMP2_INM,DAC1_OUT2
PortA,PA6,,TIM1_BKIN,,,,SPI1_MISO,COMP1_OUT,USART3_CTS,,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT,ADC1_IN11,,
PortA,PA7,,TIM1_CH1N,,,I2C3_SCL,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,,COMP2_OUT,,,EVENTOUT,ADC1_IN12,,
PortA,PA8,MCO,TIM1_CH1,,,,,,USART1_CK,,,,,SWPMI1_IO,SAI1_SCLK_A,LPTIM2_OUT,EVENTOUT,,,
PortA,PA9,,TIM1_CH2,,,I2C1_SCL,,,USART1_TX,,,,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT,,,
PortA,PA10,,TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,USB_CRS_SYNC,,,SAI1_SD_A,,EVENTOUT,,,
PortA,PA11,,TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,USB_DM,,TIM1_BKIN2_COMP1,,,EVENTOUT,,,
PortA,PA12,,TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS/USART1_DE,,CAN1_TX,USB_DP,,,,,EVENTOUT,,,
PortA,PA13,JTMS/SWDIO,IR_OUT,,,,,,,,,USB_NOE,,SWPMI1_TX,,,EVENTOUT,,,
PortA,PA14,JTCK/SWCLK,LPTIM1_OUT,,,I2C1_SMBA,,,,,,,,SWPMI1_RX,SAI1_SD_B,,EVENTOUT,,,
PortA,PA15,JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS/USART3_DE,,TSC_G3_IO1,,,SWPMI1_SUSPEND,SAI1_FS_B,,EVENTOUT,,,
PortB,PB0,,TIM1_CH2N,,,,SPI1_NSS,,USART3_CK,,,QUADSPI_BK1_IO1,,COMP1_OUT,SA1_EXTCLK,,EVENTOUT,ADC1_IN15,,
PortB,PB1,,TIM1_CH3N,,,,,,USART3_RTS/USART3_DE,LPUART1_RTS/LPUART1_DE,,QUADSPI_BK1_IO0,,,,LPTIM2_IN1,EVENTOUT,ADC1_IN16,COMP1_INM,
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS/USART1_DE,,,,,,SAI1_SCK_B,,EVENTOUT,,COMP2_INM,
PortB,PB4,NJTRST,,,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,,TSC_G2_IO1,,,,SAI1_MCLK_B,,EVENTOUT,,COMP2_INP,
PortB,PB5,,LPTIM1_IN1,,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,,TSC_G2_IO2,,,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT,,,
PortB,PB6,,LPTIM1_ETR,,,I2C1_SCL,,,USART1_TX,,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N,EVENTOUT,,COMP2_INP,
PortB,PB7,,LPTIM1_IN2,,,I2C1_SDA,,,USART1_RX,,TSC_G2_IO4,,,,,,EVENTOUT,,COMP2_INM,
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,,,
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,,,
PortH,PH3,,,,,,,,,,,,,,,,EVENTOUT,,,
1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
2 SYS_AF TIM1/TIM2/LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3 USART1/USART2/USART3 LPUART1 CAN1/TSC USB/QUADSPI COMP1/COMP2/SWPMI1 SAI1 TIM2/TIM15/TIM16/LPTIM2 EVENTOUT ADC COMP DAC
3 PortA PA0 TIM2_CH1 USART2_CTS COMP1_OUT SAI1_EXTCLK TIM2_ETR EVENTOUT ADC1_IN5 COMP1_INM
4 PortA PA1 TIM2_CH2 I2C1_SMBA SPI1_SCK USART2_RTS/USART2_DE TIM15_CH1N EVENTOUT ADC1_IN6 COMP1_INP
5 PortA PA2 TIM2_CH3 USART2_TX LPUART1_TX QUADSPI_BK1_NCS COMP2_OUT TIM15_CH1 EVENTOUT ADC1_IN7 COMP2_INM
6 PortA PA3 TIM2_CH4 USART2_RX LPUART1_RX QUADSPI_CLK SAI1_MCLK_A TIM15_CH2 EVENTOUT ADC1_IN8 COMP2_INP
7 PortA PA4 SPI1_NSS SPI3_NSS USART2_CK SAI1_FS_B LPTIM2_OUT EVENTOUT ADC1_IN9 COMP1_INM/COMP2_INM DAC1_OUT1
8 PortA PA5 TIM2_CH1 TIM2_ETR SPI1_SCK LPTIM2_ETR EVENTOUT ADC1_IN10 COMP1_INM/COMP2_INM DAC1_OUT2
9 PortA PA6 TIM1_BKIN SPI1_MISO COMP1_OUT USART3_CTS QUADSPI_BK1_IO3 TIM1_BKIN_COMP2 TIM16_CH1 EVENTOUT ADC1_IN11
10 PortA PA7 TIM1_CH1N I2C3_SCL SPI1_MOSI QUADSPI_BK1_IO2 COMP2_OUT EVENTOUT ADC1_IN12
11 PortA PA8 MCO TIM1_CH1 USART1_CK SWPMI1_IO SAI1_SCLK_A LPTIM2_OUT EVENTOUT
12 PortA PA9 TIM1_CH2 I2C1_SCL USART1_TX SAI1_FS_A TIM15_BKIN EVENTOUT
13 PortA PA10 TIM1_CH3 I2C1_SDA USART1_RX USB_CRS_SYNC SAI1_SD_A EVENTOUT
14 PortA PA11 TIM1_CH4 TIM1_BKIN2 SPI1_MISO COMP1_OUT USART1_CTS CAN1_RX USB_DM TIM1_BKIN2_COMP1 EVENTOUT
15 PortA PA12 TIM1_ETR SPI1_MOSI USART1_RTS/USART1_DE CAN1_TX USB_DP EVENTOUT
16 PortA PA13 JTMS/SWDIO IR_OUT USB_NOE SWPMI1_TX EVENTOUT
17 PortA PA14 JTCK/SWCLK LPTIM1_OUT I2C1_SMBA SWPMI1_RX SAI1_SD_B EVENTOUT
18 PortA PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX SPI1_NSS SPI3_NSS USART3_RTS/USART3_DE TSC_G3_IO1 SWPMI1_SUSPEND SAI1_FS_B EVENTOUT
19 PortB PB0 TIM1_CH2N SPI1_NSS USART3_CK QUADSPI_BK1_IO1 COMP1_OUT SA1_EXTCLK EVENTOUT ADC1_IN15
20 PortB PB1 TIM1_CH3N USART3_RTS/USART3_DE LPUART1_RTS/LPUART1_DE QUADSPI_BK1_IO0 LPTIM2_IN1 EVENTOUT ADC1_IN16 COMP1_INM
21 PortB PB3 JTDO/TRACESWO TIM2_CH2 SPI1_SCK SPI3_SCK USART1_RTS/USART1_DE SAI1_SCK_B EVENTOUT COMP2_INM
22 PortB PB4 NJTRST I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS TSC_G2_IO1 SAI1_MCLK_B EVENTOUT COMP2_INP
23 PortB PB5 LPTIM1_IN1 I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK TSC_G2_IO2 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT
24 PortB PB6 LPTIM1_ETR I2C1_SCL USART1_TX TSC_G2_IO3 SAI1_FS_B TIM16_CH1N EVENTOUT COMP2_INP
25 PortB PB7 LPTIM1_IN2 I2C1_SDA USART1_RX TSC_G2_IO4 EVENTOUT COMP2_INM
26 PortC PC14 EVENTOUT
27 PortC PC15 EVENTOUT
28 PortH PH3 EVENTOUT