diff --git a/stmhal/Makefile b/stmhal/Makefile index 892ed74b3..4daf665fa 100644 --- a/stmhal/Makefile +++ b/stmhal/Makefile @@ -129,6 +129,7 @@ SRC_HAL = $(addprefix $(HAL_DIR)/src/,\ stm32f4xx_hal_gpio.c \ stm32f4xx_hal_i2c.c \ stm32f4xx_hal_pcd.c \ + stm32f4xx_hal_pcd_ex.c \ stm32f4xx_hal_rcc.c \ stm32f4xx_hal_rcc_ex.c \ stm32f4xx_hal_rng.c \ diff --git a/stmhal/boards/HYDRABUS/stm32f4xx_hal_conf.h b/stmhal/boards/HYDRABUS/stm32f4xx_hal_conf.h index 225703d24..363b4c9a9 100644 --- a/stmhal/boards/HYDRABUS/stm32f4xx_hal_conf.h +++ b/stmhal/boards/HYDRABUS/stm32f4xx_hal_conf.h @@ -1,393 +1,408 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @author MCD Application Team - * @version V1.0.1 - * @date 26-February-2014 - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -#define STM32F405xx -#define USE_USB_FS - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -#define HAL_CAN_MODULE_ENABLED -#define HAL_CRC_MODULE_ENABLED -#define HAL_CRYP_MODULE_ENABLED -#define HAL_DAC_MODULE_ENABLED -#define HAL_DCMI_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -#define HAL_ETH_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_NAND_MODULE_ENABLED -#define HAL_NOR_MODULE_ENABLED -#define HAL_PCCARD_MODULE_ENABLED -#define HAL_SRAM_MODULE_ENABLED -/* #define HAL_SDRAM_MODULE_ENABLED */ -#define HAL_HASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -#define HAL_I2S_MODULE_ENABLED -#define HAL_IWDG_MODULE_ENABLED -#define HAL_LTDC_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_RNG_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -/* #define HAL_SAI_MODULE_ENABLED */ -#define HAL_SD_MODULE_ENABLED -#define HAL_SPI_MODULE_ENABLED -#define HAL_TIM_MODULE_ENABLED -#define HAL_UART_MODULE_ENABLED -#define HAL_USART_MODULE_ENABLED -#define HAL_IRDA_MODULE_ENABLED -#define HAL_SMARTCARD_MODULE_ENABLED -#define HAL_WWDG_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_PCD_MODULE_ENABLED -#define HAL_HCD_MODULE_ENABLED - - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 -#define INSTRUCTION_CACHE_ENABLE 1 -#define DATA_CACHE_ENABLE 1 - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1 */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2 -#define MAC_ADDR1 0 -#define MAC_ADDR2 0 -#define MAC_ADDR3 0 -#define MAC_ADDR4 0 -#define MAC_ADDR5 0 - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01 -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FF) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) - -#define PHY_READ_TO ((uint32_t)0x0000FFFF) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-June-2014 + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +#define STM32F405xx +#define USE_USB_FS + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_PCCARD_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +/* #define HAL_SDRAM_MODULE_ENABLED */ +#define HAL_HASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 1 +#define DATA_CACHE_ENABLE 1 + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stmhal/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h b/stmhal/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h index a90bcf28a..8d1563566 100644 --- a/stmhal/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h +++ b/stmhal/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @version V1.0.1 - * @date 26-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -117,6 +117,21 @@ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + /** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source @@ -134,6 +149,7 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */ #define USE_RTOS 0 #define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 1 @@ -380,8 +396,7 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/stmhal/boards/PYBV10/stm32f4xx_hal_conf.h b/stmhal/boards/PYBV10/stm32f4xx_hal_conf.h index 315c24dc6..363b4c9a9 100644 --- a/stmhal/boards/PYBV10/stm32f4xx_hal_conf.h +++ b/stmhal/boards/PYBV10/stm32f4xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @version V1.0.1 - * @date 26-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -116,6 +116,21 @@ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + /** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source @@ -133,6 +148,7 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */ #define USE_RTOS 0 #define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 1 @@ -379,8 +395,7 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/stmhal/boards/PYBV3/stm32f4xx_hal_conf.h b/stmhal/boards/PYBV3/stm32f4xx_hal_conf.h index 315c24dc6..363b4c9a9 100644 --- a/stmhal/boards/PYBV3/stm32f4xx_hal_conf.h +++ b/stmhal/boards/PYBV3/stm32f4xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @version V1.0.1 - * @date 26-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -116,6 +116,21 @@ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + /** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source @@ -133,6 +148,7 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */ #define USE_RTOS 0 #define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 1 @@ -379,8 +395,7 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/stmhal/boards/PYBV4/stm32f4xx_hal_conf.h b/stmhal/boards/PYBV4/stm32f4xx_hal_conf.h index 315c24dc6..363b4c9a9 100644 --- a/stmhal/boards/PYBV4/stm32f4xx_hal_conf.h +++ b/stmhal/boards/PYBV4/stm32f4xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @version V1.0.1 - * @date 26-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -116,6 +116,21 @@ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + /** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source @@ -133,6 +148,7 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */ #define USE_RTOS 0 #define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 1 @@ -379,8 +395,7 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/stmhal/boards/STM32F4DISC/stm32f4xx_hal_conf.h b/stmhal/boards/STM32F4DISC/stm32f4xx_hal_conf.h index 075b44dbc..9f22cd048 100644 --- a/stmhal/boards/STM32F4DISC/stm32f4xx_hal_conf.h +++ b/stmhal/boards/STM32F4DISC/stm32f4xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @version V1.0.1 - * @date 26-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -116,6 +116,21 @@ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + /** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source @@ -133,6 +148,7 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */ #define USE_RTOS 0 #define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 1 @@ -379,8 +395,7 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/stmhal/cmsis/devinc/stm32f401xc.h b/stmhal/cmsis/devinc/stm32f401xc.h index 3141f0e06..62a51744c 100644 --- a/stmhal/cmsis/devinc/stm32f401xc.h +++ b/stmhal/cmsis/devinc/stm32f401xc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f401xc.h * @author MCD Application Team - * @version V2.0.0 - * @date 18-February-2014 + * @version V2.1.0 + * @date 19-June-2014 * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File. * * This file contains: @@ -536,20 +536,6 @@ typedef struct __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; - - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - - /** * @brief __USB_OTG_Core_register @@ -689,6 +675,7 @@ USB_OTG_HostChannelTypeDef; #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE @@ -763,9 +750,6 @@ USB_OTG_HostChannelTypeDef; #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -/*!< AHB2 peripherals */ -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0xE0042000) @@ -847,8 +831,7 @@ USB_OTG_HostChannelTypeDef; #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) @@ -1971,6 +1954,24 @@ USB_OTG_HostChannelTypeDef; #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /******************************************************************************/ /* */ @@ -2121,6 +2122,9 @@ USB_OTG_HostChannelTypeDef; #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */ +#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */ +#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */ +#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */ #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */ #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */ @@ -2335,7 +2339,6 @@ USB_OTG_HostChannelTypeDef; #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) /******************** Bit definition for RCC_AHB2RSTR register **************/ -#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) /******************** Bit definition for RCC_AHB3RSTR register **************/ @@ -2384,7 +2387,6 @@ USB_OTG_HostChannelTypeDef; #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) /******************** Bit definition for RCC_AHB2ENR register ***************/ -#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) /******************** Bit definition for RCC_AHB3ENR register ***************/ @@ -2433,7 +2435,6 @@ USB_OTG_HostChannelTypeDef; #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) /******************** Bit definition for RCC_AHB2LPENR register *************/ -#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) /******************** Bit definition for RCC_AHB3LPENR register *************/ @@ -2513,22 +2514,6 @@ USB_OTG_HostChannelTypeDef; #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000) #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000) -/******************************************************************************/ -/* */ -/* RNG */ -/* */ -/******************************************************************************/ -/******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN ((uint32_t)0x00000004) -#define RNG_CR_IE ((uint32_t)0x00000008) - -/******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY ((uint32_t)0x00000001) -#define RNG_SR_CECS ((uint32_t)0x00000002) -#define RNG_SR_SECS ((uint32_t)0x00000004) -#define RNG_SR_CEIS ((uint32_t)0x00000020) -#define RNG_SR_SEIS ((uint32_t)0x00000040) - /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ @@ -3166,10 +3151,7 @@ USB_OTG_HostChannelTypeDef; #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) /****************** Bit definition for SYSCFG_PMC register ******************/ -#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */ #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */ -#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */ -#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */ /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f401xe + * @{ + */ + +#ifndef __STM32F401xE_H +#define __STM32F401xE_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief __USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */ + uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */ + __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */ + uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} +USB_OTG_GlobalTypeDef; + + + +/** + * @brief __device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ + __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */ + uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */ + __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */ + uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */ + uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */ + __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ + uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ + uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ +} +USB_OTG_DeviceTypeDef; + + +/** + * @brief __IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} +USB_OTG_INEndpointTypeDef; + + +/** + * @brief __OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} +USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief __Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} +USB_OTG_HostTypeDef; + + +/** + * @brief __Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} +USB_OTG_HostChannelTypeDef; + + +/** + * @brief Peripheral_memory_map + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) + +#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) +#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) +#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) +#define USB_OTG_HOST_BASE ((uint32_t )0x400) +#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) +#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) +#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) +#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*! #include #include @@ -73,6 +74,7 @@ STATIC DAC_HandleTypeDef DAC_Handle; void dac_init(void) { + memset(&DAC_Handle, 0, sizeof DAC_Handle); DAC_Handle.Instance = DAC; DAC_Handle.State = HAL_DAC_STATE_RESET; HAL_DAC_Init(&DAC_Handle); @@ -142,7 +144,10 @@ STATIC mp_obj_t pyb_dac_make_new(mp_obj_t type_in, uint n_args, uint n_kw, const // stop anything already going on HAL_DAC_Stop(&DAC_Handle, dac->dac_channel); - HAL_DAC_Stop_DMA(&DAC_Handle, dac->dac_channel); + if ((dac->dac_channel == DAC_CHANNEL_1 && DAC_Handle.DMA_Handle1 != NULL) + || (dac->dac_channel == DAC_CHANNEL_2 && DAC_Handle.DMA_Handle2 != NULL)) { + HAL_DAC_Stop_DMA(&DAC_Handle, dac->dac_channel); + } dac->state = 0; diff --git a/stmhal/hal/inc/stm32f4xx_hal.h b/stmhal/hal/inc/stm32f4xx_hal.h index 2da0680c9..f3a3f9783 100644 --- a/stmhal/hal/inc/stm32f4xx_hal.h +++ b/stmhal/hal/inc/stm32f4xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -152,11 +152,14 @@ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); /* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); +void HAL_IncTick(void); +void HAL_Delay(__IO uint32_t Delay); uint32_t HAL_GetTick(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); diff --git a/stmhal/hal/inc/stm32f4xx_hal_adc.h b/stmhal/hal/inc/stm32f4xx_hal_adc.h index 581efeb84..320226431 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_adc.h +++ b/stmhal/hal/inc/stm32f4xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention @@ -139,9 +139,9 @@ typedef struct */ typedef struct { - uint32_t Channel; /*!< The ADC channel to configure + uint32_t Channel; /*!< The ADC channel to configure. This parameter can be a value of @ref ADC_channels */ - uint32_t Rank; /*!< The rank in the regular group sequencer + uint32_t Rank; /*!< The rank in the regular group sequencer. This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel. This parameter can be a value of @ref ADC_sampling_times */ @@ -154,14 +154,14 @@ typedef struct typedef struct { uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. - This parameter can be a value of @ref ADC_analog_watchdog_selection. */ + This parameter can be a value of @ref ADC_analog_watchdog_selection */ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a 12-bit value. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a 12-bit value. */ uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel - This parameter can be a value of @ref ADC_channels. */ + This parameter can be a value of @ref ADC_channels */ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured is interrupt mode or in polling mode. This parameter can be set to ENABLE or DISABLE */ @@ -538,6 +538,13 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset ADC handle state + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) + /** * @brief Enable the ADC peripheral. * @param __HANDLE__: ADC handle @@ -663,7 +670,7 @@ typedef struct * @param __FLAG__: ADC flag. * @retval None */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__)) +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** * @brief Get the selected ADC's flag status. diff --git a/stmhal/hal/inc/stm32f4xx_hal_adc_ex.h b/stmhal/hal/inc/stm32f4xx_hal_adc_ex.h index 785ef0e87..3559847dd 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_adc_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -61,8 +61,8 @@ */ typedef struct { - uint32_t InjectedChannel; /*!< Configure the ADC injected channel - This parameter can be a value of @ref ADC_channels. */ + uint32_t InjectedChannel; /*!< Configure the ADC injected channel. + This parameter can be a value of @ref ADC_channels */ uint32_t InjectedRank; /*!< The rank in the injected group sequencer This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel. @@ -77,9 +77,9 @@ typedef struct uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels. This parameter can be set to ENABLE or DISABLE. */ uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels. - This parameter can be a value of @ref ADC_External_trigger_Source_Injected. */ + This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */ uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels. - This parameter can be a value of @ref ADC_External_trigger_Source_Injected */ + This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */ }ADC_InjectionConfTypeDef; /** @@ -88,9 +88,9 @@ typedef struct typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. - This parameter can be a value of @ref ADC_Common_mode */ + This parameter can be a value of @ref ADCEx_Common_mode */ uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. - This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */ + This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ }ADC_MultiModeTypeDef; diff --git a/stmhal/hal/inc/stm32f4xx_hal_can.h b/stmhal/hal/inc/stm32f4xx_hal_can.h index 8c32b3b00..250da8807 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_can.h +++ b/stmhal/hal/inc/stm32f4xx_hal_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_can.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -152,7 +152,7 @@ typedef struct uint32_t FilterActivation; /*!< Enable or disable the filter. This parameter can be set to ENABLE or DISABLE. */ - uint32_t BankNumber; /*!< Select the start slave bank filter + uint32_t BankNumber; /*!< Select the start slave bank filter. This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ }CAN_FilterConfTypeDef; @@ -579,6 +579,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset CAN handle state + * @param __HANDLE__: specifies the CAN Handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + /** * @brief Enable the specified CAN interrupts. * @param __HANDLE__: CAN handle @@ -667,11 +673,11 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__HANDLE__)->Instance->ESR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK)))) +((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK)))) /** @brief Check if the specified CAN interrupt source is enabled or disabled. * @param __HANDLE__: CAN Handle diff --git a/stmhal/hal/inc/stm32f4xx_hal_conf_template.h b/stmhal/hal/inc/stm32f4xx_hal_conf_template.h index 5d88879ca..6b2b4be5d 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_conf_template.h +++ b/stmhal/hal/inc/stm32f4xx_hal_conf_template.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_conf_template.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f4xx_hal_conf.h. @@ -115,6 +115,21 @@ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + /** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source @@ -131,9 +146,10 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 1 #define DATA_CACHE_ENABLE 1 diff --git a/stmhal/hal/inc/stm32f4xx_hal_cortex.h b/stmhal/hal/inc/stm32f4xx_hal_cortex.h index 7636eb5bf..baea63aa9 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_cortex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/stmhal/hal/inc/stm32f4xx_hal_crc.h b/stmhal/hal/inc/stm32f4xx_hal_crc.h index 2b8dc7512..2483e3556 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_crc.h +++ b/stmhal/hal/inc/stm32f4xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -85,6 +85,12 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset CRC handle state + * @param __HANDLE__: CRC handle + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + /** * @brief Resets CRC Data Register. * @param __HANDLE__: CRC handle @@ -92,6 +98,21 @@ typedef struct */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param __HANDLE__: CRC handle + * @param __VALUE: 8-bit value to be stored in the ID register + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)) + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * @param __HANDLE__: CRC handle + * @retval 8-bit value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) + /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions **********************************/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_cryp.h b/stmhal/hal/inc/stm32f4xx_hal_cryp.h index 61a1318be..a4dae01c1 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_cryp.h +++ b/stmhal/hal/inc/stm32f4xx_hal_cryp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention @@ -53,59 +53,57 @@ /** @addtogroup CRYP * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** - * @brief CRYP Configuration Structure definition + * @brief CRYP Configuration Structure definition */ typedef struct -{ +{ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of @ref CRYP_Data_Type */ - + uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length. This parameter can be a value of @ref CRYP_Key_Size */ - + uint8_t* pKey; /*!< The key used for encryption/decryption */ - + uint8_t* pInitVect; /*!< The initialization vector used also as initialization counter in CTR mode */ - + uint8_t IVSize; /*!< The size of initialization vector. This parameter (called nonce size in CCM) is used only in AES-128/192/256 encryption/decryption CCM mode */ - + uint8_t TagSize; /*!< The size of returned authentication TAG. This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */ - + uint8_t* Header; /*!< The header used in GCM and CCM modes */ - + uint16_t HeaderSize; /*!< The size of header buffer in bytes */ - + uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes. This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */ - }CRYP_InitTypeDef; /** - * @brief HAL CRYP State structures definition - */ + * @brief HAL CRYP State structures definition + */ typedef enum { HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */ HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */ HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */ HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */ - HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */ - + HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */ }HAL_CRYP_STATETypeDef; /** - * @brief HAL CRYP phase structures definition - */ + * @brief HAL CRYP phase structures definition + */ typedef enum { HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */ @@ -115,32 +113,31 @@ typedef enum }HAL_PhaseTypeDef; /** - * @brief CRYP handle Structure definition + * @brief CRYP handle Structure definition */ typedef struct -{ +{ CRYP_InitTypeDef Init; /*!< CRYP required parameters */ - + uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - + uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - + __IO uint16_t CrypInCount; /*!< Counter of inputed data */ - + __IO uint16_t CrypOutCount; /*!< Counter of outputed data */ - + HAL_StatusTypeDef Status; /*!< CRYP peripheral status */ - + HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */ - + DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ - + DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ - + HAL_LockTypeDef Lock; /*!< CRYP locking object */ - + __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ - }CRYP_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -151,7 +148,7 @@ typedef struct /** @defgroup CRYP_Key_Size * @{ - */ + */ #define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) #define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0 #define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1 @@ -210,7 +207,6 @@ typedef struct * @} */ - /** @defgroup CRYP_Flags * @{ */ @@ -229,7 +225,7 @@ typedef struct interrupt status */ /** * @} - */ + */ /** * @} @@ -237,6 +233,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset CRYP handle state + * @param __HANDLE__: specifies the CRYP handle. + * @retval None + */ +#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) + /** * @brief Enable/Disable the CRYP peripheral. * @param None @@ -253,13 +255,12 @@ typedef struct #define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH) /** - * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,... + * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC. * @param MODE: The algorithm mode. * @retval None */ #define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE) - /** @brief Check whether the specified CRYP flag is set or not. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: @@ -304,7 +305,7 @@ typedef struct #include "stm32f4xx_hal_cryp_ex.h" /* Exported functions --------------------------------------------------------*/ -/* Initialization/de-initialization functions **********************************/ +/* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); @@ -368,10 +369,10 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -/* Processing functions ********************************************************/ +/* Processing functions ******************************************************/ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); -/* Peripheral State functions **************************************************/ +/* Peripheral State functions ************************************************/ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); /* MSP functions *************************************************************/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_cryp_ex.h b/stmhal/hal/inc/stm32f4xx_hal_cryp_ex.h index 7d27cf6eb..773d30c1d 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_cryp_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_cryp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of CRYP HAL Extension module. ****************************************************************************** * @attention diff --git a/stmhal/hal/inc/stm32f4xx_hal_dac.h b/stmhal/hal/inc/stm32f4xx_hal_dac.h index a8ebee7ca..c1fd23209 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_dac.h +++ b/stmhal/hal/inc/stm32f4xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -59,8 +59,8 @@ /* Exported types ------------------------------------------------------------*/ /** - * @brief HAL State structures definition - */ + * @brief HAL State structures definition + */ typedef enum { HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ @@ -68,39 +68,37 @@ typedef enum HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ - }HAL_DAC_StateTypeDef; /** - * @brief DAC handle Structure definition - */ + * @brief DAC handle Structure definition + */ typedef struct { DAC_TypeDef *Instance; /*!< Register base address */ - + __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ HAL_LockTypeDef Lock; /*!< DAC locking object */ - + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ - - DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ - + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + __IO uint32_t ErrorCode; /*!< DAC Error code */ - + }DAC_HandleTypeDef; /** - * @brief DAC Configuration regular Channel structure definition - */ + * @brief DAC Configuration regular Channel structure definition + */ typedef struct { uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection */ - + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ - }DAC_ChannelConfTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -111,12 +109,12 @@ typedef struct #define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ +#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ /** * @} */ - -/** @defgroup DAC_trigger_selection + +/** @defgroup DAC_trigger_selection * @{ */ @@ -186,7 +184,7 @@ typedef struct /** @defgroup DAC_data * @{ */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) /** * @} */ @@ -195,7 +193,7 @@ typedef struct * @{ */ #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \ ((FLAG) == DAC_FLAG_DMAUDR2)) @@ -207,67 +205,104 @@ typedef struct * @{ */ #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \ ((IT) == DAC_IT_DMAUDR2)) - /** * @} */ /* Exported macro ------------------------------------------------------------*/ -/* Enable the DAC peripheral */ + +/** @brief Reset DAC handle state + * @param __HANDLE__: specifies the DAC handle. + * @retval None + */ +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) + +/** @brief Enable the DAC channel + * @param __HANDLE__: specifies the DAC handle. + * @param __DAC_Channel__: specifies the DAC channel + * @retval None + */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) -/* Disable the DAC peripheral */ +/** @brief Disable the DAC channel + * @param __HANDLE__: specifies the DAC handle + * @param __DAC_Channel__: specifies the DAC channel. + * @retval None + */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) - -/* Set DHR12R1 alignment */ + +/** @brief Set DHR12R1 alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ #define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) -/* Set DHR12R2 alignment */ +/** @brief Set DHR12R2 alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ #define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__)) -/* Set DHR12RD alignment */ +/** @brief Set DHR12RD alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ #define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__)) -/* Enable the DAC interrupt */ +/** @brief Enable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) -/* Disable the DAC interrupt */ +/** @brief Disable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) -/* Get the selected DAC's flag status */ +/** @brief Get the selected DAC's flag status. + * @param __HANDLE__: specifies the DAC handle. + * @retval None + */ #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/* Clear the DAC's flag */ -#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__)) +/** @brief Clear the DAC's flag. + * @param __HANDLE__: specifies the DAC handle. + * @retval None + */ +#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) /* Include DAC HAL Extension module */ -#include "stm32f4xx_hal_dac_ex.h" +#include "stm32f4xx_hal_dac_ex.h" -/* Exported functions --------------------------------------------------------*/ -/* Initialization/de-initialization functions ***********************************/ +/* Exported functions --------------------------------------------------------*/ +/* Initialization/de-initialization functions *********************************/ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); -/* I/O operation functions ******************************************************/ +/* I/O operation functions ****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); -/* Peripheral Control functions *************************************************/ +/* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); -/* Peripheral State functions ***************************************************/ +/* Peripheral State functions *************************************************/ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); diff --git a/stmhal/hal/inc/stm32f4xx_hal_dac_ex.h b/stmhal/hal/inc/stm32f4xx_hal_dac_ex.h index d658c86db..a8ed1c5b4 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_dac_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention diff --git a/stmhal/hal/inc/stm32f4xx_hal_dcmi.h b/stmhal/hal/inc/stm32f4xx_hal_dcmi.h index 2a6c73f8f..bb9c5123b 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_dcmi.h +++ b/stmhal/hal/inc/stm32f4xx_hal_dcmi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention @@ -59,17 +59,16 @@ /* Exported types ------------------------------------------------------------*/ /** - * @brief DCMI Error source - */ + * @brief DCMI Error source + */ typedef enum { DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */ DCMI_OVERRUN = 2, /*!< DCMI Overrun */ - -}DCMI_ErrorTypeDef; +}DCMI_ErrorTypeDef; /** - * @brief DCMI Embedded Synchronisation CODE Init structure definition + * @brief DCMI Embedded Synchronisation CODE Init structure definition */ typedef struct { @@ -77,11 +76,10 @@ typedef struct uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ - }DCMI_CodesInitTypeDef; /** - * @brief DCMI Init structure definition + * @brief DCMI Init structure definition */ typedef struct { @@ -102,17 +100,16 @@ typedef struct uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. This parameter can be a value of @ref DCMI_Extended_Data_Mode */ - + DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */ - + uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. - This parameter can be a value of @ref DCMI_MODE_JPEG */ - + This parameter can be a value of @ref DCMI_MODE_JPEG */ + }DCMI_InitTypeDef; - /** - * @brief HAL DCMI State structures definition + * @brief HAL DCMI State structures definition */ typedef enum { @@ -121,35 +118,34 @@ typedef enum HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */ HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */ HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */ - }HAL_DCMI_StateTypeDef; /** - * @brief DCMI handle Structure definition - */ + * @brief DCMI handle Structure definition + */ typedef struct -{ +{ DCMI_TypeDef *Instance; /*!< DCMI Register base address */ - - DCMI_InitTypeDef Init; /*!< DCMI parameters */ - - HAL_LockTypeDef Lock; /*!< DCMI locking object */ - - __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */ - - __IO uint32_t XferCount; /*!< DMA transfer counter */ - - __IO uint32_t XferSize; /*!< DMA transfer size */ - - uint32_t XferTransferNumber; /*!< DMA transfer number */ - uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */ - + DCMI_InitTypeDef Init; /*!< DCMI parameters */ + + HAL_LockTypeDef Lock; /*!< DCMI locking object */ + + __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */ + + __IO uint32_t XferCount; /*!< DMA transfer counter */ + + __IO uint32_t XferSize; /*!< DMA transfer size */ + + uint32_t XferTransferNumber; /*!< DMA transfer number */ + + uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */ - __IO uint32_t ErrorCode; /*!< DCMI Error code */ - -}DCMI_HandleTypeDef; + __IO uint32_t ErrorCode; /*!< DCMI Error code */ + +}DCMI_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -162,13 +158,13 @@ typedef struct */ #define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */ -#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */ +#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */ #define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ /** * @} - */ + */ -/** @defgroup DCMI_Capture_Mode +/** @defgroup DCMI_Capture_Mode * @{ */ #define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously @@ -180,8 +176,7 @@ typedef struct ((MODE) == DCMI_MODE_SNAPSHOT)) /** * @} - */ - + */ /** @defgroup DCMI_Synchronization_Mode * @{ @@ -190,17 +185,16 @@ typedef struct is synchronized with the HSYNC/VSYNC signals */ #define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow */ - + #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \ ((MODE) == DCMI_SYNCHRO_EMBEDDED)) /** * @} - */ + */ - -/** @defgroup DCMI_PIXCK_Polarity +/** @defgroup DCMI_PIXCK_Polarity * @{ - */ + */ #define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */ #define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ @@ -208,12 +202,11 @@ typedef struct ((POLARITY) == DCMI_PCKPOLARITY_RISING)) /** * @} - */ + */ - -/** @defgroup DCMI_VSYNC_Polarity +/** @defgroup DCMI_VSYNC_Polarity * @{ - */ + */ #define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */ #define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ @@ -221,10 +214,9 @@ typedef struct ((POLARITY) == DCMI_VSPOLARITY_HIGH)) /** * @} - */ + */ - -/** @defgroup DCMI_HSYNC_Polarity +/** @defgroup DCMI_HSYNC_Polarity * @{ */ #define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */ @@ -234,11 +226,11 @@ typedef struct ((POLARITY) == DCMI_HSPOLARITY_HIGH)) /** * @} - */ + */ /** @defgroup DCMI_MODE_JPEG * @{ - */ + */ #define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */ #define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */ @@ -246,11 +238,11 @@ typedef struct ((JPEG_MODE) == DCMI_JPEG_ENABLE)) /** * @} - */ + */ /** @defgroup DCMI_Capture_Rate * @{ - */ + */ #define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */ #define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ #define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ @@ -260,12 +252,11 @@ typedef struct ((RATE) == DCMI_CR_ALTERNATE_4_FRAME)) /** * @} - */ - + */ /** @defgroup DCMI_Extended_Data_Mode * @{ - */ + */ #define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ @@ -277,11 +268,11 @@ typedef struct ((DATA) == DCMI_EXTEND_DATA_14B)) /** * @} - */ + */ /** @defgroup DCMI_Window_Coordinate * @{ - */ + */ #define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */ #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE) @@ -297,11 +288,11 @@ typedef struct #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) /** * @} - */ + */ -/** @defgroup DCMI_interrupt_sources +/** @defgroup DCMI_interrupt_sources * @{ - */ + */ #define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) #define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE) #define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) @@ -317,13 +308,14 @@ typedef struct ((IT) == DCMI_IT_LINE)) /** * @} - */ + */ -/** @defgroup DCMI_Flags +/** @defgroup DCMI_Flags * @{ - */ + */ + /** - * @brief DCMI SR register + * @brief DCMI SR register */ #define DCMI_FLAG_HSYNC ((uint32_t)0x2001) #define DCMI_FLAG_VSYNC ((uint32_t)0x2002) @@ -368,6 +360,13 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DCMI handle state + * @param __HANDLE__: specifies the DCMI handle. + * @retval None + */ +#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) + /** * @brief Enable the DCMI. * @param __HANDLE__: DCMI handle @@ -411,7 +410,7 @@ typedef struct * @arg DCMI_FLAG_LINERI: Line flag mask * @retval None */ -#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__)) +#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** * @brief Enable the specified DCMI interrupts. @@ -455,15 +454,15 @@ typedef struct */ #define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions *******************************/ +/* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); -/* IO operation functions *******************************************************/ +/* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi); void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi); @@ -472,12 +471,12 @@ void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); -/* Peripheral Control functions *************************************************/ +/* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize); HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi); -/* Peripheral State functions ***************************************************/ +/* Peripheral State functions *************************************************/ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); diff --git a/stmhal/hal/inc/stm32f4xx_hal_def.h b/stmhal/hal/inc/stm32f4xx_hal_def.h index 606a5138a..35d7f2ebb 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_def.h +++ b/stmhal/hal/inc/stm32f4xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_def.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -79,14 +79,32 @@ typedef enum #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ do{ \ - (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ - (__DMA_HANDLE_).Parent = (__HANDLE__); \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while(0) +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + #if (USE_RTOS == 1) /* Reserved for future use */ + #error “USE_RTOS should be 0 in the current HAL release” #else #define __HAL_LOCK(__HANDLE__) \ do{ \ @@ -133,12 +151,44 @@ typedef enum #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC HAL_StatusTypeDef + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc HAL_StatusTypeDef + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) + +#endif + + #ifdef __cplusplus } #endif diff --git a/stmhal/hal/inc/stm32f4xx_hal_dma.h b/stmhal/hal/inc/stm32f4xx_hal_dma.h index fddd76a2e..54a5bd3f8 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_dma.h +++ b/stmhal/hal/inc/stm32f4xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -54,36 +54,36 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** - * @brief DMA Configuration Structure definition + * @brief DMA Configuration Structure definition */ typedef struct { uint32_t Channel; /*!< Specifies the channel used for the specified stream. This parameter can be a value of @ref DMA_Channel_selection */ - + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ - + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ + This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ - + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ + data transfer is configured on the selected Stream */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. This parameter can be a value of @ref DMA_Priority_level */ @@ -92,80 +92,75 @@ typedef struct This parameter can be a value of @ref DMA_FIFO_direct_mode @note The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected stream */ - + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. This parameter can be a value of @ref DMA_FIFO_threshold_level */ - + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptable - transaction. + transaction. This parameter can be a value of @ref DMA_Memory_burst @note The burst mode is possible only if the address Increment mode is enabled. */ - + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of @ref DMA_Peripheral_burst @note The burst mode is possible only if the address Increment mode is enabled. */ - }DMA_InitTypeDef; /** - * @brief HAL DMA State structures definition - */ + * @brief HAL DMA State structures definition + */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ - HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ + HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ - HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ + HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ - HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ + HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ - }HAL_DMA_StateTypeDef; /** - * @brief HAL DMA Error Code structure definition - */ + * @brief HAL DMA Error Code structure definition + */ typedef enum { HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ - }HAL_DMA_LevelCompleteTypeDef; - /** - * @brief DMA handle Structure definition - */ + * @brief DMA handle Structure definition + */ typedef struct __DMA_HandleTypeDef -{ +{ DMA_Stream_TypeDef *Instance; /*!< Register base address */ - + DMA_InitTypeDef Init; /*!< DMA communication parameters */ - + HAL_LockTypeDef Lock; /*!< DMA locking object */ - + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - + void *Parent; /*!< Parent object state */ - + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ - + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ - -}DMA_HandleTypeDef; +}DMA_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -178,7 +173,7 @@ typedef struct __DMA_HandleTypeDef */ #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ +#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ /** @@ -418,6 +413,13 @@ typedef struct __DMA_HandleTypeDef */ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DMA handle state + * @param __HANDLE__: specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + /** * @brief Return the current DMA Stream FIFO filled level. * @param __HANDLE__: DMA handle @@ -580,9 +582,9 @@ typedef struct __DMA_HandleTypeDef * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR |= (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR |= (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR |= (__FLAG__)) : (DMA1->LIFCR |= (__FLAG__))) +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) /** * @brief Enable the specified DMA Stream interrupts. diff --git a/stmhal/hal/inc/stm32f4xx_hal_dma2d.h b/stmhal/hal/inc/stm32f4xx_hal_dma2d.h index f23637b6e..f6e963b83 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_dma2d.h +++ b/stmhal/hal/inc/stm32f4xx_hal_dma2d.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma2d.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention @@ -58,121 +58,118 @@ /* Exported types ------------------------------------------------------------*/ #define MAX_DMA2D_LAYER 2 - + /** - * @brief DMA2D color Structure definition + * @brief DMA2D color Structure definition */ typedef struct { uint32_t Blue; /*!< Configures the blue value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - uint32_t Green; /*!< Configures the green value. + uint32_t Green; /*!< Configures the green value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - - uint32_t Red; /*!< Configures the red value. + + uint32_t Red; /*!< Configures the red value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ } DMA2D_ColorTypeDef; /** - * @brief DMA2D CLUT Structure definition + * @brief DMA2D CLUT Structure definition */ typedef struct { - uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address. */ + uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ - uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode. + uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode. This parameter can be one value of @ref DMA2D_CLUT_CM */ - + uint32_t Size; /*!< configures the DMA2D CLUT size. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ } DMA2D_CLUTCfgTypeDef; /** - * @brief DMA2D Init structure definition + * @brief DMA2D Init structure definition */ typedef struct { uint32_t Mode; /*!< configures the DMA2D transfer mode. This parameter can be one value of @ref DMA2D_Mode */ - + uint32_t ColorMode; /*!< configures the color format of the output image. This parameter can be one value of @ref DMA2D_Color_Mode */ uint32_t OutputOffset; /*!< Specifies the Offset value. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ - } DMA2D_InitTypeDef; /** - * @brief DMA2D Layer structure definition + * @brief DMA2D Layer structure definition */ typedef struct { - - uint32_t InputOffset; /*!< configures the DMA2D foreground offset. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode . This parameter can be one value of @ref DMA2D_Input_Color_Mode */ - + uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode. This parameter can be one value of @ref DMA2D_ALPHA_MODE */ - uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - + uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode. + This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF + in case of A8 or A4 color mode (ARGB). + Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ + } DMA2D_LayerCfgTypeDef; /** - * @brief HAL DMA2D State structures definition - */ + * @brief HAL DMA2D State structures definition + */ typedef enum { HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */ HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */ HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */ HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */ - }HAL_DMA2D_StateTypeDef; /** - * @brief DMA2D handle Structure definition - */ + * @brief DMA2D handle Structure definition + */ typedef struct __DMA2D_HandleTypeDef -{ +{ DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */ - + DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */ - + void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */ - + void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */ - + DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ - + HAL_LockTypeDef Lock; /*!< DMA2D Lock */ - + __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */ - + __IO uint32_t ErrorCode; /*!< DMA2D Error code */ - -} DMA2D_HandleTypeDef; +} DMA2D_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA2D_Exported_Constants * @{ - */ + */ /** @defgroup DMA2D_Layer * @{ */ -#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER) +#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER) /** * @} */ @@ -182,12 +179,12 @@ typedef struct __DMA2D_HandleTypeDef */ #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */ +#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */ #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ /** * @} */ - + /** @defgroup DMA2D_Mode * @{ */ @@ -200,7 +197,7 @@ typedef struct __DMA2D_HandleTypeDef ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) /** * @} - */ + */ /** @defgroup DMA2D_Color_Mode * @{ @@ -224,7 +221,6 @@ typedef struct __DMA2D_HandleTypeDef #define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */ -#define IS_DMA2D_ALPHA_VALUE(ALPHA_VALUE) ((ALPHA_VALUE) <= COLOR_VALUE) #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE) /** * @} @@ -242,7 +238,7 @@ typedef struct __DMA2D_HandleTypeDef * @} */ -/** @defgroup DMA2D_OFFSET +/** @defgroup DMA2D_Offset * @{ */ #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ @@ -303,7 +299,7 @@ typedef struct __DMA2D_HandleTypeDef * @} */ -/** @defgroup DMA2D_CLUT_SIZE +/** @defgroup DMA2D_Size_Clut * @{ */ #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */ @@ -321,8 +317,8 @@ typedef struct __DMA2D_HandleTypeDef #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK) /** * @} - */ - + */ + /** @defgroup DMA2D_Interrupts * @{ */ @@ -339,7 +335,7 @@ typedef struct __DMA2D_HandleTypeDef /** * @} */ - + /** @defgroup DMA2D_Flag * @{ */ @@ -361,6 +357,13 @@ typedef struct __DMA2D_HandleTypeDef * @} */ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DMA2D handle state + * @param __HANDLE__: specifies the DMA2D handle. + * @retval None + */ +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) + /** * @brief Enable the DMA2D. * @param __HANDLE__: DMA2D handle @@ -404,7 +407,7 @@ typedef struct __DMA2D_HandleTypeDef * @arg DMA2D_FLAG_TE: Transfer error flag * @retval None */ -#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR |= (__FLAG__)) +#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) /** * @brief Enables the specified DMA2D interrupts. diff --git a/stmhal/hal/inc/stm32f4xx_hal_dma_ex.h b/stmhal/hal/inc/stm32f4xx_hal_dma_ex.h index 433311e1c..488d05f80 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_dma_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention diff --git a/stmhal/hal/inc/stm32f4xx_hal_eth.h b/stmhal/hal/inc/stm32f4xx_hal_eth.h index 9906b4bc2..cc670e281 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_eth.h +++ b/stmhal/hal/inc/stm32f4xx_hal_eth.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_eth.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of ETH HAL module. ****************************************************************************** * @attention @@ -85,24 +85,24 @@ typedef struct and the mode (half/full-duplex). This parameter can be a value of @ref ETH_AutoNegotiation */ - uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps + uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. This parameter can be a value of @ref ETH_Speed */ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode This parameter can be a value of @ref ETH_Duplex_Mode */ - uint16_t PhyAddress; /*!< Ethernet PHY address + uint16_t PhyAddress; /*!< Ethernet PHY address. This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ - uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode + uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. This parameter can be a value of @ref ETH_Rx_Mode */ - uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software + uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. This parameter can be a value of @ref ETH_Checksum_Mode */ - uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface + uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. This parameter can be a value of @ref ETH_Media_Interface */ } ETH_InitTypeDef; @@ -124,78 +124,78 @@ typedef struct When disabled, the MAC can send up to 16384 bytes. This parameter can be a value of @ref ETH_Jabber */ - uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission + uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. This parameter can be a value of @ref ETH_Inter_Frame_Gap */ - uint32_t CarrierSense; /*!< Selects or not the Carrier Sense + uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. This parameter can be a value of @ref ETH_Carrier_Sense */ - uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn + uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode + in Half-Duplex mode. This parameter can be a value of @ref ETH_Receive_Own */ - uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode + uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. This parameter can be a value of @ref ETH_Loop_Back_Mode */ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. This parameter can be a value of @ref ETH_Checksum_Offload */ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a collision occurs (Half-Duplex mode) + when a collision occurs (Half-Duplex mode). This parameter can be a value of @ref ETH_Retry_Transmission */ - uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping + uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ - uint32_t BackOffLimit; /*!< Selects the BackOff limit value + uint32_t BackOffLimit; /*!< Selects the BackOff limit value. This parameter can be a value of @ref ETH_Back_Off_Limit */ - uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) + uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). This parameter can be a value of @ref ETH_Deferral_Check */ - uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering) + uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). This parameter can be a value of @ref ETH_Receive_All */ - uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode + uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. This parameter can be a value of @ref ETH_Source_Addr_Filter */ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) This parameter can be a value of @ref ETH_Pass_Control_Frames */ - uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames + uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ - uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames + uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. This parameter can be a value of @ref ETH_Destination_Addr_Filter */ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode This parameter can be a value of @ref ETH_Promiscuous_Mode */ - uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ - uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ - uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table + uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table + uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame + uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ - uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames + uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame + automatic retransmission of PAUSE Frame. This parameter can be a value of @ref ETH_Pause_Low_Threshold */ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address) + unicast address and unique multicast address). This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and @@ -207,7 +207,7 @@ typedef struct This parameter can be a value of @ref ETH_Transmit_Flow_Control */ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering + comparison and filtering. This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ @@ -221,54 +221,54 @@ typedef struct typedef struct { - uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames + uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode + uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. This parameter can be a value of @ref ETH_Receive_Store_Forward */ - uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames + uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. This parameter can be a value of @ref ETH_Flush_Received_Frame */ - uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode + uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. This parameter can be a value of @ref ETH_Transmit_Store_Forward */ - uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control + uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ - uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames + uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. This parameter can be a value of @ref ETH_Forward_Error_Frames */ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ - uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO + uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. This parameter can be a value of @ref ETH_Receive_Threshold_Control */ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second frame of Transmit data even before obtaining the status for the first frame. This parameter can be a value of @ref ETH_Second_Frame_Operate */ - uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats + uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. This parameter can be a value of @ref ETH_Address_Aligned_Beats */ - uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers + uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. This parameter can be a value of @ref ETH_Fixed_Burst */ - uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction + uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ - uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction + uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ - uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format + uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration + uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. This parameter can be a value of @ref ETH_DMA_Arbitration */ } ETH_DMAInitTypeDef; @@ -1290,9 +1290,9 @@ typedef struct ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) -/** - * @brief ETH_DMA_Enhanced_descriptor_format - */ +/** @defgroup ETH_DMA_Enhanced_descriptor_format + * @{ + */ #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080) #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000) @@ -1700,6 +1700,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset ETH handle state + * @param __HANDLE__: specifies the ETH handle. + * @retval None + */ +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) + /** * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. * @param __HANDLE__: ETH Handle @@ -1872,20 +1878,6 @@ typedef struct */ #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) -/** - * @brief Clears the specified ETHERNET MAC flag. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval None. - */ -#define __HAL_ETH_MAC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACSR &= ~(__FLAG__)) - /** * @brief Enables the specified ETHERNET DMA interrupts. * @param __HANDLE__ : ETH Handle @@ -1915,7 +1907,7 @@ typedef struct /** * @brief Checks whether the specified ETHERNET DMA flag is set or not. * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__: specifies the flag to check. @defgroup ETH_DMA_Flags * @retval The new state of ETH_DMA_FLAG (SET or RESET). */ #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) @@ -1923,10 +1915,10 @@ typedef struct /** * @brief Checks whether the specified ETHERNET DMA flag is set or not. * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__: specifies the flag to clear. @defgroup ETH_DMA_Flags * @retval The new state of ETH_DMA_FLAG (SET or RESET). */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR &= ~(__FLAG__)) +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) /** * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. @@ -2127,7 +2119,68 @@ typedef struct */ #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) +/** @defgroup ETH_EXTI_LINE_WAKEUP + * @{ + */ +#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ +/** + * @} + */ + +/** + * @brief Enables the ETH External interrupt line. + * @param None + * @retval None + */ +#define __HAL_ETH_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disables the ETH External interrupt line. + * @param None + * @retval None + */ +#define __HAL_ETH_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Get flag of the ETH External interrupt line. + * @param None + * @retval None + */ +#define __HAL_ETH_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Clear flag of the ETH External interrupt line. + * @param None + * @retval None + */ +#define __HAL_ETH_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Sets rising edge trigger to the ETH External interrupt line. + * @param None + * @retval None + */ +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP + +/** + * @brief Sets falling edge trigger to the ETH External interrupt line. + * @param None + * @retval None + */ +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP);\ + EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Sets rising/falling edge trigger to the ETH External interrupt line. + * @param None + * @retval None + */ +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ + EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP /* Exported functions --------------------------------------------------------*/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_flash.h b/stmhal/hal/inc/stm32f4xx_hal_flash.h index 7921d5199..a4373038b 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_flash.h +++ b/stmhal/hal/inc/stm32f4xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -321,6 +321,7 @@ typedef struct /* Include FLASH HAL Extension module */ #include "stm32f4xx_hal_flash_ex.h" +#include "stm32f4xx_hal_flash_ramfunc.h" /* Exported functions --------------------------------------------------------*/ /* Program operation functions ***********************************************/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_flash_ex.h b/stmhal/hal/inc/stm32f4xx_hal_flash_ex.h index 58cee49dc..ba92208c7 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_flash_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention @@ -61,19 +61,19 @@ */ typedef struct { - uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase. + uint32_t TypeErase; /*!< Mass erase or sector Erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ - uint32_t Banks; /*!< Banks: Select banks to erase when Mass erase is enabled + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. This parameter must be a value of @ref FLASHEx_Banks */ - uint32_t Sector; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of @ref FLASHEx_Sectors */ - uint32_t NbSectors; /*!< NbSectors: Number of sectors to be erased. + uint32_t NbSectors; /*!< Number of sectors to be erased. This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ - uint32_t VoltageRange;/*!< VoltageRange: The device voltage range which defines the erase parallelism + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism This parameter must be a value of @ref FLASHEx_Voltage_Range */ } FLASH_EraseInitTypeDef; @@ -83,65 +83,66 @@ typedef struct */ typedef struct { - uint32_t OptionType; /*!< OptionType: Option byte to be configured. + uint32_t OptionType; /*!< Option byte to be configured. This parameter can be a value of @ref FLASHEx_Option_Type */ - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + uint32_t WRPState; /*!< Write protection activation or deactivation. This parameter can be a value of @ref FLASHEx_WRP_State */ - uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series */ - uint32_t Banks; /*!< Banks: Select banks for WRP activation/deactivation of all sectors + uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. This parameter must be a value of @ref FLASHEx_Banks */ - uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + uint32_t RDPLevel; /*!< Set the read protection level. This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ - uint32_t BORLevel; /*!< BORLevel: Set the BOR Level. + uint32_t BORLevel; /*!< Set the BOR Level. This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ + uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ } FLASH_OBProgramInitTypeDef; /** * @brief FLASH Advanced Option Bytes Program structure definition */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) typedef struct { - uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . + uint32_t OptionType; /*!< Option byte to be configured for extension. This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */ - uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. + uint32_t PCROPState; /*!< PCROP activation or deactivation. This parameter can be a value of @ref FLASHEx_PCROP_State */ -#if defined (STM32F401xC) || defined (STM32F401xE) - uint16_t Sectors; /*!< Sectors: specifies the sector(s) set for PCROP +#if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE) + uint16_t Sectors; /*!< specifies the sector(s) set for PCROP. This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ -#endif /* STM32F401xC || STM32F401xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - uint32_t Banks; /*!< Banks: Select banks for PCROP activation/deactivation of all sectors + uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors. This parameter must be a value of @ref FLASHEx_Banks */ - uint16_t SectorsBank1; /*!< SectorsBank1: specifies the sector(s) set for PCROP for Bank1 + uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1. This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ - uint16_t SectorsBank2; /*!< SectorsBank2: specifies the sector(s) set for PCROP for Bank2 + uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2. This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ - uint8_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config + uint8_t BootConfig; /*!< Specifies Option bytes for boot config. This parameter can be a value of @ref FLASHEx_Dual_Boot */ #endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ } FLASH_AdvOBProgramInitTypeDef; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants * @{ */ @@ -260,7 +261,8 @@ typedef struct * @} */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** @defgroup FLASHEx_PCROP_State FLASH PCROP State * @{ */ @@ -273,7 +275,7 @@ typedef struct /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ /** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type * @{ @@ -287,12 +289,12 @@ typedef struct #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define OBEX_PCROP ((uint32_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +/*-----------------------------------------------------------------------------------------------------*/ +/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ @@ -469,11 +479,10 @@ typedef struct ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11)) - -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +/*-----------------------------------------------------------------------------------------------------*/ +/*--------------------------------------------- STM32F401xC -------------------------------------------*/ #if defined(STM32F401xC) #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ @@ -487,12 +496,11 @@ typedef struct #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5)) - -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) #endif /* STM32F401xC */ +/*-----------------------------------------------------------------------------------------------------*/ -#if defined(STM32F401xE) +/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/ +#if defined(STM32F401xE) || defined(STM32F411xE) #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ @@ -508,11 +516,9 @@ typedef struct ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) - -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) -#endif /* STM32F401xE */ - +#endif /* STM32F401xE || STM32F411xE */ +/*-----------------------------------------------------------------------------------------------------*/ +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < FLASH_END)) #define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) /** @@ -522,6 +528,7 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @{ */ +/*----------------------------------------- STM32F42xxx/STM32F43xxx-------------------------------------*/ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ @@ -551,7 +558,9 @@ typedef struct #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000)) #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +/*-----------------------------------------------------------------------------------------------------*/ +/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ @@ -569,7 +578,9 @@ typedef struct #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +/*-----------------------------------------------------------------------------------------------------*/ +/*--------------------------------------------- STM32F401xC -------------------------------------------*/ #if defined(STM32F401xC) #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ @@ -581,8 +592,10 @@ typedef struct #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) #endif /* STM32F401xC */ +/*-----------------------------------------------------------------------------------------------------*/ -#if defined(STM32F401xE) +/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/ +#if defined(STM32F401xE) || defined(STM32F411xE) #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ @@ -594,7 +607,8 @@ typedef struct #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -#endif /* STM32F401xE */ +#endif /* STM32F401xE || STM32F411xE */ +/*-----------------------------------------------------------------------------------------------------*/ /** * @} */ @@ -602,6 +616,7 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection * @{ */ +/*----------------------------------------- STM32F42xxx/STM32F43xxx-------------------------------------*/ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ @@ -631,7 +646,9 @@ typedef struct #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +/*-----------------------------------------------------------------------------------------------------*/ +/*--------------------------------------------- STM32F401xC -------------------------------------------*/ #if defined(STM32F401xC) #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ @@ -643,8 +660,10 @@ typedef struct #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) #endif /* STM32F401xC */ +/*-----------------------------------------------------------------------------------------------------*/ -#if defined(STM32F401xE) +/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/ +#if defined(STM32F401xE) || defined(STM32F411xE) #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ #define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ @@ -656,7 +675,8 @@ typedef struct #define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -#endif /* STM32F401xE */ +#endif /* STM32F401xE || STM32F411xE */ +/*-----------------------------------------------------------------------------------------------------*/ /** * @} @@ -677,11 +697,12 @@ typedef struct /** @defgroup FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ #define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ /** * @} */ @@ -706,12 +727,14 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) uint16_t HAL_FLASHEx_OB_GetBank2WRP(void); diff --git a/stmhal/hal/inc/stm32f4xx_hal_flash_ramfunc.h b/stmhal/hal/inc/stm32f4xx_hal_flash_ramfunc.h new file mode 100644 index 000000000..b50dbe49f --- /dev/null +++ b/stmhal/hal/inc/stm32f4xx_hal_flash_ramfunc.h @@ -0,0 +1,84 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ramfunc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-June-2014 + * @brief Header file of FLASH RAMFUNC driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FLASH_RAMFUNC_H +#define __STM32F4xx_FLASH_RAMFUNC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F411xE) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void); +__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void); +__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void); +__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void); + +#endif /* STM32F411xE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_gpio.h b/stmhal/hal/inc/stm32f4xx_hal_gpio.h index f14654821..741f1da93 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_gpio.h +++ b/stmhal/hal/inc/stm32f4xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -73,7 +73,7 @@ typedef struct uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed_define */ - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. This parameter can be a value of @ref GPIO_Alternat_function_selection */ }GPIO_InitTypeDef; @@ -114,23 +114,9 @@ typedef enum #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint32_t)0x00) == 0x00) && ((PIN) != (uint32_t)0x00)) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_0) || \ - ((PIN) == GPIO_PIN_1) || \ - ((PIN) == GPIO_PIN_2) || \ - ((PIN) == GPIO_PIN_3) || \ - ((PIN) == GPIO_PIN_4) || \ - ((PIN) == GPIO_PIN_5) || \ - ((PIN) == GPIO_PIN_6) || \ - ((PIN) == GPIO_PIN_7) || \ - ((PIN) == GPIO_PIN_8) || \ - ((PIN) == GPIO_PIN_9) || \ - ((PIN) == GPIO_PIN_10) || \ - ((PIN) == GPIO_PIN_11) || \ - ((PIN) == GPIO_PIN_12) || \ - ((PIN) == GPIO_PIN_13) || \ - ((PIN) == GPIO_PIN_14) || \ - ((PIN) == GPIO_PIN_15)) +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) + /** * @} */ @@ -177,7 +163,6 @@ typedef enum /** * @} */ - /** @defgroup GPIO_speed_define * @brief GPIO Output Maximum frequency * @{ @@ -216,7 +201,7 @@ typedef enum /** * @brief Checks whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be(0..15) + * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) @@ -224,7 +209,7 @@ typedef enum /** * @brief Clears the EXTI's line pending flags. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..15) + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) @@ -232,7 +217,7 @@ typedef enum /** * @brief Checks whether the specified EXTI line is asserted or not. * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be(0..15) + * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) @@ -240,11 +225,19 @@ typedef enum /** * @brief Clears the EXTI's line pending bits. * @param __EXTI_LINE__: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..15) + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + /* Include GPIO HAL Extension module */ #include "stm32f4xx_hal_gpio_ex.h" @@ -255,10 +248,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /* IO operation functions *******************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} diff --git a/stmhal/hal/inc/stm32f4xx_hal_gpio_ex.h b/stmhal/hal/inc/stm32f4xx_hal_gpio_ex.h index 2e0c86eaf..0bed44311 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_gpio_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -687,6 +687,116 @@ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT)) #endif /* STM32F401xC || STM32F401xE */ +/*------------------------------------------------------------------------------------------*/ + +/*---------------------------------------- STM32F411xx--------------------------------------*/ +#if defined(STM32F411xE) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ + + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \ + ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI4) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF6_SPI5) || ((AF) == GPIO_AF7_SPI3) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F411xE */ /** * @} */ diff --git a/stmhal/hal/inc/stm32f4xx_hal_hash.h b/stmhal/hal/inc/stm32f4xx_hal_hash.h index 339b2d297..32e3be6f5 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_hash.h +++ b/stmhal/hal/inc/stm32f4xx_hal_hash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_HASH_H @@ -56,72 +56,68 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** - * @brief HASH Configuration Structure definition + * @brief HASH Configuration Structure definition */ typedef struct -{ +{ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of @ref HASH_Data_Type */ - + uint32_t KeySize; /*!< The key size is used only in HMAC operation */ - + uint8_t* pKey; /*!< The key is used only in HMAC operation */ - }HASH_InitTypeDef; /** - * @brief HAL State structures definition + * @brief HAL State structures definition */ typedef enum { HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */ - HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */ - HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */ + HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */ + HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */ HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */ HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */ - }HAL_HASH_STATETypeDef; /** - * @brief HAL phase structures definition - */ + * @brief HAL phase structures definition + */ typedef enum { HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */ HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */ - }HAL_HASHPhaseTypeDef; /** - * @brief HASH Handle Structure definition - */ + * @brief HASH Handle Structure definition + */ typedef struct -{ +{ HASH_InitTypeDef Init; /*!< HASH required parameters */ - + uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ - + uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */ - + __IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */ - + __IO uint32_t HashInCount; /*!< Counter of inputed data */ - + __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */ - + HAL_StatusTypeDef Status; /*!< HASH peripheral status */ - + HAL_HASHPhaseTypeDef Phase; /*!< HASH peripheral phase */ - + DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */ - + HAL_LockTypeDef Lock; /*!< HASH locking object */ - + __IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */ - } HASH_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -130,9 +126,9 @@ typedef struct * @{ */ -/** @defgroup HASH_Algo_Selection +/** @defgroup HASH_Algo_Selection * @{ - */ + */ #define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ #define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ #define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ @@ -146,7 +142,7 @@ typedef struct * @} */ -/** @defgroup HASH_Algorithm_Mode +/** @defgroup HASH_Algorithm_Mode * @{ */ #define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ @@ -158,9 +154,9 @@ typedef struct * @} */ -/** @defgroup HASH_Data_Type +/** @defgroup HASH_Data_Type * @{ - */ + */ #define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ #define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ #define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ @@ -174,7 +170,7 @@ typedef struct * @} */ -/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode +/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode * @{ */ #define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ @@ -186,9 +182,9 @@ typedef struct * @} */ -/** @defgroup HASH_flags_definition +/** @defgroup HASH_flags_definition * @{ - */ + */ #define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */ #define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ #define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ @@ -196,9 +192,9 @@ typedef struct #define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */ /** * @} - */ + */ -/** @defgroup HASH_interrupts_definition +/** @defgroup HASH_interrupts_definition * @{ */ #define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */ @@ -213,6 +209,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset HASH handle state + * @param __HANDLE__: specifies the HASH handle. + * @retval None + */ +#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) + /** @brief Check whether the specified HASH flag is set or not. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: diff --git a/stmhal/hal/inc/stm32f4xx_hal_hash_ex.h b/stmhal/hal/inc/stm32f4xx_hal_hash_ex.h index e03a57538..d5d92abe9 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_hash_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_hash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention diff --git a/stmhal/hal/inc/stm32f4xx_hal_hcd.h b/stmhal/hal/inc/stm32f4xx_hal_hcd.h index 27929eed0..71faa3601 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_hcd.h +++ b/stmhal/hal/inc/stm32f4xx_hal_hcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hcd.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention @@ -61,10 +61,11 @@ */ typedef enum { - HCD_READY = 0x00, - HCD_ERROR = 0x01, - HCD_BUSY = 0x02, - HCD_TIMEOUT = 0x03 + HAL_HCD_STATE_RESET = 0x00, + HAL_HCD_STATE_READY = 0x01, + HAL_HCD_STATE_ERROR = 0x02, + HAL_HCD_STATE_BUSY = 0x03, + HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; typedef USB_OTG_GlobalTypeDef HCD_TypeDef; @@ -95,16 +96,11 @@ typedef struct /** @defgroup HCD_Instance_definition * @{ */ - -#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__)) -#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) - #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ ((INSTANCE) == USB_OTG_HS)) -#elif defined(STM32F401xC) || defined(STM32F401xE) +#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS)) #endif @@ -144,9 +140,10 @@ typedef struct #define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__)) -#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) + +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) diff --git a/stmhal/hal/inc/stm32f4xx_hal_i2c.h b/stmhal/hal/inc/stm32f4xx_hal_i2c.h index e0d1decf1..733ec2785 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_i2c.h +++ b/stmhal/hal/inc/stm32f4xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -80,7 +80,7 @@ typedef struct This parameter can be a 7-bit address. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_general_call_addressing_mode. */ + This parameter can be a value of @ref I2C_general_call_addressing_mode */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref I2C_nostretch_mode */ @@ -268,6 +268,13 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset I2C handle state + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) + /** @brief Enable or disable the specified I2C interrupts. * @param __HANDLE__: specifies the I2C Handle. * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. @@ -341,7 +348,7 @@ typedef struct * @arg I2C_FLAG_BERR: Bus error flag * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 &= ~((__FLAG__) & I2C_FLAG_MASK)) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) /** @brief Clears the I2C ADDR pending flag. * @param __HANDLE__: specifies the I2C Handle. diff --git a/stmhal/hal/inc/stm32f4xx_hal_i2c_ex.h b/stmhal/hal/inc/stm32f4xx_hal_i2c_ex.h index 6312f558e..135bebd59 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_i2c_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_i2c_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention @@ -43,7 +43,8 @@ extern "C" { #endif -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" diff --git a/stmhal/hal/inc/stm32f4xx_hal_i2s.h b/stmhal/hal/inc/stm32f4xx_hal_i2s.h index bff907800..c4537e758 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_i2s.h +++ b/stmhal/hal/inc/stm32f4xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -187,17 +187,25 @@ typedef struct /** @defgroup I2S_Standard * @{ */ -#define I2S_STANDARD_PHILLIPS ((uint32_t)0x00000000) +#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) #define I2S_STANDARD_MSB ((uint32_t)0x00000010) #define I2S_STANDARD_LSB ((uint32_t)0x00000020) #define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030) #define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILLIPS) || \ +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ ((STANDARD) == I2S_STANDARD_MSB) || \ ((STANDARD) == I2S_STANDARD_LSB) || \ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ ((STANDARD) == I2S_STANDARD_PCM_LONG)) +/** @defgroup I2S_Legacy + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +/** + * @} + */ + /** * @} */ @@ -307,6 +315,13 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset I2S handle state + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) + /** @brief Enable or disable the specified SPI peripheral (in I2S mode). * @param __HANDLE__: specifies the I2S Handle. * @retval None diff --git a/stmhal/hal/inc/stm32f4xx_hal_i2s_ex.h b/stmhal/hal/inc/stm32f4xx_hal_i2s_ex.h index 34b95f9e0..ddccf55da 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_i2s_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_i2s_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention diff --git a/stmhal/hal/inc/stm32f4xx_hal_irda.h b/stmhal/hal/inc/stm32f4xx_hal_irda.h index fe308e178..5048e2189 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_irda.h +++ b/stmhal/hal/inc/stm32f4xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_irda.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention @@ -233,22 +233,37 @@ typedef struct #define IRDA_IT_TC ((uint32_t)0x10000040) #define IRDA_IT_RXNE ((uint32_t)0x10000020) #define IRDA_IT_IDLE ((uint32_t)0x10000010) - + #define IRDA_IT_LBD ((uint32_t)0x20000040) -#define IRDA_IT_CTS ((uint32_t)0x30000400) +#define IRDA_IT_CTS ((uint32_t)0x30000400) #define IRDA_IT_ERR ((uint32_t)0x30000001) /** * @} */ - + /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset IRDA handle state + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) + +/** @brief Flushs the IRDA DR register + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + */ +#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + /** @brief Checks whether the specified IRDA flag is set or not. * @param __HANDLE__: specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or @@ -287,8 +302,47 @@ typedef struct * * @retval None */ -#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__)) +#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) +/** @brief Clear the IRDA PE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->DR;}while(0) +/** @brief Clear the IRDA FE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the IRDA NE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the IRDA ORE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the IRDA IDLE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) /** @brief Enables or disables the specified IRDA interrupt. * @param __HANDLE__: specifies the USART Handle. @@ -358,9 +412,14 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); /* Peripheral State functions **************************************************/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_iwdg.h b/stmhal/hal/inc/stm32f4xx_hal_iwdg.h index 3dab46811..982c0d7dc 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_iwdg.h +++ b/stmhal/hal/inc/stm32f4xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention @@ -112,6 +112,10 @@ typedef struct #define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR write Access enable */ #define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR write Access disable */ +#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \ + ((__KR__) == KR_KEY_ENABLE))|| \ + ((__KR__) == KR_KEY_EWA)) || \ + ((__KR__) == KR_KEY_DWA)) /** * @} */ @@ -133,12 +137,13 @@ typedef struct * @{ */ #define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 ((uint8_t)0x01) /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 ((uint8_t)0x02) /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 ((uint8_t)0x03) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 ((uint8_t)0x04) /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 ((uint8_t)0x05) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 ((uint8_t)0x06) /*!< IWDG prescaler set to 256 */ +#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ + #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4) || \ ((PRESCALER) == IWDG_PRESCALER_8) || \ @@ -167,12 +172,18 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset IWDG handle state + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) + /** * @brief Enables the IWDG peripheral. * @param __HANDLE__: IWDG handle * @retval None */ -#define __HAL_IWDG_START(__HANDLE__) ((__HANDLE__)->Instance->KR |= KR_KEY_ENABLE) +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE) /** * @brief Reloads IWDG counter with value defined in the reload register @@ -180,21 +191,21 @@ typedef struct * @param __HANDLE__: IWDG handle * @retval None */ -#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_RELOAD) +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD) /** * @brief Enables write access to IWDG_PR and IWDG_RLR registers. * @param __HANDLE__: IWDG handle * @retval None */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_EWA) +#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA) /** * @brief Disables write access to IWDG_PR and IWDG_RLR registers. * @param __HANDLE__: IWDG handle * @retval None */ -#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_DWA) +#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA) /** * @brief Gets the selected IWDG's flag status. @@ -207,18 +218,6 @@ typedef struct */ #define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) -/** - * @brief Clears the IWDG's pending flags. - * @param __HANDLE__: IWDG handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag - * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag - * @retval None - */ -#define __HAL_IWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__)) - - /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions ********************************/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_ltdc.h b/stmhal/hal/inc/stm32f4xx_hal_ltdc.h index aab9258b3..719ecfe2c 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_ltdc.h +++ b/stmhal/hal/inc/stm32f4xx_hal_ltdc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention @@ -59,9 +59,9 @@ /* Exported types ------------------------------------------------------------*/ #define MAX_LAYER 2 - + /** - * @brief LTDC color structure definition + * @brief LTDC color structure definition */ typedef struct { @@ -70,15 +70,15 @@ typedef struct uint8_t Green; /*!< Configures the green value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - + uint8_t Red; /*!< Configures the red value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - - uint8_t Reserved; /*!< Reserved 0xFF */ -} LTDC_ColorTypeDef; - + + uint8_t Reserved; /*!< Reserved 0xFF */ +} LTDC_ColorTypeDef; + /** - * @brief LTDC Init structure definition + * @brief LTDC Init structure definition */ typedef struct { @@ -95,7 +95,7 @@ typedef struct This parameter can be one of value of @ref LTDC_PC_POLARITY */ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization heigh. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ @@ -104,42 +104,41 @@ typedef struct This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh. - This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ - - uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. This parameter - This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ - uint32_t AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + + uint32_t AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ - uint32_t TotalWidth; /*!< configures the total width. This parameter + uint32_t TotalWidth; /*!< configures the total width. This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ - uint32_t TotalHeigh; /*!< configures the total heigh. This parameter + uint32_t TotalHeigh; /*!< configures the total heigh. This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ - - LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ + LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ } LTDC_InitTypeDef; /** - * @brief LTDC Layer structure definition + * @brief LTDC Layer structure definition */ typedef struct { uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - + uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - + uint32_t WindowY0; /*!< Configures the Window vertical Start Position. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - + uint32_t PixelFormat; /*!< Specifies the pixel format. This parameter can be one of value of @ref LTDC_Pixelformat */ @@ -154,60 +153,58 @@ typedef struct uint32_t BlendingFactor2; /*!< Select the blending factor 2. This parameter can be one of value of @ref LTDC_BlendingFactor2 */ - + uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ uint32_t ImageWidth; /*!< Configures the color frame buffer line length. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ - + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ - + LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ - } LTDC_LayerCfgTypeDef; /** - * @brief HAL LTDC State structures definition - */ + * @brief HAL LTDC State structures definition + */ typedef enum { - HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */ HAL_LTDC_STATE_READY = 0x01, /*!< LTDC initialized and ready for use */ - HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */ - HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */ - HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */ - + HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */ }HAL_LTDC_StateTypeDef; /** - * @brief LTDC handle Structure definition - */ + * @brief LTDC handle Structure definition + */ typedef struct -{ +{ LTDC_TypeDef *Instance; /*!< LTDC Register base address */ - + LTDC_InitTypeDef Init; /*!< LTDC parameters */ - + LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ - - HAL_LockTypeDef Lock; /*!< LTDC Lock */ - + + HAL_LockTypeDef Lock; /*!< LTDC Lock */ + __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ - __IO uint32_t ErrorCode; /*!< LTDC Error code */ - -} LTDC_HandleTypeDef; + __IO uint32_t ErrorCode; /*!< LTDC Error code */ + +} LTDC_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup LTDC_Exported_Constants * @{ */ - + /** @defgroup LTDC_Layer * @{ */ -#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER) +#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER) /** * @} */ @@ -331,7 +328,7 @@ typedef struct */ #define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001) /*!< RGB888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005) /*!< L8 LTDC pixel format */ @@ -388,7 +385,7 @@ typedef struct /** @defgroup LTDC_Interrupts * @{ - */ + */ #define LTDC_IT_LI LTDC_IER_LIE #define LTDC_IT_FU LTDC_IER_FUIE #define LTDC_IT_TE LTDC_IER_TERRIE @@ -411,13 +408,20 @@ typedef struct ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR)) /** * @} - */ + */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset LTDC handle state + * @param __HANDLE__: specifies the LTDC handle. + * @retval None + */ +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) + /** * @brief Enable the LTDC. * @param __HANDLE__: LTDC handle @@ -443,7 +447,6 @@ typedef struct #define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) - /** * @brief Disable the LTDC Layer. * @param __HANDLE__: LTDC handle @@ -485,7 +488,7 @@ typedef struct * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag * @retval None */ -#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__)) +#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** * @brief Enables the specified LTDC interrupts. @@ -525,10 +528,10 @@ typedef struct * @retval The state of INTERRUPT (SET or RESET). */ #define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__)) - -/* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions *******************************/ +/* Exported functions --------------------------------------------------------*/ + +/* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc); @@ -536,10 +539,10 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc); -/* IO operation functions *******************************************************/ +/* IO operation functions *****************************************************/ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); -/* Peripheral Control functions *************************************************/ +/* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); @@ -556,7 +559,7 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); -/* Peripheral State functions ***************************************************/ +/* Peripheral State functions *************************************************/ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); diff --git a/stmhal/hal/inc/stm32f4xx_hal_nand.h b/stmhal/hal/inc/stm32f4xx_hal_nand.h index b74c1b0db..e9f780a09 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_nand.h +++ b/stmhal/hal/inc/stm32f4xx_hal_nand.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_nand.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_NAND_H @@ -62,70 +62,67 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -/* Exported typedef ----------------------------------------------------------*/ +/* Exported typedef ----------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /** - * @brief HAL NAND State structures definition - */ + * @brief HAL NAND State structures definition + */ typedef enum { HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ - }HAL_NAND_StateTypeDef; /** - * @brief NAND Memory electronic signature Structure definition + * @brief NAND Memory electronic signature Structure definition */ typedef struct { - /*State = HAL_NAND_STATE_RESET) + /** * @brief NAND memory address computation. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__: NAND memory address. * @param __HANDLE__ : NAND handle. * @retval NAND Raw address value */ -#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.BlockSize)))* ((__HANDLE__)->Info.ZoneSize))) - +#define __ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize))) + /** * @brief NAND memory address cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__: NAND memory address. * @retval NAND address cycling value. */ -#define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__)& 0xFF) /* 1st addressing cycle */ -#define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8) /* 2nd addressing cycle */ -#define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16) /* 3rd addressing cycle */ -#define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */ +#define __ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ +#define __ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ +#define __ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ +#define __ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ /* Exported functions --------------------------------------------------------*/ -/* Initialization/de-initialization functions **********************************/ +/* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); @@ -198,7 +212,7 @@ void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); -/* IO operation functions *****************************************************/ +/* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); @@ -209,12 +223,12 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressT uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress); -/* NAND Control functions ******************************************************/ +/* NAND Control functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); -/* NAND State functions *********************************************************/ +/* NAND State functions *******************************************************/ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); diff --git a/stmhal/hal/inc/stm32f4xx_hal_nor.h b/stmhal/hal/inc/stm32f4xx_hal_nor.h index 2719618cd..86ccc3597 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_nor.h +++ b/stmhal/hal/inc/stm32f4xx_hal_nor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_nor.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention @@ -62,7 +62,7 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -/* Exported typedef ----------------------------------------------------------*/ +/* Exported typedef ----------------------------------------------------------*/ /** * @brief HAL SRAM State structures definition */ @@ -71,10 +71,9 @@ typedef enum HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ - HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ - HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ - -}HAL_NOR_StateTypeDef; + HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ + HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ +}HAL_NOR_StateTypeDef; /** * @brief FMC NOR Status typedef @@ -85,8 +84,7 @@ typedef enum NOR_ONGOING, NOR_ERROR, NOR_TIMEOUT - -}NOR_StatusTypedef; +}NOR_StatusTypedef; /** * @brief FMC NOR ID typedef @@ -94,19 +92,17 @@ typedef enum typedef struct { uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ - - uint16_t Device_Code1; - - uint16_t Device_Code2; - - uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. + + uint16_t Device_Code1; + + uint16_t Device_Code2; + + uint16_t Device_Code3; /*!< Defines the devices' codes used to identify the memory. These codes can be accessed by performing read operations with specific control signals and addresses set.They can also be accessed by issuing - an Auto Select command */ - + an Auto Select command */ }NOR_IDTypeDef; - /** * @brief FMC NOR CFI typedef */ @@ -115,32 +111,31 @@ typedef struct /*!< Defines the information stored in the memory's Common flash interface which contains a description of various electrical and timing parameters, density information and functions supported by the memory */ - - uint16_t CFI_1; - - uint16_t CFI_2; - - uint16_t CFI_3; - - uint16_t CFI_4; - + + uint16_t CFI_1; + + uint16_t CFI_2; + + uint16_t CFI_3; + + uint16_t CFI_4; }NOR_CFITypeDef; /** - * @brief NOR handle Structure definition + * @brief NOR handle Structure definition */ typedef struct { - FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - + FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ + FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ - + FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ - HAL_LockTypeDef Lock; /*!< NOR locking object */ - + HAL_LockTypeDef Lock; /*!< NOR locking object */ + __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ - + }NOR_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -162,27 +157,35 @@ typedef struct /* NOR operation wait timeout */ #define NOR_TMEOUT ((uint16_t)0xFFFF) -/* #define NOR_MEMORY_16B */ -#define NOR_MEMORY_8B +/* NOR memory data width */ +#define NOR_MEMORY_8B ((uint8_t)0x0) +#define NOR_MEMORY_16B ((uint8_t)0x1) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS ((uint32_t)0x60000000) +#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000) +#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000) +#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000) +#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000) /** * @} */ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset NOR handle state + * @param __HANDLE__: specifies the NOR handle. + * @retval None + */ +#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) + /** * @brief NOR memory address shifting. * @param __ADDRESS__: NOR memory address * @retval NOR shifted address value */ -#ifdef NOR_MEMORY_8B - #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (2 * (__ADDRESS__))) -#else /* NOR_MEMORY_16B */ - #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (__ADDRESS__)) -#endif /* NOR_MEMORY_8B */ +#define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) (((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):\ + ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))) /** * @brief NOR memory write data to specified address. @@ -194,14 +197,14 @@ typedef struct /* Exported functions --------------------------------------------------------*/ -/* Initialization/de-initialization functions **********************************/ +/* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); -/* I/O operation functions *****************************************************/ +/* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); @@ -214,11 +217,11 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); -/* NOR Control functions *******************************************************/ +/* NOR Control functions *****************************************************/ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); -/* NOR State functions **********************************************************/ +/* NOR State functions ********************************************************/ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); diff --git a/stmhal/hal/inc/stm32f4xx_hal_pccard.h b/stmhal/hal/inc/stm32f4xx_hal_pccard.h index 38ded356c..1301c068f 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_pccard.h +++ b/stmhal/hal/inc/stm32f4xx_hal_pccard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pccard.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of PCCARD HAL module. ****************************************************************************** * @attention @@ -138,6 +138,13 @@ typedef struct /** * @} */ +/* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset PCCARD handle state + * @param __HANDLE__: specifies the PCCARD handle. + * @retval None + */ +#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET) /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions **********************************/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_pcd.h b/stmhal/hal/inc/stm32f4xx_hal_pcd.h index 5b597d89e..5e06e20e3 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_pcd.h +++ b/stmhal/hal/inc/stm32f4xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -61,10 +61,11 @@ */ typedef enum { - PCD_READY = 0x00, - PCD_ERROR = 0x01, - PCD_BUSY = 0x02, - PCD_TIMEOUT = 0x03 + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 } PCD_StateTypeDef; @@ -118,7 +119,7 @@ typedef struct #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ ((INSTANCE) == USB_OTG_HS)) -#elif defined(STM32F401xC) || defined(STM32F401xE) +#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS)) #endif @@ -139,9 +140,9 @@ typedef struct #define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__)) -#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ @@ -184,7 +185,9 @@ typedef struct EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP;\ EXTI->FTSR |= USB_HS_EXTI_LINE_WAKEUP - +#define __HAL_USB_HS_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_FS_EXTI_LINE_WAKEUP) + + #define __HAL_USB_FS_EXTI_ENABLE_IT() EXTI->IMR |= USB_FS_EXTI_LINE_WAKEUP #define __HAL_USB_FS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_FS_EXTI_LINE_WAKEUP) #define __HAL_USB_FS_EXTI_GET_FLAG() EXTI->PR & (USB_FS_EXTI_LINE_WAKEUP) @@ -201,12 +204,17 @@ typedef struct #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\ EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\ EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= USB_FS_EXTI_LINE_WAKEUP + EXTI->FTSR |= USB_FS_EXTI_LINE_WAKEUP + +#define __HAL_USB_FS_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_FS_EXTI_LINE_WAKEUP) /** * @} */ +/* Include PCD HAL Extension module */ +#include "stm32f4xx_hal_pcd_ex.h" + /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions **********************************/ @@ -233,8 +241,6 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); - - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); @@ -247,10 +253,13 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); -HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); + +/* Create an alias to keep compatibility with the old name */ +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo + /* Peripheral State functions **************************************************/ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); diff --git a/stmhal/hal/inc/stm32f4xx_hal_pcd_ex.h b/stmhal/hal/inc/stm32f4xx_hal_pcd_ex.h new file mode 100644 index 000000000..8cd9f78f1 --- /dev/null +++ b/stmhal/hal/inc/stm32f4xx_hal_pcd_ex.h @@ -0,0 +1,78 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pcd_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-June-2014 + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_PCD_EX_H +#define __STM32F4xx_HAL_PCD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ + +/* Exported functions --------------------------------------------------------*/ + +/* Peripheral Extended functions *********************************************/ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_PCD_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_pwr.h b/stmhal/hal/inc/stm32f4xx_hal_pwr.h index 0bc900f5a..0f59ef8d2 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_pwr.h +++ b/stmhal/hal/inc/stm32f4xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -60,7 +60,7 @@ */ typedef struct { - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This parameter can be a value of @ref PWR_PVD_detection_level */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. @@ -81,10 +81,6 @@ typedef struct #define PVDE_BitNumber 0x04 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) -/* Alias word address of FPDS bit */ -#define FPDS_BitNumber 0x09 -#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) - /* Alias word address of PMODE bit */ #define PMODE_BitNumber 0x0E #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) @@ -94,10 +90,6 @@ typedef struct #define CSR_OFFSET (PWR_OFFSET + 0x04) #define EWUP_BitNumber 0x08 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* Alias word address of BRE bit */ -#define BRE_BitNumber 0x09 -#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) /** @defgroup PWR_Exported_Constants * @{ @@ -289,29 +281,41 @@ typedef struct */ #define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__)) +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled. + * This parameter can be: + * @arg PWR_EXTI_LINE_PVD + * @retval None + */ +#define __HAL_PVD_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) /* Include PWR HAL Extension module */ #include "stm32f4xx_hal_pwr_ex.h" /* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions *******************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); -/* Peripheral Control functions ************************************************/ -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); -void HAL_PWR_PVD_IRQHandler(void); +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVDCallback(void); diff --git a/stmhal/hal/inc/stm32f4xx_hal_pwr_ex.h b/stmhal/hal/inc/stm32f4xx_hal_pwr_ex.h index dd3635243..93866a9e1 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_pwr_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention @@ -54,12 +54,13 @@ * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* ------------- PWR registers bit address in the alias region ---------------*/ /* --- CR Register ---*/ +/* Alias word address of FPDS bit */ +#define FPDS_BitNumber 0x09 +#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) /* Alias word address of ODEN bit */ #define ODEN_BitNumber 0x10 @@ -69,7 +70,33 @@ #define ODSWEN_BitNumber 0x11 #define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) +/* Alias word address of MRLVDS bit */ +#define MRLVDS_BitNumber 0x0B +#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4)) +/* Alias word address of LPLVDS bit */ +#define LPLVDS_BitNumber 0x0A +#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of BRE bit */ +#define BRE_BitNumber 0x09 +#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + +/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode + * @{ + */ +#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS +#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) + +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) +/** + * @} + */ + /** @defgroup PWREx_Over_Under_Drive_Flag * @{ */ @@ -79,13 +106,14 @@ /** * @} */ - +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** @brief Macros to enable or disable the Over drive mode. * @note These macros can be used only for STM32F42xx/STM3243xx devices. */ @@ -138,9 +166,17 @@ void HAL_PWREx_DisableFlashPowerDown(void); HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +void HAL_PWREx_EnableMainRegulatorLowVoltage(void); +void HAL_PWREx_DisableMainRegulatorLowVoltage(void); +void HAL_PWREx_EnableLowRegulatorLowVoltage(void); +void HAL_PWREx_DisableLowRegulatorLowVoltage(void); +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void); HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** diff --git a/stmhal/hal/inc/stm32f4xx_hal_rcc.h b/stmhal/hal/inc/stm32f4xx_hal_rcc.h index 08b0ebd62..be558b357 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_rcc.h +++ b/stmhal/hal/inc/stm32f4xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -67,16 +67,16 @@ typedef struct uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ - uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK) - This parameter must be a value of @ref RCC_PLLP_Clock_Divider. */ + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ }RCC_PLLInitTypeDef; @@ -655,11 +655,15 @@ typedef struct /** @brief Force or release AHB2 peripheral reset. */ #define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) -#define __OTGFS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) -#define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/* alias define maintained for legacy */ +#define __OTGFS_FORCE_RESET __USB_OTG_FS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __USB_OTG_FS_RELEASE_RESET + #define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) @@ -764,9 +768,13 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#define __OTGFS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) -#define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +#define __USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +/* alias define maintained for legacy */ +#define __OTGFS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_SLEEP_DISABLE #define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) @@ -1042,11 +1050,6 @@ typedef struct */ #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) -/** @defgroup RCC_Flags_Interrupts_Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable * the selected interrupts). * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. @@ -1126,9 +1129,6 @@ typedef struct */ #define RCC_FLAG_MASK ((uint8_t)0x1F) #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) -/** - * @} - */ #define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC)) diff --git a/stmhal/hal/inc/stm32f4xx_hal_rcc_ex.h b/stmhal/hal/inc/stm32f4xx_hal_rcc_ex.h index 0abb47823..41b39e527 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_rcc_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -61,16 +61,16 @@ */ typedef struct { - uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock - This parameter must be a number between Min_Data = 192 and Max_Data = 432 + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 192 and Max_Data = 432. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock - This parameter must be a number between Min_Data = 2 and Max_Data = 7 + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15 + This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLI2S is selected as Clock Source SAI */ }RCC_PLLI2SInitTypeDef; @@ -80,15 +80,15 @@ typedef struct typedef struct { uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 192 and Max_Data = 432 + This parameter must be a number between Min_Data = 192 and Max_Data = 432. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15 + This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock - This parameter must be a number between Min_Data = 2 and Max_Data = 7 + This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ }RCC_PLLSAIInitTypeDef; @@ -100,13 +100,13 @@ typedef struct uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ - uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. This parameter must be a number between Min_Data = 1 and Max_Data = 32 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ @@ -117,27 +117,33 @@ typedef struct uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. This parameter can be a value of @ref RCC_RTC_Clock_Source */ - uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** * @brief PLLI2S Clock structure definition */ typedef struct { - uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock +#if defined(STM32F411xE) + uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ +#endif /* STM32F411xE */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 192 and Max_Data = 432 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock - This parameter must be a number between Min_Data = 2 and Max_Data = 7 + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ }RCC_PLLI2SInitTypeDef; @@ -151,14 +157,14 @@ typedef struct uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ }RCC_PeriphCLKInitTypeDef; -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Constants * @{ @@ -177,11 +183,12 @@ typedef struct #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F)) #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002) #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003)) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ /** * @} @@ -286,55 +293,67 @@ typedef struct * @} */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F411xE) +/** @defgroup RCCEx_PLLI2S_PLLI2SM + * @{ + */ +#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) /** * @} */ +/** @defgroup RCCEx_LSE_Dual_Mode_Selection + * @{ + */ +#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) +#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +/** + * @} + */ + +#endif /* STM32F411xE */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) /** @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ - -#if !defined(STM32F401xC) && !defined(STM32F401xE) -#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN)) -#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN)) -#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN)) -#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN)) -#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN)) -#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN)) -#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN)) -#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN)) +#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN)) +#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN)) +#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN)) +#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN)) +#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN)) +#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN)) +#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN)) +#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN)) +#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN)) +#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN)) +#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN)) #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN)) -#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) -#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) -#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) -#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) -#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) -#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) -#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) -#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) +#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) +#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) +#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) -#endif /* !(STM32F401xC && STM32F401xE) */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN)) -#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN)) -#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN)) - -#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) -#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) -#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ - -#if !defined(STM32F401xC) && !defined(STM32F401xE) /** * @brief Enable ETHERNET clock. */ @@ -343,58 +362,386 @@ typedef struct __ETHMACTX_CLK_ENABLE(); \ __ETHMACRX_CLK_ENABLE(); \ } while(0) +/** + * @brief Disable ETHERNET clock. + */ +#define __ETH_CLK_DISABLE() do { \ + __ETHMACTX_CLK_DISABLE(); \ + __ETHMACRX_CLK_DISABLE(); \ + __ETHMAC_CLK_DISABLE(); \ + } while(0) + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN)) +#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) +#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN)) +#define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN)) + +#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F437xx || STM32F439xx */ + +/** @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)) +#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) +#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) +#define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN)) +#define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN)) +#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN)) +#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) +#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) +#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN)) +#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN)) +#define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN)) +#define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN)) +#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) +#define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN)) +#define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN)) + +#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN)) +#define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN)) +#define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN)) +#define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN)) +#define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN)) +#define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN)) + +#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) +#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) +#define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN)) + +#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) +#endif /* STM32F429xx || STM32F439xx */ + +/** @brief Force or release AHB1 peripheral reset. + */ +#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) +#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) +#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) +#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) + +#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) +#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) +#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) +#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) + +/** @brief Force or release AHB2 peripheral reset. + */ +#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) +#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) + +#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F437xx || STM32F439xx */ + +/** @brief Force or release AHB3 peripheral reset + */ +#define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) + +/** @brief Force or release APB1 peripheral reset. + */ +#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) + +#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) + +/** @brief Force or release APB2 peripheral reset. + */ +#define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) +#define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) + +#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) +#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) +#define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) +#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F429xx|| STM32F439xx */ + +/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) +#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) +#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) +#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) +#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) + +#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) +#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) +#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) +#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) + +/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) +#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F437xx || STM32F439xx */ + +/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) + +#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) +#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) + +#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) +#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) + +#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +/*---------------------------------------------------------------------------------------------*/ + +/*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +/** @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN)) +#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN)) +#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN)) +#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN)) +#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN)) + +#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN)) +#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN)) +#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN)) +#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN)) +#define __ETH_CLK_ENABLE() do { \ + __ETHMAC_CLK_ENABLE(); \ + __ETHMACTX_CLK_ENABLE(); \ + __ETHMACRX_CLK_ENABLE(); \ + } while(0) /** * @brief Disable ETHERNET clock. */ +#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) #define __ETH_CLK_DISABLE() do { \ __ETHMACTX_CLK_DISABLE(); \ __ETHMACRX_CLK_DISABLE(); \ __ETHMAC_CLK_DISABLE(); \ } while(0) -#endif /* !(STM32F401xC && STM32F401xE) */ +#endif /* STM32F407xx || STM32F417xx */ /** @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) +#if defined(STM32F407xx)|| defined(STM32F417xx) #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN)) #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#endif /* !(STM32F401xC && STM32F401xE) */ +#endif /* STM32F407xx || STM32F417xx */ -#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx) +#if defined(STM32F415xx) || defined(STM32F417xx) #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN)) #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN)) #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) - -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ +#endif /* STM32F415xx || STM32F417xx */ /** @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN)) #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)) -#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ - /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN)) @@ -420,22 +767,12 @@ typedef struct #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#endif /* !(STM32F401xC && STM32F401xE) */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN)) -#define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN)) - -#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) -#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN)) #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN)) #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN)) @@ -443,23 +780,9 @@ typedef struct #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#endif /* !(STM32F401xC && STM32F401xE) */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN)) -#define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN)) -#define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN)) -#define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN)) - -#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) -#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) -#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) -#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** @brief Force or release AHB1 peripheral reset. */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) @@ -471,49 +794,30 @@ typedef struct #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) -#endif /* !STM32F401xC && STM32F401xE */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) -#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) -#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) - -#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) -#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) -#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - /** @brief Force or release AHB2 peripheral reset. */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) +#if defined(STM32F407xx)|| defined(STM32F417xx) #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -#endif /* !STM32F401xC && STM32F401xE */ +#endif /* STM32F407xx || STM32F417xx */ -#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx) +#if defined(STM32F415xx) || defined(STM32F417xx) #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ +#endif /* STM32F415xx || STM32F417xx */ /** @brief Force or release AHB3 peripheral reset */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) -#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - /** @brief Force or release APB1 peripheral reset. - */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) + */ #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) @@ -537,43 +841,18 @@ typedef struct #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#endif /* !STM32F401xC && STM32F401xE */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) -#define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) - -#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) -#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** @brief Force or release APB2 peripheral reset. */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -#endif /* !STM32F401xC && STM32F401xE */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) -#define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) -#define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) -#define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) - -#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) -#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) -#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) -#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) + */ #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) @@ -595,18 +874,6 @@ typedef struct #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) -#endif /* !STM32F401xC && STM32F401xE */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) -#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) -#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) -#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) - -#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) -#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) -#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -614,19 +881,18 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) +#if defined(STM32F407xx)|| defined(STM32F417xx) #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) -#endif /* !STM32F401xC && STM32F401xE */ +#endif /* STM32F407xx || STM32F417xx */ -#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx) +#if defined(STM32F415xx) || defined(STM32F417xx) #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) - -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ +#endif /* STM32F415xx || STM32F417xx */ /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -634,15 +900,8 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx) -#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) -#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -650,7 +909,6 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) @@ -674,23 +932,13 @@ typedef struct #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#endif /* !STM32F401xC && STM32F401xE */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) -#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) - -#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) -#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#if !defined(STM32F401xC) && !defined(STM32F401xE) + */ #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) @@ -698,21 +946,31 @@ typedef struct #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) -#endif /* !STM32F401xC && STM32F401xE */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +/*---------------------------------------------------------------------------------------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +/*------------------------------------------ STM32F411xx --------------------------------------*/ +#if defined(STM32F411xE) +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + */ +#define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN)) +#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) + +/** @brief Force or release APB2 peripheral reset. + */ +#define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + */ #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) -#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) -#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) - #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) -#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) -#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) -#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#endif /* STM32F411xE */ +/*---------------------------------------------------------------------------------------------*/ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** @brief Macro to configure the Timers clocks prescalers * @note This feature is only available with STM32F429x/439x Devices. @@ -729,6 +987,36 @@ typedef struct */ #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F411xE) + +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLLI2S jitter. + * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 192 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. + * @param __PLLI2SR__: specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ + ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__)) +#endif /* STM32F411xE */ + + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /** @brief Macros to Enable or Disable the PLLISAI. * @note The PLLSAI is only available with STM32F429x/439x Devices. * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. @@ -857,6 +1145,9 @@ typedef struct HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +#if defined(STM32F411xE) +void HAL_RCCEx_SelectLSEMode(uint8_t Mode); +#endif /* STM32F411xE */ /** * @} */ diff --git a/stmhal/hal/inc/stm32f4xx_hal_rng.h b/stmhal/hal/inc/stm32f4xx_hal_rng.h index ad89d5554..17d25cf85 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_rng.h +++ b/stmhal/hal/inc/stm32f4xx_hal_rng.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rng.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention @@ -43,6 +43,8 @@ extern "C" { #endif +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -121,6 +123,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset RNG handle state + * @param __HANDLE__: RNG Handle + * @retval None + */ +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) + /** * @brief Enables the RNG peripheral. * @param __HANDLE__: RNG Handle @@ -149,7 +157,7 @@ typedef struct * @param __FLAG__: RNG flag * @retval None */ -#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__)) +#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** * @brief Enables the RNG interrupts. @@ -195,6 +203,8 @@ void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); /* Peripheral State functions **************************************************/ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + /** * @} */ diff --git a/stmhal/hal/inc/stm32f4xx_hal_rtc.h b/stmhal/hal/inc/stm32f4xx_hal_rtc.h index 0329faf7f..c612e5bc5 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_rtc.h +++ b/stmhal/hal/inc/stm32f4xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -98,7 +98,7 @@ typedef struct typedef struct { uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ uint8_t Minutes; /*!< Specifies the RTC Time Minutes. @@ -113,7 +113,7 @@ typedef struct uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. + uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation. This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit @@ -542,6 +542,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset RTC handle state + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) + /** * @brief Disable the write protection for RTC registers. * @param __HANDLE__: specifies the RTC handle. @@ -657,34 +663,55 @@ typedef struct * @brief Enable the RTC Exti line. * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT * @retval None - */ -#define __HAL_RTC_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) + */ +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT /** * @brief Disable the RTC Exti line. * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT * @retval None */ -#define __HAL_RTC_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) /** * @brief Clear the RTC Exti flags. * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled. * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT * @retval None */ -#define __HAL_RTC_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) +#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG + /* Include RTC HAL Extension module */ #include "stm32f4xx_hal_rtc_ex.h" diff --git a/stmhal/hal/inc/stm32f4xx_hal_rtc_ex.h b/stmhal/hal/inc/stm32f4xx_hal_rtc_ex.h index 6d8160abb..79d035751 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_rtc_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention @@ -335,7 +335,7 @@ typedef struct * @} */ -/** @defgroup RTC_Smooth_calib_period_Definitions +/** @defgroup RTCEx_Smooth_calib_period_Definitions * @{ */ #define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation diff --git a/stmhal/hal/inc/stm32f4xx_hal_sai.h b/stmhal/hal/inc/stm32f4xx_hal_sai.h index f88f54676..f435d6e23 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_sai.h +++ b/stmhal/hal/inc/stm32f4xx_hal_sai.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sai.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention @@ -177,35 +177,34 @@ typedef enum typedef struct { SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ - + SAI_InitTypeDef Init; /*!< SAI communication parameters */ - + SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ - + SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ - - uint16_t *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< SAI Tx transfer size */ - - uint16_t TxXferCount; /*!< SAI Tx transfer counter */ - - uint16_t *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer */ - - uint16_t RxXferSize; /*!< SAI Rx transfer size */ - - uint16_t RxXferCount; /*!< SAI Rx transfer counter */ - - DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ - HAL_LockTypeDef Lock; /*!< SAI locking object */ - - __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ - - __IO uint32_t ErrorCode; /*!< SAI Error code */ + uint16_t *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer */ + uint16_t TxXferSize; /*!< SAI Tx transfer size */ + + uint16_t TxXferCount; /*!< SAI Tx transfer counter */ + + uint16_t *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer */ + + uint16_t RxXferSize; /*!< SAI Rx transfer size */ + + uint16_t RxXferCount; /*!< SAI Rx transfer counter */ + + DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< SAI locking object */ + + __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ + + __IO uint32_t ErrorCode; /*!< SAI Error code */ }SAI_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -218,7 +217,7 @@ typedef struct */ #define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */ -#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */ +#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */ #define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ /** * @} @@ -236,7 +235,7 @@ typedef struct ((SOURCE) == SAI_CLKSOURCE_EXT)) /** * @} - */ + */ /** @defgroup SAI_Audio_Frequency * @{ @@ -462,8 +461,8 @@ typedef struct /** @defgroup SAI_Block_Slot_Active * @{ */ -#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000) -#define SAI_SLOTACTIVE_0 ((uint32_t)0x00010000) +#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000) +#define SAI_SLOTACTIVE_0 ((uint32_t)0x00010000) #define SAI_SLOTACTIVE_1 ((uint32_t)0x00020000) #define SAI_SLOTACTIVE_2 ((uint32_t)0x00040000) #define SAI_SLOTACTIVE_3 ((uint32_t)0x00080000) @@ -645,6 +644,11 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset SAI handle state + * @param __HANDLE__: specifies the SAI Handle. + * @retval None + */ +#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) /** @brief Enable or disable the specified SAI interrupts. * @param __HANDLE__: specifies the SAI Handle. @@ -704,7 +708,7 @@ typedef struct * * @retval None */ -#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR |= (__FLAG__)) +#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) diff --git a/stmhal/hal/inc/stm32f4xx_hal_sd.h b/stmhal/hal/inc/stm32f4xx_hal_sd.h index 359dbec10..93bacc5da 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_sd.h +++ b/stmhal/hal/inc/stm32f4xx_hal_sd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sd.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of SD HAL module. ****************************************************************************** * @attention @@ -55,6 +55,9 @@ */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup SD_Exported_Types + * @{ + */ #define SD_InitTypeDef SDIO_InitTypeDef #define SD_TypeDef SDIO_TypeDef @@ -63,11 +66,11 @@ */ typedef struct { - SD_TypeDef *Instance; /*!< SDIO register base address */ + SD_TypeDef *Instance; /*!< SDIO register base address */ SD_InitTypeDef Init; /*!< SD required parameters */ - HAL_LockTypeDef Lock; /*!< SD locking object */ + HAL_LockTypeDef Lock; /*!< SD locking object */ uint32_t CardType; /*!< SD card type */ @@ -79,13 +82,13 @@ typedef struct __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */ - __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */ + __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */ __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */ __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */ - DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ @@ -199,7 +202,7 @@ typedef enum SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ SD_DATA_TIMEOUT = (4), /*!< Data timeout */ SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */ - SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */ + SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */ SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */ SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */ SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ @@ -231,20 +234,20 @@ typedef enum /** * @brief Standard error defines */ - SD_INTERNAL_ERROR = (34), + SD_INTERNAL_ERROR = (34), SD_NOT_CONFIGURED = (35), - SD_REQUEST_PENDING = (36), - SD_REQUEST_NOT_APPLICABLE = (37), - SD_INVALID_PARAMETER = (38), - SD_UNSUPPORTED_FEATURE = (39), - SD_UNSUPPORTED_HW = (40), - SD_ERROR = (41), + SD_REQUEST_PENDING = (36), + SD_REQUEST_NOT_APPLICABLE = (37), + SD_INVALID_PARAMETER = (38), + SD_UNSUPPORTED_FEATURE = (39), + SD_UNSUPPORTED_HW = (40), + SD_ERROR = (41), SD_OK = (0) }HAL_SD_ErrorTypedef; /** - * @brief SD Transfer state enumeration structure + * @brief SD Transfer state enumeration structure */ typedef enum { @@ -394,7 +397,7 @@ typedef enum /* Exported macro ------------------------------------------------------------*/ -/** @defgroup SD_Interrupt_Clock +/** @defgroup SD_Exported_macros * @brief macros to handle interrupts and specific clock configurations * @{ */ @@ -606,14 +609,26 @@ typedef enum */ /* Exported functions --------------------------------------------------------*/ - -/* Initialization/de-initialization functions **********************************/ +/** @addtogroup SD_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup SD_Group1 + * @{ + */ HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo); HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); void HAL_SD_MspInit(SD_HandleTypeDef *hsd); void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); - -/* I/O operation functions *****************************************************/ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup SD_Group2 + * @{ + */ /* Blocking mode: Polling */ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); @@ -635,18 +650,37 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); - -/* Peripheral Control functions ************************************************/ +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup SD_Group3 + * @{ + */ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo); HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode); HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd); HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd); - -/* Peripheral State functions **************************************************/ +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup SD_Group4 + * @{ + */ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus); HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); - +/** + * @} + */ + +/** + * @} + */ + /** * @} */ diff --git a/stmhal/hal/inc/stm32f4xx_hal_sdram.h b/stmhal/hal/inc/stm32f4xx_hal_sdram.h index 17df79135..d6bc4c1d9 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_sdram.h +++ b/stmhal/hal/inc/stm32f4xx_hal_sdram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sdram.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention @@ -89,8 +89,15 @@ typedef struct }SDRAM_HandleTypeDef; -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset SDRAM handle state + * @param __HANDLE__: specifies the SDRAM handle. + * @retval None + */ +#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) + /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions **********************************/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_smartcard.h b/stmhal/hal/inc/stm32f4xx_hal_smartcard.h index d501286b6..8c216532f 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_smartcard.h +++ b/stmhal/hal/inc/stm32f4xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_smartcard.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -91,13 +91,13 @@ typedef struct data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler + uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler. This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ - uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time + uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time. This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ - uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state + uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state. This parameter can be a value of @ref SmartCard_NACK_State */ }SMARTCARD_InitTypeDef; @@ -106,13 +106,14 @@ typedef struct */ typedef enum { - HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ + HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ + HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ }HAL_SMARTCARD_StateTypeDef; /** @@ -313,6 +314,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset SMARTCARD handle state + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) + /** @brief Flushs the Smartcard DR register * @param __HANDLE__: specifies the SMARTCARD Handle. */ @@ -349,7 +356,48 @@ typedef struct * USART_SR register followed by a write operation to USART_DR register. * @note TXE flag is cleared only by a write to the USART_DR register. */ -#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__)) +#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clear the SMARTCARD PE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->DR;}while(0) +/** @brief Clear the SMARTCARD FE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the SMARTCARD NE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the SMARTCARD ORE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the SMARTCARD IDLE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) + /** @brief Enables or disables the specified SmartCard interrupts. * @param __HANDLE__: specifies the SMARTCARD Handle. diff --git a/stmhal/hal/inc/stm32f4xx_hal_spi.h b/stmhal/hal/inc/stm32f4xx_hal_spi.h index 372bac21e..d4dfab170 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_spi.h +++ b/stmhal/hal/inc/stm32f4xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -346,6 +346,13 @@ typedef struct __SPI_HandleTypeDef /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset SPI handle state + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) + /** @brief Enable or disable the specified SPI interrupts. * @param __HANDLE__: specifies the SPI handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. @@ -392,7 +399,7 @@ typedef struct __SPI_HandleTypeDef * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= ~(SPI_FLAG_CRCERR)) +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. * @param __HANDLE__: specifies the SPI handle. @@ -447,11 +454,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); /* Peripheral State and Control functions **************************************/ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); diff --git a/stmhal/hal/inc/stm32f4xx_hal_sram.h b/stmhal/hal/inc/stm32f4xx_hal_sram.h index d6aabc28f..132a274a8 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_sram.h +++ b/stmhal/hal/inc/stm32f4xx_hal_sram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sram.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -97,8 +97,15 @@ typedef struct }SRAM_HandleTypeDef; -/* Exported constants --------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset SRAM handle state + * @param __HANDLE__: SRAM handle + * @retval None + */ +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) + /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions **********************************/ diff --git a/stmhal/hal/inc/stm32f4xx_hal_tim.h b/stmhal/hal/inc/stm32f4xx_hal_tim.h index 92edc17cb..df837f506 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_tim.h +++ b/stmhal/hal/inc/stm32f4xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -52,9 +52,9 @@ /** @addtogroup TIM * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** * @brief TIM Time base Configuration Structure definition @@ -69,7 +69,7 @@ typedef struct uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ @@ -89,12 +89,12 @@ typedef struct */ typedef struct -{ +{ uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ @@ -121,12 +121,12 @@ typedef struct * @brief TIM One Pulse Mode Configuration Structure definition */ typedef struct -{ +{ uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ @@ -159,7 +159,7 @@ typedef struct */ typedef struct -{ +{ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -204,7 +204,7 @@ typedef struct This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; /** @@ -212,14 +212,14 @@ typedef struct */ typedef struct { - uint32_t ClockSource; /*!< TIM clock sources + uint32_t ClockSource; /*!< TIM clock sources. This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity + uint32_t ClockPolarity; /*!< TIM clock polarity. This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler + uint32_t ClockPrescaler; /*!< TIM clock prescaler. This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a value of @ref TIM_Clock_Filter */ + uint32_t ClockFilter; /*!< TIM clock filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_ClockConfigTypeDef; /** @@ -227,16 +227,16 @@ typedef struct */ typedef struct { - uint32_t ClearInputState; /*!< TIM clear Input state + uint32_t ClearInputState; /*!< TIM clear Input state. This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources + uint32_t ClearInputSource; /*!< TIM clear Input sources. This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a value of @ref TIM_ClearInput_Filter */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_ClearInputConfigTypeDef; /** @@ -252,7 +252,7 @@ typedef struct { uint32_t TriggerPrescaler; /*!< Input trigger prescaler This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a value of @ref TIM_Trigger_Filter */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_SlaveConfigTypeDef; @@ -263,9 +263,9 @@ typedef enum { HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ }HAL_TIM_StateTypeDef; /** @@ -275,9 +275,9 @@ typedef enum { HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ }HAL_TIM_ActiveChannel; /** @@ -285,13 +285,13 @@ typedef enum */ typedef struct { - TIM_TypeDef *Instance; /*!< Register base address */ + TIM_TypeDef *Instance; /*!< Register base address */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ }TIM_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -312,15 +312,15 @@ typedef struct /** @defgroup TIM_ETR_Polarity * @{ */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ /** * @} */ /** @defgroup TIM_ETR_Prescaler * @{ - */ + */ #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ @@ -332,7 +332,6 @@ typedef struct /** @defgroup TIM_Counter_Mode * @{ */ - #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 @@ -346,12 +345,11 @@ typedef struct ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) /** * @} - */ - + */ + /** @defgroup TIM_ClockDivision * @{ */ - #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) @@ -366,7 +364,6 @@ typedef struct /** @defgroup TIM_Output_Compare_and_PWM_modes * @{ */ - #define TIM_OCMODE_TIMING ((uint32_t)0x0000) #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) @@ -392,7 +389,6 @@ typedef struct /** @defgroup TIM_Output_Compare_State * @{ */ - #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) @@ -400,7 +396,8 @@ typedef struct ((STATE) == TIM_OUTPUTSTATE_ENABLE)) /** * @} - */ + */ + /** @defgroup TIM_Output_Fast_State * @{ */ @@ -411,11 +408,11 @@ typedef struct ((STATE) == TIM_OCFAST_ENABLE)) /** * @} - */ + */ + /** @defgroup TIM_Output_Compare_N_State * @{ */ - #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) @@ -424,11 +421,10 @@ typedef struct /** * @} */ - + /** @defgroup TIM_Output_Compare_Polarity * @{ */ - #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) @@ -441,7 +437,6 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Polarity * @{ */ - #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) @@ -454,7 +449,6 @@ typedef struct /** @defgroup TIM_Output_Compare_Idle_State * @{ */ - #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ @@ -466,7 +460,6 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Idle_State * @{ */ - #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ @@ -478,7 +471,6 @@ typedef struct /** @defgroup TIM_Channel * @{ */ - #define TIM_CHANNEL_1 ((uint32_t)0x0000) #define TIM_CHANNEL_2 ((uint32_t)0x0004) #define TIM_CHANNEL_3 ((uint32_t)0x0008) @@ -495,35 +487,32 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_2)) #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) + ((CHANNEL) == TIM_CHANNEL_2)) #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3)) /** * @} - */ - + */ /** @defgroup TIM_Input_Capture_Polarity * @{ */ - #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE - + #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) /** * @} - */ + */ /** @defgroup TIM_Input_Capture_Selection * @{ */ - #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be @@ -535,12 +524,11 @@ typedef struct ((SELECTION) == TIM_ICSELECTION_TRC)) /** * @} - */ + */ /** @defgroup TIM_Input_Capture_Prescaler * @{ */ - #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ @@ -557,17 +545,17 @@ typedef struct /** @defgroup TIM_One_Pulse_Mode * @{ */ - #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ ((MODE) == TIM_OPMODE_REPETITIVE)) /** * @} - */ + */ + /** @defgroup TIM_Encoder_Mode * @{ - */ + */ #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) @@ -576,7 +564,8 @@ typedef struct ((MODE) == TIM_ENCODERMODE_TI12)) /** * @} - */ + */ + /** @defgroup TIM_Interrupt_definition * @{ */ @@ -598,7 +587,7 @@ typedef struct ((IT) == TIM_IT_CC4) || \ ((IT) == TIM_IT_COM) || \ ((IT) == TIM_IT_TRIGGER) || \ - ((IT) == TIM_IT_BREAK)) + ((IT) == TIM_IT_BREAK)) /** * @} */ @@ -608,7 +597,6 @@ typedef struct /** @defgroup TIM_DMA_sources * @{ */ - #define TIM_DMA_UPDATE (TIM_DIER_UDE) #define TIM_DMA_CC1 (TIM_DIER_CC1DE) #define TIM_DMA_CC2 (TIM_DIER_CC2DE) @@ -617,15 +605,13 @@ typedef struct #define TIM_DMA_COM (TIM_DIER_COMDE) #define TIM_DMA_TRIGGER (TIM_DIER_TDE) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) - /** * @} */ - + /** @defgroup TIM_Event_Source * @{ */ - #define TIM_EventSource_Update TIM_EGR_UG #define TIM_EventSource_CC1 TIM_EGR_CC1G #define TIM_EventSource_CC2 TIM_EGR_CC2G @@ -634,16 +620,14 @@ typedef struct #define TIM_EventSource_COM TIM_EGR_COMG #define TIM_EventSource_Trigger TIM_EGR_TG #define TIM_EventSource_Break TIM_EGR_BG -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) - +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) /** * @} - */ + */ /** @defgroup TIM_Flag_definition * @{ - */ - + */ #define TIM_FLAG_UPDATE (TIM_SR_UIF) #define TIM_FLAG_CC1 (TIM_SR_CC1IF) #define TIM_FLAG_CC2 (TIM_SR_CC2IF) @@ -668,14 +652,14 @@ typedef struct ((FLAG) == TIM_FLAG_CC1OF) || \ ((FLAG) == TIM_FLAG_CC2OF) || \ ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) + ((FLAG) == TIM_FLAG_CC4OF)) /** * @} */ /** @defgroup TIM_Clock_Source * @{ - */ + */ #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) @@ -699,7 +683,7 @@ typedef struct ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) /** * @} - */ + */ /** @defgroup TIM_Clock_Polarity * @{ @@ -718,9 +702,10 @@ typedef struct /** * @} */ + /** @defgroup TIM_Clock_Prescaler * @{ - */ + */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ @@ -732,15 +717,15 @@ typedef struct ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) /** * @} - */ + */ + /** @defgroup TIM_Clock_Filter * @{ */ - #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} - */ + */ /** @defgroup TIM_ClearInput_Source * @{ @@ -763,7 +748,7 @@ typedef struct ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) /** * @} - */ + */ /** @defgroup TIM_ClearInput_Prescaler * @{ @@ -779,15 +764,14 @@ typedef struct /** * @} */ - + /** @defgroup TIM_ClearInput_Filter * @{ */ - #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} - */ + */ /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state * @{ @@ -882,7 +866,7 @@ typedef struct ((SOURCE) == TIM_TRGO_OC3REF) || \ ((SOURCE) == TIM_TRGO_OC4REF)) - + /** * @} */ @@ -902,7 +886,7 @@ typedef struct ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) /** * @} - */ + */ /** @defgroup TIM_Master_Slave_Mode * @{ @@ -918,7 +902,6 @@ typedef struct /** @defgroup TIM_Trigger_Selection * @{ */ - #define TIM_TS_ITR0 ((uint32_t)0x0000) #define TIM_TS_ITR1 ((uint32_t)0x0010) #define TIM_TS_ITR2 ((uint32_t)0x0020) @@ -969,7 +952,7 @@ typedef struct /** @defgroup TIM_Trigger_Prescaler * @{ - */ + */ #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ @@ -986,30 +969,26 @@ typedef struct /** @defgroup TIM_Trigger_Filter * @{ */ - #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} - */ + */ /** @defgroup TIM_TI1_Selection * @{ */ - #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) - /** * @} */ - + /** @defgroup TIM_DMA_Base_address * @{ */ - #define TIM_DMABase_CR1 (0x00000000) #define TIM_DMABase_CR2 (0x00000001) #define TIM_DMABase_SMCR (0x00000002) @@ -1049,7 +1028,7 @@ typedef struct ((BASE) == TIM_DMABase_CCR4) || \ ((BASE) == TIM_DMABase_BDTR) || \ ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) + ((BASE) == TIM_DMABase_OR)) /** * @} */ @@ -1057,7 +1036,6 @@ typedef struct /** @defgroup TIM_DMA_Burst_Length * @{ */ - #define TIM_DMABurstLength_1Transfer (0x00000000) #define TIM_DMABurstLength_2Transfers (0x00000100) #define TIM_DMABurstLength_3Transfers (0x00000200) @@ -1096,11 +1074,11 @@ typedef struct ((LENGTH) == TIM_DMABurstLength_18Transfers)) /** * @} - */ + */ + /** @defgroup TIM_Input_Capture_Filer_Value * @{ */ - #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} @@ -1137,6 +1115,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset TIM handle state + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) + /** * @brief Enable the TIM peripheral. * @param __HANDLE__: TIM handle @@ -1173,8 +1157,8 @@ typedef struct } \ } while(0) -/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ +/* The Main Output of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ /** * @brief Disable the TIM main Output. * @param __HANDLE__: TIM handle @@ -1189,20 +1173,20 @@ typedef struct (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ - } while(0) + } while(0) #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__)) +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= ~(__INTERRUPT__)) +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) -#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC |= (__PRESC__)) +#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ @@ -1215,7 +1199,7 @@ typedef struct ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) - + /** * @brief Sets the TIM Capture Compare Register value on runtime without * calling another time ConfigChannel function. @@ -1232,13 +1216,34 @@ typedef struct #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) +/** + * @brief Gets the TIM Capture Compare Register value on runtime + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval None + */ +#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) + /** * @brief Sets the TIM Counter Register value on runtime. * @param __HANDLE__: TIM handle. * @param __COUNTER__: specifies the Counter register new value. * @retval None */ -#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) +#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Gets the TIM Counter Register value on runtime. + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Sets the TIM Autoreload Register value on runtime without calling @@ -1247,11 +1252,17 @@ typedef struct * @param __AUTORELOAD__: specifies the Counter register new value. * @retval None */ -#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ +#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ } while(0) +/** + * @brief Gets the TIM Autoreload Register value on runtime + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Sets the TIM Clock Division value on runtime without calling @@ -1261,16 +1272,22 @@ typedef struct * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1 * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 + * @arg TIM_CLOCKDIVISION_DIV4 * @retval None */ #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ - do{ \ + do{ \ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while(0) - +/** + * @brief Gets the TIM Clock Division value on runtime + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + /** * @brief Sets the TIM Input Capture prescaler on runtime without calling * another time HAL_TIM_IC_ConfigChannel() function. @@ -1293,8 +1310,24 @@ typedef struct do{ \ __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) + } while(0) +/** + * @brief Gets the TIM Input Capture prescaler on runtime + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval None + */ +#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) /** * @} */ diff --git a/stmhal/hal/inc/stm32f4xx_hal_tim_ex.h b/stmhal/hal/inc/stm32f4xx_hal_tim_ex.h index 8ef621be2..9a1b878e1 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_tim_ex.h +++ b/stmhal/hal/inc/stm32f4xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention @@ -79,9 +79,9 @@ typedef struct * @brief TIM Master configuration Structure definition */ typedef struct { - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection. This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection + uint32_t MasterSlaveMode; /*!< Master/slave mode selection. This parameter can be a value of @ref TIM_Master_Slave_Mode */ }TIM_MasterConfigTypeDef; @@ -90,19 +90,19 @@ typedef struct { */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode + uint32_t OffStateRunMode; /*!< TIM off state in run mode. This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode. This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level + uint32_t LockLevel; /*!< TIM Lock level. This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time + uint32_t DeadTime; /*!< TIM dead Time. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State + uint32_t BreakState; /*!< TIM Break State. This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity + uint32_t BreakPolarity; /*!< TIM Break input polarity. This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state. This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ }TIM_BreakDeadTimeConfigTypeDef; @@ -110,7 +110,7 @@ typedef struct /** @defgroup TIMEx_Exported_Constants * @{ */ - + /** @defgroup TIMEx_Remap * @{ */ diff --git a/stmhal/hal/inc/stm32f4xx_hal_uart.h b/stmhal/hal/inc/stm32f4xx_hal_uart.h index 99d308997..a957bec7b 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_uart.h +++ b/stmhal/hal/inc/stm32f4xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -300,19 +300,32 @@ typedef struct #define UART_IT_LBD ((uint32_t)0x20000040) #define UART_IT_CTS ((uint32_t)0x30000400) - + #define UART_IT_ERR ((uint32_t)0x30000001) /** * @} */ - + /** * @} */ /* Exported macro ------------------------------------------------------------*/ - + +/** @brief Reset UART handle state + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) + +/** @brief Flushs the UART DR register + * @param __HANDLE__: specifies the UART Handle. + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + /** @brief Checks whether the specified UART flag is set or not. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or @@ -356,8 +369,48 @@ typedef struct * * @retval None */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__)) +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->DR;}while(0) +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + /** @brief Enables or disables the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or @@ -402,6 +455,82 @@ typedef struct #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) +/** @brief Enable CTS flow control + * This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * The Handle Instance can be USART1, USART2 or LPUART. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0) + +/** @brief Disable CTS flow control + * This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * The Handle Instance can be USART1, USART2 or LPUART. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0) + +/** @brief Enable RTS flow control + * This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * The Handle Instance can be USART1, USART2 or LPUART. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0) + +/** @brief Disable RTS flow control + * This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * The Handle Instance can be USART1, USART2 or LPUART. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0) + /** @brief macros to enables or disables the UART's one bit sampling method * @param __HANDLE__: specifies the UART Handle. * @retval None diff --git a/stmhal/hal/inc/stm32f4xx_hal_usart.h b/stmhal/hal/inc/stm32f4xx_hal_usart.h index f73a6557f..7a36cabe1 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_usart.h +++ b/stmhal/hal/inc/stm32f4xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_usart.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -62,7 +62,7 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate))) + - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate))) - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. @@ -251,7 +251,7 @@ typedef struct * @} */ -/** @defgroup Usart_NACK_State +/** @defgroup USART_NACK_State * @{ */ #define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK) @@ -262,7 +262,7 @@ typedef struct * @} */ -/** @defgroup Usart_Flags +/** @defgroup USART_Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the SR register * @{ @@ -298,24 +298,29 @@ typedef struct #define USART_IT_LBD ((uint32_t)0x20000040) #define USART_IT_CTS ((uint32_t)0x30000400) - + #define USART_IT_ERR ((uint32_t)0x30000001) /** * @} */ - + /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset USART handle state + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) /** @brief Checks whether the specified Smartcard flag is set or not. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg USART_FLAG_TXE: Transmit data register empty flag @@ -333,8 +338,7 @@ typedef struct /** @brief Clears the specified Smartcard pending flags. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: * @arg USART_FLAG_TC: Transmission Complete flag. @@ -351,13 +355,46 @@ typedef struct * * @retval None */ -#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__)) +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->DR;}while(0) +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the USART NE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the USART IDLE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Enables or disables the specified Usart interrupts. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @param __INTERRUPT__: specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt @@ -381,8 +418,7 @@ typedef struct /** @brief Checks whether the specified Usart interrupt has occurred or not. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. + * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @param __IT__: specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt diff --git a/stmhal/hal/inc/stm32f4xx_hal_wwdg.h b/stmhal/hal/inc/stm32f4xx_hal_wwdg.h index 1c0c6a00c..c7ebda102 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_wwdg.h +++ b/stmhal/hal/inc/stm32f4xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -54,19 +54,18 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ -/** - * @brief WWDG HAL State Structure definition - */ +/** + * @brief WWDG HAL State Structure definition + */ typedef enum { HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */ HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */ - HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ + HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */ HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ - }HAL_WWDG_StateTypeDef; /** @@ -74,14 +73,14 @@ typedef enum */ typedef struct { - uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. This parameter can be a value of @ref WWDG_Prescaler */ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number lower than Max_Data = 0x80 */ - uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. - This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ }WWDG_InitTypeDef; @@ -90,7 +89,7 @@ typedef struct */ typedef struct { - WWDG_TypeDef *Instance; /*!< Register base address */ + WWDG_TypeDef *Instance; /*!< Register base address */ WWDG_InitTypeDef Init; /*!< WWDG required parameters */ @@ -107,6 +106,7 @@ typedef struct */ /** @defgroup WWDG_BitAddress_AliasRegion + * @brief WWDG registers bit address in the alias region * @{ */ @@ -123,7 +123,7 @@ typedef struct */ #define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI) -#define IS_WWDG_IT(IT) ((IT) == WWDG_IT_EWI) +#define IS_WWDG_IT(__IT__) ((__IT__) == WWDG_IT_EWI) /** * @} @@ -133,26 +133,26 @@ typedef struct * @brief WWDG Flag definition * @{ */ -#define WWDG_FLAG_EWIF ((uint32_t)0x0001) /*!< Early wakeup interrupt flag */ +#define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */ +#define IS_WWDG_FLAG(__FLAG__) ((__FLAG__) == WWDG_FLAG_EWIF)) -#define IS_WWDG_FLAG(FLAG) ((FLAG) == WWDG_FLAG_EWIF)) /** * @} */ - + /** @defgroup WWDG_Prescaler * @{ */ #define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 ((uint32_t)0x00000080) /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 ((uint32_t)0x00000100) /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 ((uint32_t)0x00000180) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */ -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_PRESCALER_1) || \ - ((PRESCALER) == WWDG_PRESCALER_2) || \ - ((PRESCALER) == WWDG_PRESCALER_4) || \ - ((PRESCALER) == WWDG_PRESCALER_8)) +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ + ((__PRESCALER__) == WWDG_PRESCALER_8)) /** * @} @@ -161,7 +161,7 @@ typedef struct /** @defgroup WWDG_Window * @{ */ -#define IS_WWDG_WINDOW(WINDOW) ((WINDOW) <= 0x7F) +#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) /** * @} @@ -170,24 +170,30 @@ typedef struct /** @defgroup WWDG_Counter * @{ */ -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) /** * @} */ +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset WWDG handle state + * @param __HANDLE__: WWDG handle + * @retval None + */ +#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET) + /** * @brief Enables the WWDG peripheral. * @param __HANDLE__: WWDG handle * @retval None */ -#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA) +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) /** * @brief Gets the selected WWDG's flag status. @@ -207,16 +213,26 @@ typedef struct * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval None */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__)) +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** * @brief Enables the WWDG early wakeup interrupt. + * @param __INTERRUPT__: specifies the interrupt to enable. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early wakeup interrupt * @note Once enabled this interrupt cannot be disabled except by a system reset. * @retval None */ #define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__)) - +/** @brief Clear the WWDG's interrupt pending bits + * bits to clear the selected interrupt pending bits. + * @param __HANDLE__: WWDG handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + */ +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions **********************************/ diff --git a/stmhal/hal/inc/stm32f4xx_ll_fmc.h b/stmhal/hal/inc/stm32f4xx_ll_fmc.h index 7653665e7..83278104b 100644 --- a/stmhal/hal/inc/stm32f4xx_ll_fmc.h +++ b/stmhal/hal/inc/stm32f4xx_ll_fmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fmc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention @@ -63,70 +63,69 @@ #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef -#define FMC_NORSRAM_DEVICE FMC_Bank1 -#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E -#define FMC_NAND_DEVICE FMC_Bank2_3 -#define FMC_PCCARD_DEVICE FMC_Bank4 -#define FMC_SDRAM_DEVICE FMC_Bank5_6 - +#define FMC_NORSRAM_DEVICE FMC_Bank1 +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E +#define FMC_NAND_DEVICE FMC_Bank2_3 +#define FMC_PCCARD_DEVICE FMC_Bank4 +#define FMC_SDRAM_DEVICE FMC_Bank5_6 /** - * @brief FMC_NORSRAM Configuration Structure definition + * @brief FMC_NORSRAM Configuration Structure definition */ typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ - + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ - + uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. This parameter can be a value of @ref FMC_Memory_Type */ - + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ - + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of @ref FMC_Burst_Access_Mode */ - + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ - + uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FMC_Wrap_Mode */ - + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of @ref FMC_Wait_Timing */ - + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. This parameter can be a value of @ref FMC_Write_Operation */ - + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of @ref FMC_Wait_Signal */ - + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. This parameter can be a value of @ref FMC_Extended_Mode */ - + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of @ref FMC_AsynchronousWait */ - + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ - + This parameter can be a value of @ref FMC_Write_Burst */ + uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ }FMC_NORSRAM_InitTypeDef; @@ -139,28 +138,28 @@ typedef struct the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. @note This parameter is not used with synchronous NOR Flash memories. */ - + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between Min_Data = 1 and Max_Data = 15. @note This parameter is not used with synchronous NOR Flash memories. */ - + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. @note This parameter is only used for multiplexed NOR Flash memories. */ - + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: @@ -168,10 +167,9 @@ typedef struct - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories with synchronous burst mode enable */ - + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FMC_Access_Mode */ - }FMC_NORSRAM_TimingTypeDef; /** @@ -180,29 +178,28 @@ typedef struct typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ - + This parameter can be a value of @ref FMC_NAND_Bank */ + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. This parameter can be any value of @ref FMC_Wait_feature */ - + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be any value of @ref FMC_NAND_Data_Width */ - + uint32_t EccComputation; /*!< Enables or disables the ECC computation. This parameter can be any value of @ref FMC_ECC */ - + uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. This parameter can be any value of @ref FMC_ECC_Page_Size */ - + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - -}FMC_NAND_InitTypeDef; +}FMC_NAND_InitTypeDef; /** * @brief FMC_NAND_PCCARD Timing parameters structure definition @@ -214,45 +211,43 @@ typedef struct to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - + uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - + uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - + uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - }FMC_NAND_PCC_TimingTypeDef; /** - * @brief FMC_NAND Configuration Structure definition + * @brief FMC_NAND Configuration Structure definition */ typedef struct { uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. This parameter can be any value of @ref FMC_Wait_feature */ - + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - -}FMC_PCCARD_InitTypeDef; +}FMC_PCCARD_InitTypeDef; /** * @brief FMC_SDRAM Configuration Structure definition @@ -260,37 +255,36 @@ typedef struct typedef struct { uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. - This parameter can be a value of @ref FMC_SDRAM_Bank */ - + This parameter can be a value of @ref FMC_SDRAM_Bank */ + uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ - + uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ - + uint32_t MemoryDataWidth; /*!< Defines the memory device width. This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ - + uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ - + uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ - + uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ - + uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow to disable the clock before changing frequency. This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ - + uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands during the CAS latency and stores data in the Read FIFO. This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ - + uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ - }FMC_SDRAM_InitTypeDef; /** @@ -301,32 +295,31 @@ typedef struct uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and an active or Refresh command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - + uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to issuing the Activate command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - + uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - + uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command and the delay between two consecutive Refresh commands in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - + uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - + uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - + uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - -}FMC_SDRAM_TimingTypeDef; +}FMC_SDRAM_TimingTypeDef; /** * @brief SDRAM command parameters structure definition @@ -334,25 +327,23 @@ typedef struct typedef struct { uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. - This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ - + This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ + uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. - This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ - + This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ + uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued in auto refresh mode. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ - + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ }FMC_SDRAM_CommandTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup FMC_NOR_SRAM_Controller * @{ - */ - + */ + /** @defgroup FMC_NORSRAM_Bank * @{ */ @@ -474,7 +465,7 @@ typedef struct #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \ - ((OPERATION) == FMC_WRITE_OPERATION_ENABLE)) + ((OPERATION) == FMC_WRITE_OPERATION_ENABLE)) /** * @} */ @@ -630,7 +621,7 @@ typedef struct #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) + ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) /** * @} */ @@ -1131,16 +1122,16 @@ typedef struct * @retval None */ #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN)) + ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN)) /** * @brief Disable the NAND device access. * @param __INSTANCE__: FMC_NAND Instance * @param __BANK__: FMC_NAND Bank * @retval None - */ + */ #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN)) + ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN)) /** * @} */ diff --git a/stmhal/hal/inc/stm32f4xx_ll_fsmc.h b/stmhal/hal/inc/stm32f4xx_ll_fsmc.h index 0bcde8d6b..7f1c9ca40 100644 --- a/stmhal/hal/inc/stm32f4xx_ll_fsmc.h +++ b/stmhal/hal/inc/stm32f4xx_ll_fsmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fsmc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of FSMC HAL module. ****************************************************************************** * @attention @@ -62,69 +62,68 @@ #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef -#define FSMC_NORSRAM_DEVICE FSMC_Bank1 -#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E -#define FSMC_NAND_DEVICE FSMC_Bank2_3 -#define FSMC_PCCARD_DEVICE FSMC_Bank4 +#define FSMC_NORSRAM_DEVICE FSMC_Bank1 +#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E +#define FSMC_NAND_DEVICE FSMC_Bank2_3 +#define FSMC_PCCARD_DEVICE FSMC_Bank4 /** - * @brief FSMC_NORSRAM Configuration Structure definition + * @brief FSMC_NORSRAM Configuration Structure definition */ typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - + uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. This parameter can be a value of @ref FSMC_Memory_Type */ - + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ - + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - + uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FSMC_Wrap_Mode */ - + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of @ref FSMC_Wait_Timing */ - + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. This parameter can be a value of @ref FSMC_Write_Operation */ - + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal */ - + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. This parameter can be a value of @ref FSMC_Extended_Mode */ - + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of @ref FSMC_AsynchronousWait */ - + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ + This parameter can be a value of @ref FSMC_Write_Burst */ }FSMC_NORSRAM_InitTypeDef; - /** - * @brief FSMC_NORSRAM Timing parameters structure definition + * @brief FSMC_NORSRAM Timing parameters structure definition */ typedef struct { @@ -132,28 +131,28 @@ typedef struct the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. @note This parameter is not used with synchronous NOR Flash memories. */ - + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between Min_Data = 1 and Max_Data = 15. @note This parameter is not used with synchronous NOR Flash memories. */ - + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. @note This parameter is only used for multiplexed NOR Flash memories. */ - + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: @@ -161,40 +160,40 @@ typedef struct - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories with synchronous burst mode enable */ - + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FSMC_Access_Mode */ - + }FSMC_NORSRAM_TimingTypeDef; /** - * @brief FSMC_NAND Configuration Structure definition + * @brief FSMC_NAND Configuration Structure definition */ typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - + This parameter can be a value of @ref FSMC_NAND_Bank */ + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. This parameter can be any value of @ref FSMC_Wait_feature */ - + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be any value of @ref FSMC_NAND_Data_Width */ - + uint32_t EccComputation; /*!< Enables or disables the ECC computation. This parameter can be any value of @ref FSMC_ECC */ - + uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. This parameter can be any value of @ref FSMC_ECC_Page_Size */ - + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - + }FSMC_NAND_InitTypeDef; /** @@ -207,45 +206,45 @@ typedef struct to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - + uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - + uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - + uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - + }FSMC_NAND_PCC_TimingTypeDef; /** - * @brief FSMC_NAND Configuration Structure definition - */ + * @brief FSMC_NAND Configuration Structure definition + */ typedef struct { uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. This parameter can be any value of @ref FSMC_Wait_feature */ - + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - -}FSMC_PCCARD_InitTypeDef; + +}FSMC_PCCARD_InitTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -379,7 +378,7 @@ typedef struct #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \ - ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE)) + ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE)) /** * @} */ @@ -542,7 +541,7 @@ typedef struct #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) + ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) /** * @} */ @@ -1016,6 +1015,10 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); #define FMC_NAND_BANK2 FSMC_NAND_BANK2 +#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 +#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 +#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 + #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE #define FMC_IT_LEVEL FSMC_IT_LEVEL #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE diff --git a/stmhal/hal/inc/stm32f4xx_ll_sdmmc.h b/stmhal/hal/inc/stm32f4xx_ll_sdmmc.h index 54aab31da..5d562ef53 100644 --- a/stmhal/hal/inc/stm32f4xx_ll_sdmmc.h +++ b/stmhal/hal/inc/stm32f4xx_ll_sdmmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention @@ -56,6 +56,10 @@ /* Exported types ------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Types SDIO Exported Types + * @{ + */ + /** * @brief SDMMC Configuration Structure definition */ @@ -134,6 +138,10 @@ typedef struct This parameter can be a value of @ref SDIO_DPSM_State */ }SDIO_DataInitTypeDef; +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup SDIO_Exported_Constants @@ -144,7 +152,7 @@ typedef struct * @{ */ #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) -#define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000) +#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) @@ -156,7 +164,7 @@ typedef struct * @{ */ #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) -#define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400) +#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) @@ -168,7 +176,7 @@ typedef struct * @{ */ #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) -#define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200) +#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) @@ -180,8 +188,8 @@ typedef struct * @{ */ #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) -#define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800) -#define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000) +#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 +#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ ((WIDE) == SDIO_BUS_WIDE_4B) || \ @@ -194,7 +202,7 @@ typedef struct * @{ */ #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) -#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000) +#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) @@ -209,10 +217,6 @@ typedef struct /** * @} */ - -/** - * @} - */ /** @defgroup SDIO_Command_Index * @{ @@ -226,8 +230,8 @@ typedef struct * @{ */ #define SDIO_RESPONSE_NO ((uint32_t)0x00000000) -#define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040) -#define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0) +#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 +#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ @@ -240,8 +244,8 @@ typedef struct * @{ */ #define SDIO_WAIT_NO ((uint32_t)0x00000000) -#define SDIO_WAIT_IT ((uint32_t)0x00000100) -#define SDIO_WAIT_PEND ((uint32_t)0x00000200) +#define SDIO_WAIT_IT SDIO_CMD_WAITINT +#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ ((WAIT) == SDIO_WAIT_IT) || \ @@ -254,7 +258,7 @@ typedef struct * @{ */ #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) -#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400) +#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ ((CPSM) == SDIO_CPSM_ENABLE)) @@ -290,14 +294,14 @@ typedef struct * @{ */ #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) -#define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010) -#define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020) +#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 +#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030) -#define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040) +#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050) #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060) #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070) -#define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080) +#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090) #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0) #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0) @@ -328,7 +332,7 @@ typedef struct * @{ */ #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) -#define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002) +#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) @@ -340,7 +344,7 @@ typedef struct * @{ */ #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) -#define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004) +#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ ((MODE) == SDIO_TRANSFER_MODE_STREAM)) @@ -352,7 +356,7 @@ typedef struct * @{ */ #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) -#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001) +#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ ((DPSM) == SDIO_DPSM_ENABLE)) @@ -375,30 +379,30 @@ typedef struct /** @defgroup SDIO_Interrupt_sources * @{ */ -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL +#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL +#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT +#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT +#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR +#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR +#define SDIO_IT_CMDREND SDIO_STA_CMDREND +#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT +#define SDIO_IT_DATAEND SDIO_STA_DATAEND +#define SDIO_IT_STBITERR SDIO_STA_STBITERR +#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND +#define SDIO_IT_CMDACT SDIO_STA_CMDACT +#define SDIO_IT_TXACT SDIO_STA_TXACT +#define SDIO_IT_RXACT SDIO_STA_RXACT +#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE +#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF +#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF +#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF +#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE +#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE +#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL +#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL +#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT +#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) /** @@ -408,30 +412,30 @@ typedef struct /** @defgroup SDIO_Flags * @{ */ -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL +#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL +#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT +#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT +#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR +#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR +#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND +#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT +#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND +#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR +#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND +#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT +#define SDIO_FLAG_TXACT SDIO_STA_TXACT +#define SDIO_FLAG_RXACT SDIO_STA_RXACT +#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE +#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF +#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF +#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF +#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE +#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE +#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL +#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL +#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT +#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ @@ -553,27 +557,26 @@ typedef struct /* ---------------------- SDIO registers bit mask --------------------------- */ /* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ + SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ + SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) /* --- PWRCTRL Register ---*/ -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - /* --- DCTRL Register ---*/ /* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) +#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ + SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) /* --- CMD Register ---*/ /* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) +#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ + SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ + SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) /* SDIO RESP Registers Address */ #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) -/* SD FLASH SDIO Interface */ -#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80) - /* SDIO Intialization Frequency (400KHz max) */ #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) @@ -716,7 +719,7 @@ typedef struct /** - * @brief Clears the SDIO's pending flags. + * @brief Clears the SDIO pending flags. * @param __INSTANCE__ : Pointer to SDIO register base * @param __FLAG__: specifies the flag to clear. * This parameter can be one or a combination of the following values: @@ -895,17 +898,39 @@ typedef struct * @} */ +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ - +/** @addtogroup SDIO_Exported_Functions + * @{ + */ + /* Initialization/de-initialization functions **********************************/ +/** @addtogroup HAL_SDIO_Group1 + * @{ + */ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); - +/** + * @} + */ + /* I/O operation functions *****************************************************/ +/** @addtogroup HAL_SDIO_Group2 + * @{ + */ /* Blocking mode: Polling */ uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); - +/** + * @} + */ + /* Peripheral Control functions ************************************************/ +/** @addtogroup HAL_SDIO_Group3 + * @{ + */ HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); @@ -923,18 +948,26 @@ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); /* SDIO IO Cards mode management functions */ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif #endif /* __STM32F4xx_LL_SDMMC_H */ -/** - * @} - */ - -/** - * @} - */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stmhal/hal/inc/stm32f4xx_ll_usb.h b/stmhal/hal/inc/stm32f4xx_ll_usb.h index f286feb9a..489dc2975 100644 --- a/stmhal/hal/inc/stm32f4xx_ll_usb.h +++ b/stmhal/hal/inc/stm32f4xx_ll_usb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention diff --git a/stmhal/hal/src/stm32f4xx_hal.c b/stmhal/hal/src/stm32f4xx_hal.c index 672422553..6c076c358 100644 --- a/stmhal/hal/src/stm32f4xx_hal.c +++ b/stmhal/hal/src/stm32f4xx_hal.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f4xx_hal.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HAL module driver. * This is the common part of the HAL initialization - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -15,7 +15,7 @@ The common HAL driver contains a set of generic and common APIs that can be used by the PPP peripheral drivers and the user to start using the HAL. [..] - The HAL contains two APIs categories: + The HAL contains two APIs' categories: (+) Common HAL APIs (+) Services HAL APIs @@ -65,10 +65,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32F4xx HAL Driver version number V1.0.0 + * @brief STM32F4xx HAL Driver version number V1.1.0 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F4xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24)\ @@ -90,7 +90,7 @@ /* Alias word address of CMP_PD bit */ #define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) #define CMP_PD_BitNumber ((uint8_t)0x00) -#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) +#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ static __IO uint32_t uwTick; @@ -114,7 +114,23 @@ static __IO uint32_t uwTick; configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. (+) de-Initializes common part of the HAL - + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. @endverbatim * @{ */ @@ -123,18 +139,17 @@ static __IO uint32_t uwTick; * @brief This function is used to initialize the HAL Library; it must be the first * instruction to be executed in the main program (before to call any other * HAL function), it performs the following: - * - Configure the Flash prefetch, instruction and Data caches - * - Configures the SysTick to generate an interrupt each 1 millisecond, - * which is clocked by the HSI (at this stage, the clock is not yet - * configured and thus the system is running from the internal HSI at 16 MHz) - * - Set NVIC Group Priority to 4 - * - Calls the HAL_MspInit() callback function defined in user file - * stm32f4xx_hal_msp.c to do the global low level hardware initialization + * Configure the Flash prefetch, instruction and Data caches. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization * * @note SysTick is used as time base for the HAL_Delay() function, the application * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. - * @note * @param None * @retval HAL status */ @@ -153,11 +168,11 @@ HAL_StatusTypeDef HAL_Init(void) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ - /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ - HAL_SYSTICK_Config(HSI_VALUE/ 1000); - /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); /* Init the low level hardware */ HAL_MspInit(); @@ -206,7 +221,7 @@ __weak void HAL_MspInit(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file - */ + */ } /** @@ -221,6 +236,34 @@ __weak void HAL_MspDeInit(void) */ } +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The the SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /*Configure the SysTick to have interrupt in 1ms time basis*/ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /*Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + + /* Return function status */ + return HAL_OK; +} + /** * @} */ @@ -228,69 +271,107 @@ __weak void HAL_MspDeInit(void) /** @defgroup HAL_Group2 HAL Control functions * @brief HAL Control functions * -@verbatim +@verbatim =============================================================================== ##### HAL Control functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) provide a tick value in millisecond - (+) provide a blocking delay in millisecond + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt (+) Get the HAL API driver version (+) Get the device identifier (+) Get the device revision identifier - (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during SLEEP mode (+) Enable/Disable Debug module during STOP mode (+) Enable/Disable Debug module during STANDBY mode - @endverbatim * @{ */ /** - * @brief This function is called from SysTick ISR each 1 millisecond, to increment - * a global variable "uwTick" used as time base. - * @param None + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param None * @retval None */ -void HAL_IncTick(void) +__weak void HAL_IncTick(void) { uwTick++; } /** - * @brief Povides a tick value in millisecond. - * @param Non + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param None * @retval tick value */ -uint32_t HAL_GetTick(void) +__weak uint32_t HAL_GetTick(void) { - return uwTick; + return uwTick; } /** - * @brief Provides a blocking delay in millisecond. - * @note Care must be taken when using HAL_Delay(), this function provides accurate delay - * (in milliseconds) based on variable incremented in SysTick ISR. This implies that - * if HAL_Delay() is called from a peripheral ISR process, then the SysTick interrupt - * must have higher priority (numerically lower) than the peripheral interrupt. - * Otherwise the caller ISR process will be blocked. To change the SysTick interrupt - * priority you have to use HAL_NVIC_SetPriority() function. - * @param Delay : specifies the delay time length, in milliseconds. + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay: specifies the delay time length, in milliseconds. * @retval None */ -void HAL_Delay(__IO uint32_t Delay) +__weak void HAL_Delay(__IO uint32_t Delay) { - uint32_t start = HAL_GetTick(); - - // Note that the following works (due to the magic of 2's complement numbers) - // even when Delay causes wraparound. - - while (HAL_GetTick() - start <= Delay) { - __WFI(); // enter sleep mode, waiting for interrupt + uint32_t tickstart = 0; + tickstart = HAL_GetTick(); + while((HAL_GetTick() - tickstart) < Delay) + { } } +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param None + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param None + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + /** * @brief Returns the HAL revision * @param None @@ -322,7 +403,7 @@ uint32_t HAL_GetDEVID(void) } /** - * @brief Enable the Debug Module during SLEEP mode + * @brief Enable the Debug Module during SLEEP mode * @param None * @retval None */ @@ -332,7 +413,7 @@ void HAL_EnableDBGSleepMode(void) } /** - * @brief Disable the Debug Module during SLEEP mode + * @brief Disable the Debug Module during SLEEP mode * @param None * @retval None */ @@ -342,7 +423,7 @@ void HAL_DisableDBGSleepMode(void) } /** - * @brief Enable the Debug Module during STOP mode + * @brief Enable the Debug Module during STOP mode * @param None * @retval None */ @@ -352,7 +433,7 @@ void HAL_EnableDBGStopMode(void) } /** - * @brief Disable the Debug Module during STOP mode + * @brief Disable the Debug Module during STOP mode * @param None * @retval None */ @@ -362,7 +443,7 @@ void HAL_DisableDBGStopMode(void) } /** - * @brief Enable the Debug Module during STANDBY mode + * @brief Enable the Debug Module during STANDBY mode * @param None * @retval None */ @@ -372,7 +453,7 @@ void HAL_EnableDBGStandbyMode(void) } /** - * @brief Disable the Debug Module during STANDBY mode + * @brief Disable the Debug Module during STANDBY mode * @param None * @retval None */ diff --git a/stmhal/hal/src/stm32f4xx_hal_adc.c b/stmhal/hal/src/stm32f4xx_hal_adc.c index 4f95cb33e..fa9668ce4 100644 --- a/stmhal/hal/src/stm32f4xx_hal_adc.c +++ b/stmhal/hal/src/stm32f4xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -63,7 +63,7 @@ (#) Configure the ADC regular channels group features, use HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. - (#) Three mode of operations are available within this driver : + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -89,7 +89,7 @@ ============================== [..] (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length - of data to be transfered at each end of conversion + of data to be transferred at each end of conversion (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can add his own code by customization of function pointer HAL_ADC_ConvCpltCallback (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can @@ -410,7 +410,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) * * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * last transfer and End of conversion selection). + * * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) @@ -434,10 +434,10 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t timeout; + uint32_t tickstart = 0; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check End of conversion flag */ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) @@ -445,7 +445,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hadc->State= HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ @@ -484,13 +484,13 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { + uint32_t tickstart = 0; + /* Check the parameters */ assert_param(IS_ADC_EVENT_TYPE(EventType)); - - uint32_t timeout; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check selected event flag */ while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) @@ -498,7 +498,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hadc->State= HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ @@ -780,7 +780,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { @@ -846,7 +846,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { @@ -1221,7 +1221,8 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) @@ -1245,7 +1246,8 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -1257,7 +1259,8 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) diff --git a/stmhal/hal/src/stm32f4xx_hal_adc_ex.c b/stmhal/hal/src/stm32f4xx_hal_adc_ex.c index 1520952af..2224dcb36 100644 --- a/stmhal/hal/src/stm32f4xx_hal_adc_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions @@ -24,22 +24,21 @@ (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) - (++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() - (++) Configure and enable two DMA streams stream for managing data + (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams stream for managing data transfer from peripheral to memory (output stream) - (++) Associate the initilalized DMA handle to the CRYP DMA handle + (+++) Associate the initilalized DMA handle to the ADC DMA handle using __HAL_LINKDMA() - (++) Configure the priority and enable the NVIC for the transfer complete + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream. - + priority than the input stream. (#) Configure the ADC Prescaler, conversion resolution and data alignment using the HAL_ADC_Init() function. (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. - (#) Three mode of operations are available within this driver : + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -66,7 +65,7 @@ ============================== [..] (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length - of data to be transfered at each end of conversion + of data to be transferred at each end of conversion (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can @@ -79,7 +78,7 @@ (+) Select the Multi mode ADC regular channels features (dual or triple mode) and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length - of data to be transfered at each end of conversion + of data to be transferred at each end of conversion (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. @@ -339,10 +338,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t timeout; - - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); /* Check End of conversion flag */ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) @@ -350,7 +349,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hadc->State= HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ @@ -409,10 +408,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @param InjectedRank: the ADC injected rank. * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected + * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected + * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected + * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval None */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) @@ -463,7 +462,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa * the configuration information for the specified ADC. * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. * @param Length: The length of data to be transferred from ADC peripheral to memory. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { @@ -538,7 +537,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) { @@ -774,7 +773,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) @@ -798,7 +798,8 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -810,7 +811,8 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) diff --git a/stmhal/hal/src/stm32f4xx_hal_can.c b/stmhal/hal/src/stm32f4xx_hal_can.c index 75598a243..7e018ee28 100644 --- a/stmhal/hal/src/stm32f4xx_hal_can.c +++ b/stmhal/hal/src/stm32f4xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_can.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: * + Initialization and de-initialization functions @@ -117,6 +117,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define CAN_TIMEOUT_VALUE 10 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -153,7 +154,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { uint32_t InitStatus = 3; - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check CAN handle */ if(hcan == NULL) @@ -191,13 +192,13 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) /* Request initialisation */ hcan->Instance->MCR |= CAN_MCR_INRQ ; - /* Get timeout */ - timeout = HAL_GetTick() + 10; - + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -283,13 +284,13 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) /* Request leave initialisation */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - /* Get timeout */ - timeout = HAL_GetTick() + 10; - + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -524,9 +525,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { uint32_t transmitmailbox = 5; - - uint32_t timeout; - + uint32_t tickstart = 0; + /* Check the parameters */ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); @@ -599,8 +599,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check End of transmission flag */ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) @@ -608,12 +608,12 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; } } } @@ -771,14 +771,13 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) * @brief Receives a correct CAN frame. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param FIFONumber: FIFO Number value - * @param Timeout: Specify Timeout value + * @param FIFONumber: FIFO Number value + * @param Timeout: Specify Timeout value * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) { - uint32_t timeout; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); @@ -797,8 +796,8 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u hcan->State = HAL_CAN_STATE_BUSY_RX; } - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check pending message */ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) @@ -806,7 +805,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -881,7 +880,6 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u * the configuration information for the specified CAN. * @param FIFONumber: Specify the FIFO number * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { @@ -957,7 +955,7 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber */ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) { - uint32_t timeout; + uint32_t tickstart = 0; /* Process locked */ __HAL_LOCK(hcan); @@ -975,13 +973,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) return HAL_ERROR; } - /* Get timeout */ - timeout = HAL_GetTick() + 10; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait the acknowledge */ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { hcan->State = HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -1009,7 +1007,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) */ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) { - uint32_t timeout; + uint32_t tickstart = 0; /* Process locked */ __HAL_LOCK(hcan); @@ -1019,14 +1017,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) /* Wake up request */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Get timeout */ - timeout = HAL_GetTick() + 10; - + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Sleep mode status */ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -1229,7 +1227,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) ##### Peripheral State and Error functions ##### ============================================================================== [..] - This subsection provides functions allowing to + This subsection provides functions allowing to : (+) Check the CAN state. (+) Check CAN Errors detected during interrupt process diff --git a/stmhal/hal/src/stm32f4xx_hal_cortex.c b/stmhal/hal/src/stm32f4xx_hal_cortex.c index b326a974b..facc59498 100644 --- a/stmhal/hal/src/stm32f4xx_hal_cortex.c +++ b/stmhal/hal/src/stm32f4xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -16,40 +16,18 @@ ============================================================================== [..] - *** How to configure Interrupts using Cortex HAL driver *** + *** How to configure Interrupts using CORTEX HAL driver *** =========================================================== [..] - This section provide functions allowing to configure the NVIC interrupts (IRQ). + This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions. (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function according to the following table. - - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. - ========================================================================================================================== - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ========================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ========================================================================================================================== - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() - - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programing manual for details in how to configure priority. - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the sub priority. @@ -59,12 +37,12 @@ (+@) Lowest hardware priority (IRQ number) [..] - *** How to configure Systick using Cortex HAL driver *** + *** How to configure Systick using CORTEX HAL driver *** ======================================================== [..] - Setup SysTick Timer for 1 msec interrupts. + Setup SysTick Timer for time base. - (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. (++) Configures the SysTick IRQ priority to the lowest value (0x0F). @@ -153,7 +131,7 @@ ##### Initialization and de-initialization functions ##### ============================================================================== [..] - This section provide the Cortex HAL driver functions allowing to configure Interrupts + This section provides the CORTEX HAL driver functions allowing to configure Interrupts Systick functionalities @endverbatim @@ -191,8 +169,8 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number - * This parameter can be an enumerator of @ref IRQn_Type enumeration + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) * @param PreemptPriority: The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 15 @@ -219,8 +197,8 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. - * @param IRQn External interrupt number - * This parameter can be an enumerator of @ref IRQn_Type enumeration + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) * @retval None */ @@ -232,8 +210,8 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) /** * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number - * This parameter can be an enumerator of @ref IRQn_Type enumeration + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) * @retval None */ @@ -298,8 +276,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number - * This parameter can be an enumerator of @ref IRQn_Type enumeration + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) * @param PriorityGroup: the priority grouping bits length. * This parameter can be one of the following values: @@ -341,8 +319,8 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) /** * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number - * This parameter can be an enumerator of @ref IRQn_Type enumeration + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. @@ -355,8 +333,8 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) /** * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of @ref IRQn_Type enumeration + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) * @retval None */ @@ -369,7 +347,7 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) /** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). * @param IRQn External interrupt number - * This parameter can be an enumerator of @ref IRQn_Type enumeration + * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. diff --git a/stmhal/hal/src/stm32f4xx_hal_crc.c b/stmhal/hal/src/stm32f4xx_hal_crc.c index 306ccc390..26b312ab7 100644 --- a/stmhal/hal/src/stm32f4xx_hal_crc.c +++ b/stmhal/hal/src/stm32f4xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -105,7 +105,8 @@ /** * @brief Initializes the CRC according to the specified * parameters in the CRC_InitTypeDef and creates the associated handle. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) @@ -137,7 +138,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) /** * @brief DeInitializes the CRC peripheral. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) @@ -169,7 +171,8 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /** * @brief Initializes the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval None */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) @@ -181,7 +184,8 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) /** * @brief DeInitializes the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval None */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) @@ -215,7 +219,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) /** * @brief Computes the 32-bit CRC of 32-bit data buffer using combination * of the previous CRC value and the new one. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @param pBuffer: pointer to the buffer containing the data to be computed * @param BufferLength: length of the buffer to be computed * @retval 32-bit CRC @@ -249,7 +254,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ /** * @brief Computes the 32-bit CRC of 32-bit data buffer independently * of the previous CRC value. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @param pBuffer: Pointer to the buffer containing the data to be computed * @param BufferLength: Length of the buffer to be computed * @retval 32-bit CRC @@ -304,7 +310,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** * @brief Returns the CRC state. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval HAL state */ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) diff --git a/stmhal/hal/src/stm32f4xx_hal_cryp.c b/stmhal/hal/src/stm32f4xx_hal_cryp.c index 2ecfb17d7..9e2489f59 100644 --- a/stmhal/hal/src/stm32f4xx_hal_cryp.c +++ b/stmhal/hal/src/stm32f4xx_hal_cryp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -29,18 +29,15 @@ (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA()) - (++) Enable the DMAx interface clock using - (+++) __DMAx_CLK_ENABLE() - (++) Configure and enable two DMA streams one for managing data transfer from + (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams one for managing data transfer from memory to peripheral (input stream) and another stream for managing data transfer from peripheral to memory (output stream) - (++) Associate the initilalized DMA handle to the CRYP DMA handle + (+++) Associate the initilalized DMA handle to the CRYP DMA handle using __HAL_LINKDMA() - (++) Configure the priority and enable the NVIC for the transfer complete + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream. - (+++) HAL_NVIC_SetPriority() - (+++) HAL_NVIC_EnableIRQ() + priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly: (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit @@ -51,13 +48,13 @@ (#)Three processing (encryption/decryption) functions are available: (##) Polling mode: encryption and decryption APIs are blocking functions - i.e. they process the data and wait till the processing is finished + i.e. they process the data and wait till the processing is finished, e.g. HAL_CRYP_AESCBC_Encrypt() (##) Interrupt mode: encryption and decryption APIs are not blocking functions - i.e. they process the data under interrupt + i.e. they process the data under interrupt, e.g. HAL_CRYP_AESCBC_Encrypt_IT() (##) DMA mode: encryption and decryption APIs are not blocking functions - i.e. the data transfer is ensured by DMA + i.e. the data transfer is ensured by DMA, e.g. HAL_CRYP_AESCBC_Encrypt_DMA() (#)When the processing function is called at first time after HAL_CRYP_Init() @@ -118,6 +115,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define CRYP_TIMEOUT_VALUE 1 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -161,7 +159,8 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction); /** * @brief Initializes the CRYP according to the specified * parameters in the CRYP_InitTypeDef and creates the associated handle. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) @@ -204,7 +203,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitializes the CRYP peripheral. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) @@ -243,7 +243,8 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Initializes the CRYP MSP. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval None */ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) @@ -255,7 +256,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitializes CRYP MSP. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval None */ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) @@ -291,7 +293,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer @@ -344,7 +347,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer @@ -400,7 +404,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer @@ -458,7 +463,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer @@ -467,7 +473,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hcryp); @@ -487,15 +493,15 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /* Enable CRYP */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; @@ -545,7 +551,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer @@ -554,7 +561,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hcryp); @@ -574,20 +581,20 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /* Enable CRYP */ __HAL_CRYP_ENABLE(); - /* Get Timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -633,7 +640,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer @@ -688,7 +696,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes * @param pCypherData: Pointer to the cyphertext buffer @@ -788,7 +797,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes * @param pCypherData: Pointer to the cyphertext buffer @@ -890,7 +900,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes * @param pCypherData: Pointer to the cyphertext buffer @@ -993,7 +1004,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer @@ -1001,7 +1013,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -1030,13 +1042,13 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Enable CRYP */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY)) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; @@ -1121,7 +1133,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -1130,7 +1143,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -1160,18 +1173,18 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Enable CRYP */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY)) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1257,7 +1270,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -1361,7 +1375,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes * @param pCypherData: Pointer to the cyphertext buffer @@ -1415,7 +1430,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer @@ -1472,7 +1488,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer @@ -1530,7 +1547,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes * @param pPlainData: Pointer to the plaintext buffer @@ -1538,7 +1556,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -1565,18 +1583,18 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /* Enable CRYP */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY)) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1613,7 +1631,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes * @param pPlainData: Pointer to the plaintext buffer @@ -1621,7 +1640,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -1648,18 +1667,18 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /* Enable CRYP */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY)) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1699,7 +1718,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -1768,10 +1788,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t ============================================================================== [..] This section provides functions allowing to: (+) Encrypt plaintext using DES using ECB or CBC chaining modes - (+) Decrypt cyphertext using using ECB or CBC chaining modes + (+) Decrypt cyphertext using ECB or CBC chaining modes [..] Three processing functions are available: - (+) polling mode - (+) interrupt mode + (+) Polling mode + (+) Interrupt mode (+) DMA mode @endverbatim @@ -1780,7 +1800,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -1819,7 +1840,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -1858,7 +1880,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -1897,7 +1920,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -1936,7 +1960,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2020,7 +2045,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2105,7 +2131,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2189,7 +2216,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2273,7 +2301,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2315,7 +2344,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2357,7 +2387,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2399,7 +2430,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2451,11 +2483,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t ##### TDES processing functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Encrypt plaintext using TDES using ECB or CBC chaining modes - (+) Decrypt cyphertext using TDES using ECB or CBC chaining modes + (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes + (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes [..] Three processing functions are available: - (+) polling mode - (+) interrupt mode + (+) Polling mode + (+) Interrupt mode (+) DMA mode @endverbatim @@ -2465,7 +2497,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2505,7 +2538,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2545,7 +2579,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2585,7 +2620,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pPlainData: Pointer to the plaintext buffer @@ -2624,7 +2660,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2708,7 +2745,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2791,7 +2829,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2874,7 +2913,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pPlainData: Pointer to the plaintext buffer @@ -2957,7 +2997,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -2999,7 +3040,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -3041,7 +3083,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pCypherData: Pointer to the cyphertext buffer @@ -3083,7 +3126,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 8 * @param pPlainData: Pointer to the plaintext buffer @@ -3145,7 +3189,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Input FIFO transfer completed callbacks. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval None */ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) @@ -3157,7 +3202,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Output FIFO transfer completed callbacks. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval None */ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) @@ -3169,7 +3215,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief CRYP error callbacks. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval None */ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) @@ -3198,7 +3245,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief This function handles CRYP interrupt request. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval None */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) @@ -3286,7 +3334,8 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @brief Returns the CRYP state. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval HAL state */ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) @@ -3352,7 +3401,8 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Writes the Key in Key registers. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Key: Pointer to Key buffer * @param KeySize: Size of Key * @retval None @@ -3410,7 +3460,8 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySiz /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param InitVector: Pointer to InitVector/InitCounter buffer * @param IVSize: Size of the InitVector/InitCounter * @retval None @@ -3448,7 +3499,8 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, u /** * @brief Process Data: Writes Input data in polling mode and read the output data - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Input: Pointer to the Input buffer * @param Ilength: Length of the Input buffer, must be a multiple of 16. * @param Output: Pointer to the returned buffer @@ -3456,7 +3508,7 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, u */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t i = 0; uint32_t inputaddr = (uint32_t)Input; @@ -3474,20 +3526,20 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In CRYP->DR = *(uint32_t*)(inputaddr); inputaddr+=4; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -3510,7 +3562,8 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In /** * @brief Process Data: Write Input data in polling mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Input: Pointer to the Input buffer * @param Ilength: Length of the Input buffer, must be a multiple of 8 * @param Output: Pointer to the returned buffer @@ -3519,7 +3572,7 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In */ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t i = 0; uint32_t inputaddr = (uint32_t)Input; @@ -3533,15 +3586,15 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8 CRYP->DR = *(uint32_t*)(inputaddr); inputaddr+=4; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; @@ -3565,7 +3618,8 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Set the DMA configuration and start the DMA transfer - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param inputaddr: address of the Input buffer * @param Size: Size of the Input buffer, must be a multiple of 16. * @param outputaddr: address of the Output buffer @@ -3602,7 +3656,8 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin /** * @brief Sets the CRYP peripheral in DES ECB mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Direction: Encryption or decryption * @retval None */ @@ -3628,7 +3683,8 @@ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in DES CBC mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Direction: Encryption or decryption * @retval None */ @@ -3657,7 +3713,8 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in TDES ECB mode. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Direction: Encryption or decryption * @retval None */ @@ -3682,7 +3739,8 @@ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in TDES CBC mode - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Direction: Encryption or decryption * @retval None */ diff --git a/stmhal/hal/src/stm32f4xx_hal_cryp_ex.c b/stmhal/hal/src/stm32f4xx_hal_cryp_ex.c index 33ce7cbeb..23d8ea7e3 100644 --- a/stmhal/hal/src/stm32f4xx_hal_cryp_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_cryp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -111,6 +111,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define CRYPEx_TIMEOUT_VALUE 1 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -153,7 +154,8 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -162,7 +164,7 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t headersize = hcryp->Init.HeaderSize; uint32_t headeraddr = (uint32_t)hcryp->Init.Header; uint32_t loopcounter = 0; @@ -283,20 +285,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -314,20 +316,21 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) { - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); + while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM)) { { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -346,20 +349,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * headeraddr+=4; } - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -407,7 +410,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -416,7 +420,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hcryp); @@ -442,20 +446,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -504,7 +508,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the cyphertext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -513,7 +518,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hcryp); @@ -539,20 +544,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(); - /* Get the timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -596,7 +601,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Computes the authentication TAG. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Size: Total length of the plain/cyphertext buffer * @param AuthTag: Pointer to the authentication buffer * @param Timeout: Timeout duration @@ -604,7 +610,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t Size, uint8_t *AuthTag, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ uint32_t inputlength = Size * 8; /* input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; @@ -660,20 +666,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t S CRYP->DR = 0; CRYP->DR = (uint32_t)(inputlength); } - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -704,14 +710,15 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t S /** * @brief Computes the authentication TAG for AES CCM mode. * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param AuthTag: Pointer to the authentication buffer * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t tagaddr = (uint32_t)AuthTag; uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch; uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */ @@ -747,20 +754,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A ctraddr+=4; CRYP->DR = *(uint32_t*)ctraddr; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -795,7 +802,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -804,7 +812,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t headersize = hcryp->Init.HeaderSize; uint32_t headeraddr = (uint32_t)hcryp->Init.Header; uint32_t loopcounter = 0; @@ -925,20 +933,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -956,20 +964,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) { - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -987,20 +995,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * headeraddr+=4; } - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1046,7 +1054,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -1054,7 +1063,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -1090,19 +1099,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /* Enable CRYP to start the init phase */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1196,7 +1205,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -1204,7 +1214,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -1335,18 +1345,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1363,18 +1373,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) { - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM)) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1390,19 +1400,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ CRYP->DR = *(uint32_t*)(headeraddr); headeraddr+=4; } - - /* Get timeout */ - timeout = HAL_GetTick() + 1; + + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1494,7 +1504,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the cyphertext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -1502,7 +1513,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -1537,19 +1548,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /* Enable CRYP to start the init phase */ __HAL_CRYP_ENABLE(); - - /* Get timeout */ - timeout = HAL_GetTick() + 1; - + + /* Get tick */ + tickstart = HAL_GetTick(); + while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1641,7 +1652,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -1651,7 +1663,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ { uint32_t inputaddr; uint32_t outputaddr; - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t headersize = hcryp->Init.HeaderSize; uint32_t headeraddr = (uint32_t)hcryp->Init.Header; uint32_t loopcounter = 0; @@ -1778,19 +1790,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(); - - /* Get timeout */ - timeout = HAL_GetTick() + 1; + + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1807,18 +1819,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) { - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM)) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1834,19 +1846,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ CRYP->DR = *(uint32_t*)(headeraddr); headeraddr+=4; } - - /* Get timeout */ - timeout = HAL_GetTick() + 1; + + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -1930,7 +1942,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -1938,7 +1951,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -1971,18 +1984,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /* Enable CRYP to start the init phase */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2026,7 +2039,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -2034,7 +2048,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; uint32_t headersize; @@ -2170,18 +2184,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2198,18 +2212,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) { - /* Get timeout */ - timeout = HAL_GetTick() + 1; - + /* Get tick */ + tickstart = HAL_GetTick(); + while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM)) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2226,18 +2240,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 headeraddr+=4; } - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2279,7 +2293,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer. * @param Size: Length of the cyphertext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -2287,7 +2302,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; @@ -2317,18 +2332,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /* Enable CRYP to start the init phase */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2368,7 +2383,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -2376,7 +2392,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t inputaddr; uint32_t outputaddr; uint32_t headersize; @@ -2512,19 +2528,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2542,18 +2558,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) { - /* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM)) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2570,18 +2586,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 headeraddr+=4; } -/* Get timeout */ - timeout = HAL_GetTick() + 1; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2621,7 +2637,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief This function handles CRYP interrupt request. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval None */ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp) @@ -2707,7 +2724,8 @@ static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Writes the Key in Key registers. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Key: Pointer to Key buffer * @param KeySize: Size of Key * @retval None @@ -2765,7 +2783,8 @@ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32 /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param InitVector: Pointer to InitVector/InitCounter buffer * @param IVSize: Size of the InitVector/InitCounter * @retval None @@ -2803,7 +2822,8 @@ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *Init /** * @brief Process Data: Writes Input data in polling mode and read the Output data. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Input: Pointer to the Input buffer. * @param Ilength: Length of the Input buffer, must be a multiple of 16 * @param Output: Pointer to the returned buffer @@ -2812,7 +2832,7 @@ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *Init */ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t i = 0; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; @@ -2829,20 +2849,20 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui CRYP->DR = *(uint32_t*)(inputaddr); inputaddr+=4; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2865,7 +2885,8 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui /** * @brief Sets the header phase - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Input: Pointer to the Input buffer. * @param Ilength: Length of the Input buffer, must be a multiple of 16 * @param Timeout: Timeout value @@ -2873,7 +2894,7 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui */ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t loopcounter = 0; uint32_t headeraddr = (uint32_t)Input; @@ -2887,20 +2908,20 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16) { - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2920,20 +2941,20 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, /* Wait until the complete message has been processed */ - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; @@ -2947,7 +2968,8 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, /** * @brief Sets the DMA configuration and start the DMA transfert. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param inputaddr: Address of the Input buffer * @param Size: Size of the Input buffer, must be a multiple of 16 * @param outputaddr: Address of the Output buffer diff --git a/stmhal/hal/src/stm32f4xx_hal_dac.c b/stmhal/hal/src/stm32f4xx_hal_dac.c index afd394aa4..ba8c70cec 100644 --- a/stmhal/hal/src/stm32f4xx_hal_dac.c +++ b/stmhal/hal/src/stm32f4xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -116,7 +116,7 @@ ============================== [..] (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length - of data to be transfered at each end of conversion + of data to be transferred at each end of conversion (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 @@ -430,9 +430,9 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) * @param Length: The length of data to be transferred from memory to DAC peripheral * @param Alignment: Specifies the data alignment for DAC channel. * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) @@ -448,27 +448,18 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - - /* Set the DMA transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - - /* Set the DMA half transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - - /* Set the DMA error callback for channel1 */ - hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - - /* Set the DMA transfer complete callback for channel2 */ - hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; - - /* Set the DMA half transfer complete callback for channel2 */ - hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; - - /* Set the DMA error callback for channel2 */ - hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; - + if(Channel == DAC_CHANNEL_1) { + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + /* Enable the selected DAC channel1 DMA request */ hdac->Instance->CR |= DAC_CR_DMAEN1; @@ -493,9 +484,18 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u } else { + /* Set the DMA transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; + + /* Set the DMA half transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; + + /* Set the DMA error callback for channel2 */ + hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; + /* Enable the selected DAC channel2 DMA request */ hdac->Instance->CR |= DAC_CR_DMAEN2; - + /* Case of use of channel 2 */ switch(Alignment) { @@ -556,20 +556,42 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); /* Disable the Peripharal */ __HAL_DAC_DISABLE(hdac, Channel); - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - + /* Disable the DMA Channel */ + /* Channel1 is used */ + if(Channel == DAC_CHANNEL_1) + { + status = HAL_DMA_Abort(hdac->DMA_Handle1); + } + else /* Channel2 is used for */ + { + status = HAL_DMA_Abort(hdac->DMA_Handle2); + } + + /* Check if DMA Channel effectively disabled */ + if(status == HAL_ERROR) + { + /* Update ADC state machine to error */ + hdac->State = HAL_DAC_STATE_ERROR; + } + else + { + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + } + /* Return function status */ - return HAL_OK; + return status; } /** @@ -732,7 +754,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); - assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ @@ -776,9 +797,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf * @arg DAC_CHANNEL_2: DAC Channel2 selected * @param Alignment: Specifies the data alignment. * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data: Data to be loaded in the selected data holding register. * @retval HAL status */ @@ -858,7 +879,8 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) @@ -872,7 +894,8 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) @@ -884,7 +907,8 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) diff --git a/stmhal/hal/src/stm32f4xx_hal_dac_ex.c b/stmhal/hal/src/stm32f4xx_hal_dac_ex.c index ac6b47112..4f4ca92d1 100644 --- a/stmhal/hal/src/stm32f4xx_hal_dac_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -123,8 +123,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * DAC_CHANNEL_1 / DAC_CHANNEL_2 * @param Amplitude: Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 @@ -172,8 +171,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * DAC_CHANNEL_1 / DAC_CHANNEL_2 * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation @@ -221,9 +219,9 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t * the configuration information for the specified DAC. * @param Alignment: Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected + * DAC_ALIGN_8B_R: 8bit right data alignment selected + * DAC_ALIGN_12B_L: 12bit left data alignment selected + * DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both @@ -317,7 +315,8 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) @@ -331,7 +330,8 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) @@ -343,7 +343,8 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) diff --git a/stmhal/hal/src/stm32f4xx_hal_dcmi.c b/stmhal/hal/src/stm32f4xx_hal_dcmi.c index 380ef32ba..6bd982510 100644 --- a/stmhal/hal/src/stm32f4xx_hal_dcmi.c +++ b/stmhal/hal/src/stm32f4xx_hal_dcmi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -39,9 +39,9 @@ window from the received image using HAL_DCMI_ConfigCrop() and HAL_DCMI_EnableCROP() functions - (#) The capture can be stopped using the following HAL_DCMI_Stop() function. + (#) The capture can be stopped using HAL_DCMI_Stop() function. - (#) To control DCMI state you can use the following function : HAL_DCMI_GetState() + (#) To control DCMI state you can use the function HAL_DCMI_GetState(). *** DCMI HAL driver macros list *** ============================================= @@ -217,7 +217,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) * values. * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) @@ -290,7 +290,7 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab. * @param pData: The destination memory Buffer address (LCD Frame buffer). * @param Length: The length of capture to be transferred. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) { @@ -363,10 +363,11 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo * @brief Disable DCMI DMA request and Disable DCMI capture * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) { - uint32_t timeout = 0x00; + uint32_t tickstart = 0; /* Lock the DCMI peripheral state */ hdcmi->State = HAL_DCMI_STATE_BUSY; @@ -376,13 +377,13 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) /* Disable Capture */ DCMI->CR &= ~(DCMI_CR_CAPTURE); - /* Get timeout */ - timeout = HAL_GetTick() + HAL_TIMEOUT_DCMI_STOP; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check if the DCMI capture effectively disabled */ while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP) { /* Process Unlocked */ __HAL_UNLOCK(hdcmi); @@ -417,7 +418,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) * @brief Handles DCMI interrupt request. * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for the DCMI. - * @retval HAL status + * @retval None */ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) { @@ -593,7 +594,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) =============================================================================== [..] This section provides functions allowing to: (+) Configure the CROP feature. - (+) ENABLE/DISABLE the CROP feature. + (+) Enable/Disable the CROP feature. @endverbatim * @{ @@ -640,7 +641,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui * @brief Disable the Crop feature. * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi) { @@ -666,7 +667,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi) * @brief Enable the Crop feature. * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi) { @@ -736,7 +737,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma) @@ -789,7 +791,8 @@ static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) diff --git a/stmhal/hal/src/stm32f4xx_hal_dma.c b/stmhal/hal/src/stm32f4xx_hal_dma.c index 21c1279bd..f1c53b0cc 100644 --- a/stmhal/hal/src/stm32f4xx_hal_dma.c +++ b/stmhal/hal/src/stm32f4xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -47,7 +47,7 @@ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can add his own function by customization of function pointer XferCpltCallback and XferErrorCallback (i.e a member of DMA handle structure). - + [..] (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. @@ -261,6 +261,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { @@ -423,19 +429,19 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { - uint32_t timeout = 0x00; + uint32_t tickstart = 0; /* Disable the stream */ __HAL_DMA_DISABLE(hdma); - /* Get timeout */ - timeout = HAL_GetTick() + HAL_TIMEOUT_DMA_ABORT; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != 0) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; @@ -469,7 +475,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp, tmp, tmp1, tmp2; - uint32_t timeout = 0x00; + uint32_t tickstart = 0; /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) @@ -483,8 +489,8 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); } - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) { @@ -493,13 +499,30 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET)) { - /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - /* Clear the FIFO error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - /* Clear the DIrect Mode error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + if(tmp != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + } + if(tmp1 != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + } + if(tmp2 != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + } /* Change the DMA state */ hdma->State= HAL_DMA_STATE_ERROR; @@ -511,32 +534,29 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_TIMEOUT; } } } - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); @@ -555,6 +575,8 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp } else { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); diff --git a/stmhal/hal/src/stm32f4xx_hal_dma2d.c b/stmhal/hal/src/stm32f4xx_hal_dma2d.c index e15193018..b456c6fb4 100644 --- a/stmhal/hal/src/stm32f4xx_hal_dma2d.c +++ b/stmhal/hal/src/stm32f4xx_hal_dma2d.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma2d.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief DMA2D HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: @@ -46,8 +46,7 @@ -@- In Register-to-Memory transfer mode, the pdata parameter is the register color, in Memory-to-memory or memory-to-memory with pixel format - conversion the pdata is the source address and it is the color value - for the A4 or A8 mode. + conversion the pdata is the source address. -@- Configure the foreground source address, the background source address, the Destination and data length and Enable the transfer using @@ -71,15 +70,15 @@ *** DMA2D HAL driver macros list *** ============================================= [..] - Below the list of most used macros in DMA2D HAL driver. + Below the list of most used macros in DMA2D HAL driver : (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral. (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. - (+) __HAL_DMA2D_CLEAR_FLAG: Clears the DMA2D pending flags. - (+) __HAL_DMA2D_ENABLE_IT: Enables the specified DMA2D interrupts. - (+) __HAL_DMA2D_DISABLE_IT: Disables the specified DMA2D interrupts. - (+) __HAL_DMA2D_GET_IT_SOURCE: Checks whether the specified DMA2D interrupt has occurred or not. + (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. + (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. + (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. + (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not. [..] (@) You can refer to the DMA2D HAL driver header file for more useful macros @@ -320,8 +319,8 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) (+) Abort DMA2D transfer. (+) Suspend DMA2D transfer. (+) Continue DMA2D transfer. - (+) polling for transfer complete. - (+) handles DMA2D interrupt request. + (+) Poll for transfer complete. + (+) handle DMA2D interrupt request. @endverbatim * @{ @@ -334,8 +333,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) * @param pdata: Configure the source memory Buffer address if * the memory to memory or memory to memory with pixel format * conversion DMA2D mode is selected, and configure - * the color value if register to memory DMA2D mode is selected - * or the color value for the A4 or A8 mode. + * the color value if register to memory DMA2D mode is selected. * @param DstAddress: The destination memory Buffer address. * @param Width: The width of data to be transferred from source to destination. * @param Heigh: The heigh of data to be transferred from source to destination. @@ -372,8 +370,7 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u * @param pdata: Configure the source memory Buffer address if * the memory to memory or memory to memory with pixel format * conversion DMA2D mode is selected, and configure - * the color value if register to memory DMA2D mode is selected - * or the color value for the A4 or A8 mode. + * the color value if register to memory DMA2D mode is selected. * @param DstAddress: The destination memory Buffer address. * @param Width: The width of data to be transferred from source to destination. * @param Heigh: The heigh of data to be transferred from source to destination. @@ -417,8 +414,7 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @param SrcAddress1: The source memory Buffer address of the foreground layer. - * @param SrcAddress2: The source memory Buffer address of the background layer - * or the color value for the A4 or A8 mode. + * @param SrcAddress2: The source memory Buffer address of the background layer. * @param DstAddress: The destination memory Buffer address * @param Width: The width of data to be transferred from source to destination. * @param Heigh: The heigh of data to be transferred from source to destination. @@ -439,15 +435,8 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t /* Disable the Peripheral */ __HAL_DMA2D_DISABLE(hdma2d); - if((hdma2d->LayerCfg[0].InputColorMode == CM_A4) || (hdma2d->LayerCfg[0].InputColorMode == CM_A8)) - { - hdma2d->Instance->BGCOLR = SrcAddress2; - } - else - { /* Configure DMA2D Stream source2 address */ hdma2d->Instance->BGMAR = SrcAddress2; - } /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh); @@ -463,8 +452,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @param SrcAddress1: The source memory Buffer address of the foreground layer. - * @param SrcAddress2: The source memory Buffer address of the background layer - * or the color value for the A4 or A8 mode. + * @param SrcAddress2: The source memory Buffer address of the background layer. * @param DstAddress: The destination memory Buffer address. * @param Width: The width of data to be transferred from source to destination. * @param Heigh: The heigh of data to be transferred from source to destination. @@ -484,16 +472,9 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 /* Disable the Peripheral */ __HAL_DMA2D_DISABLE(hdma2d); - - if ((hdma2d->LayerCfg[0].InputColorMode == CM_A4) || (hdma2d->LayerCfg[0].InputColorMode == CM_A8)) - { - hdma2d->Instance->BGCOLR = SrcAddress2; - } - else - { - /* Configure DMA2D Stream source2 address */ - hdma2d->Instance->BGMAR = SrcAddress2; - } + + /* Configure DMA2D Stream source2 address */ + hdma2d->Instance->BGMAR = SrcAddress2; /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh); @@ -521,18 +502,18 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 */ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) { - uint32_t timeout = 0x00; + uint32_t tickstart = 0; /* Disable the DMA2D */ __HAL_DMA2D_DISABLE(hdma2d); - /* Get timeout */ - timeout = HAL_GetTick() + HAL_TIMEOUT_DMA2D_ABORT; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively disabled */ while((hdma2d->Instance->CR & DMA2D_CR_START) != 0) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -563,18 +544,18 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) */ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) { - uint32_t timeout = 0x00; + uint32_t tickstart = 0; /* Suspend the DMA2D transfer */ hdma2d->Instance->CR |= DMA2D_CR_SUSP; - /* Get timeout */ - timeout = HAL_GetTick() + HAL_TIMEOUT_DMA2D_SUSPEND; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively suspended */ while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -618,13 +599,13 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) { uint32_t tmp, tmp1; - uint32_t timeout = 0x00; + uint32_t tickstart = 0; /* Polling for DMA2D transfer */ if((hdma2d->Instance->CR & DMA2D_CR_START) != 0) { - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) { @@ -648,7 +629,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Process unlocked */ __HAL_UNLOCK(hdma2d); @@ -667,8 +648,8 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ /* Polling for CLUT loading */ if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0) { - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) { @@ -685,7 +666,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -827,8 +808,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /** * @brief Configure the DMA2D Layer according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: DMA2D handle - * @param LayerIdx: DMA2D Layer index + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -854,7 +836,6 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La if(hdma2d->Init.Mode != DMA2D_M2M) { assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode)); - assert_param(IS_DMA2D_ALPHA_VALUE(pLayerCfg->InputAlpha)); } } @@ -868,8 +849,16 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* Clear Input color mode, alpha value and alpha mode bits */ tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA); - /* Prepare the value to be wrote to the BGPFCCR register */ - tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); + if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) + { + /* Prepare the value to be wrote to the BGPFCCR register */ + tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000)); + } + else + { + /* Prepare the value to be wrote to the BGPFCCR register */ + tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); + } /* Write to DMA2D BGPFCCR register */ hdma2d->Instance->BGPFCCR = tmp; @@ -886,6 +875,15 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* Write to DMA2D BGOR register */ hdma2d->Instance->BGOR = tmp; + + if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) + { + /* Prepare the value to be wrote to the BGCOLR register */ + tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF); + + /* Write to DMA2D BGCOLR register */ + hdma2d->Instance->BGCOLR = tmp; + } } /* Configure the foreground DMA2D layer */ else @@ -897,8 +895,16 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* Clear Input color mode, alpha value and alpha mode bits */ tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA); - /* Prepare the value to be wrote to the FGPFCCR register */ - tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); + if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) + { + /* Prepare the value to be wrote to the FGPFCCR register */ + tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000)); + } + else + { + /* Prepare the value to be wrote to the FGPFCCR register */ + tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); + } /* Write to DMA2D FGPFCCR register */ hdma2d->Instance->FGPFCCR = tmp; @@ -915,6 +921,15 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* Write to DMA2D FGOR register */ hdma2d->Instance->FGOR = tmp; + + if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) + { + /* Prepare the value to be wrote to the FGCOLR register */ + tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF); + + /* Write to DMA2D FGCOLR register */ + hdma2d->Instance->FGCOLR = tmp; + } } /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; @@ -931,7 +946,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La * the configuration information for the DMA2D. * @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index + * @param LayerIdx: DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -1013,7 +1028,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf * @brief Enable the DMA2D CLUT Transfer. * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index + * @param LayerIdx: DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -1041,7 +1056,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay * @brief Disable the DMA2D CLUT Transfer. * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index + * @param LayerIdx: DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -1070,7 +1085,7 @@ HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t La * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @param Line: Line Watermark configuration. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) @@ -1108,7 +1123,7 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32 ##### Peripheral State and Errors functions ##### =============================================================================== [..] - This subsection provides functions allowing to + This subsection provides functions allowing to : (+) Check the DMA2D state (+) Get error code @@ -1211,11 +1226,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ } /* Write to DMA2D OCOLR register */ hdma2d->Instance->OCOLR = tmp; - } - else if ((hdma2d->LayerCfg[1].InputColorMode == CM_A4) || (hdma2d->LayerCfg[1].InputColorMode == CM_A8)) - { - hdma2d->Instance->FGCOLR = pdata; - } + } else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ { /* Configure DMA2D source address */ diff --git a/stmhal/hal/src/stm32f4xx_hal_dma_ex.c b/stmhal/hal/src/stm32f4xx_hal_dma_ex.c index 656b58875..9c0af63fc 100644 --- a/stmhal/hal/src/stm32f4xx_hal_dma_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_dma_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: @@ -21,7 +21,7 @@ -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. -@- In Multi (Double) buffer mode, it is possible to update the base address for - the AHB memory port on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. @endverbatim ****************************************************************************** @@ -217,8 +217,8 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ * @param Address: The new address * @param memory: the memory to be changed, This parameter can be one of * the following values: - * @arg MEMORY0 - * @arg MEMORY1 + * MEMORY0 / + * MEMORY1 * @note The MEMORY0 address can be changed only when the current transfer use * MEMORY1 and the MEMORY1 address can be changed only when the current * transfer use MEMORY0. diff --git a/stmhal/hal/src/stm32f4xx_hal_eth.c b/stmhal/hal/src/stm32f4xx_hal_eth.c index 4832aa2db..739760242 100644 --- a/stmhal/hal/src/stm32f4xx_hal_eth.c +++ b/stmhal/hal/src/stm32f4xx_hal_eth.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_eth.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: @@ -113,6 +113,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */ +#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -152,14 +155,15 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); /** * @brief Initializes the Ethernet MAC and DMA according to default * parameters. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { uint32_t tmpreg = 0, phyreg = 0; uint32_t hclk = 60000000; - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t err = ETH_SUCCESS; /* Check the ETH peripheral state */ @@ -258,30 +262,32 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) { + /* Get tick */ + tickstart = HAL_GetTick(); + /* We wait for linked status */ do { - timeout++; HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS) && (timeout < PHY_READ_TO)); + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); - if(timeout == PHY_READ_TO) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Reset Timeout counter */ - timeout = 0; + return HAL_TIMEOUT; + } + } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); + /* Enable Auto-Negotiation */ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) @@ -299,16 +305,37 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) return HAL_ERROR; } + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until the auto-negotiation will be completed */ do { - timeout++; HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE) && (timeout < PHY_READ_TO)); + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); - if(timeout == PHY_READ_TO) + return HAL_TIMEOUT; + } + + } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); + + /* Read the result of the auto-negotiation */ + if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) { - /* In case of timeout */ + /* In case of write timeout */ err = ETH_ERROR; /* Config MAC and DMA */ @@ -318,15 +345,9 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) heth->State = HAL_ETH_STATE_READY; /* Return HAL_ERROR */ - return HAL_ERROR; + return HAL_ERROR; } - /* Reset Timeout counter */ - timeout = 0; - - /* Read the result of the auto-negotiation */ - HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg); - /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) { @@ -389,7 +410,8 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /** * @brief De-Initializes the ETH peripheral. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) @@ -412,7 +434,8 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) /** * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param DMATxDescTab: Pointer to the first Tx desc list * @param TxBuff: Pointer to the first TxBuffer list * @param TxBuffCount: Number of the used Tx desc in the list @@ -478,7 +501,8 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param DMARxDescTab: Pointer to the first Rx desc list * @param RxBuff: Pointer to the first RxBuffer list * @param RxBuffCount: Number of the used Rx desc in the list @@ -547,7 +571,8 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the ETH MSP. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) @@ -559,7 +584,8 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) /** * @brief DeInitializes ETH MSP. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) @@ -588,7 +614,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) HAL_ETH_GetReceivedFrame_IT(); (+) Read from an External PHY register HAL_ETH_ReadPHYRegister(); - (+) Writo to an External PHY register + (+) Write to an External PHY register HAL_ETH_WritePHYRegister(); @endverbatim @@ -598,7 +624,8 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) /** * @brief Sends an Ethernet frame. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param FrameLength: Amount of data to be sent * @retval HAL status */ @@ -711,7 +738,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /** * @brief Checks for received frames. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) @@ -784,12 +812,14 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) /* Process Unlocked */ __HAL_UNLOCK(heth); + /* Return function status */ return HAL_ERROR; } /** * @brief Gets the Received frame in interrupt mode. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) @@ -868,12 +898,13 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) __HAL_UNLOCK(heth); /* Return function status */ - return HAL_OK; + return HAL_ERROR; } /** * @brief This function handles ETH interrupt request. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval HAL status */ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) @@ -932,7 +963,8 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) /** * @brief Tx Transfer completed callbacks. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) @@ -944,7 +976,8 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) /** * @brief Rx Transfer completed callbacks. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) @@ -956,7 +989,8 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) /** * @brief Ethernet transfer error callbacks - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) @@ -968,20 +1002,20 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) /** * @brief Reads a PHY register - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: - * @arg PHY_BCR: Transceiver Basic Control Register - * @arg PHY_BSR: Transceiver Basic Status Register - * @arg More PHY register could be read depending on the used PHY + * PHY_BCR: Transceiver Basic Control Register, + * PHY_BSR: Transceiver Basic Status Register. + * More PHY register could be read depending on the used PHY * @param RegValue: PHY register value - * @retval HAL_TIMEOUT: in case of timeout - * MACMIIDR register value: Data read from the selected PHY register (correct read ) + * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) { uint32_t tmpreg = 0; - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); @@ -1009,20 +1043,24 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR /* Write the result value into the MII Address register */ heth->Instance->MACMIIAR = tmpreg; - /* Check for the Busy flag */ - do - { - timeout++; - tmpreg = heth->Instance->MACMIIAR; - } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_READ_TO)); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Return ERROR in case of timeout */ - if(timeout == PHY_READ_TO) + /* Check for the Busy flag */ + while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - /* Return HAL_TIMEOUT */ - return HAL_TIMEOUT; + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > PHY_READ_TO) + { + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + + tmpreg = heth->Instance->MACMIIAR; } /* Get MACMIIDR value */ @@ -1037,18 +1075,19 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR /** * @brief Writes to a PHY register. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: - * @arg PHY_BCR: Transceiver Control Register - * @arg More PHY register could be written depending on the used PHY + * PHY_BCR: Transceiver Control Register. + * More PHY register could be written depending on the used PHY * @param RegValue: the value to write * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) { uint32_t tmpreg = 0; - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); @@ -1079,20 +1118,24 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY /* Write the result value into the MII Address register */ heth->Instance->MACMIIAR = tmpreg; - /* Check for the Busy flag */ - do - { - timeout++; - tmpreg = heth->Instance->MACMIIAR; - } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_WRITE_TO)); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Return TIMETOUT in case of timeout */ - if(timeout == PHY_WRITE_TO) + /* Check for the Busy flag */ + while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) + { + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + + tmpreg = heth->Instance->MACMIIAR; } /* Set ETH HAL State to READY */ @@ -1129,7 +1172,8 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY /** * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) @@ -1167,7 +1211,8 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) /** * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) @@ -1205,7 +1250,8 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) /** * @brief Set ETH MAC Configuration. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param macconf: MAC Configuration structure * @retval HAL status */ @@ -1371,7 +1417,8 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /** * @brief Sets ETH DMA Configuration. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param dmaconf: DMA Configuration structure * @retval HAL status */ @@ -1478,7 +1525,8 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /** * @brief Return the ETH HAL state - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval HAL state */ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) @@ -1493,7 +1541,8 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) /** * @brief Configures Ethernet MAC and DMA with default parameters. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param err: Ethernet Init error * @retval HAL status */ @@ -1749,7 +1798,8 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /** * @brief Configures the selected MAC address. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @param MacAddr: The MAC address to configure * This parameter can be one of the following values: * @arg ETH_MAC_Address0: MAC Address0 @@ -1779,7 +1829,8 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint /** * @brief Enables the MAC transmission. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) @@ -1798,7 +1849,8 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC transmission. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) @@ -1817,7 +1869,8 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the MAC reception. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) @@ -1836,7 +1889,8 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC reception. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) @@ -1855,7 +1909,8 @@ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA transmission. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) @@ -1866,7 +1921,8 @@ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the DMA transmission. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) @@ -1877,7 +1933,8 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA reception. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) @@ -1888,7 +1945,8 @@ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the DMA reception. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) @@ -1899,7 +1957,8 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Clears the ETHERNET transmit FIFO. - * @param heth: ETH handle + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) diff --git a/stmhal/hal/src/stm32f4xx_hal_flash.c b/stmhal/hal/src/stm32f4xx_hal_flash.c index a10bf8196..8b19463eb 100644 --- a/stmhal/hal/src/stm32f4xx_hal_flash.c +++ b/stmhal/hal/src/stm32f4xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -212,7 +212,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { @@ -387,11 +387,11 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Mass Erase: Bank number which has been requested to erase - * - Sectors Erase: Sector which has been erased + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector which has been erased * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) - * - Program: Address which was selected for data program - * @retval none + * Program: Address which was selected for data program + * @retval None */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { @@ -403,10 +403,10 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Mass Erase: Bank number which has been requested to erase - * - Sectors Erase: Sector number which returned an error - * - Program: Address which was selected for data program - * @retval none + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { @@ -437,7 +437,7 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) /** * @brief Unlock the FLASH control register access * @param None - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { @@ -458,7 +458,7 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) /** * @brief Locks the FLASH control register access * @param None - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { @@ -472,7 +472,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) /** * @brief Unlock the FLASH Option Control Registers access. * @param None - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { @@ -493,7 +493,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) /** * @brief Lock the FLASH Option Control Registers access. * @param None - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { @@ -506,7 +506,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) /** * @brief Launch the option byte loading. * @param None - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { @@ -529,7 +529,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) ##### Peripheral Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time Errors of the FLASH peripheral. + This subsection permits to get in run-time Errors of the FLASH peripheral. @endverbatim * @{ @@ -558,21 +558,22 @@ FLASH_ErrorTypeDef HAL_FLASH_GetError(void) /** * @brief Wait for a FLASH operation to complete. * @param Timeout: maximum flash operationtimeout - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { + uint32_t tickstart = 0; /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - - uint32_t timeout = HAL_GetTick() + Timeout; - + /* Get tick */ + tickstart = HAL_GetTick(); + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { return HAL_TIMEOUT; } diff --git a/stmhal/hal/src/stm32f4xx_hal_flash_ex.c b/stmhal/hal/src/stm32f4xx_hal_flash_ex.c index 7846c8caf..828cd2f82 100644 --- a/stmhal/hal/src/stm32f4xx_hal_flash_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -30,7 +30,7 @@ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Erase function: Erase sector, erase all sectors - (++) There is two mode of erase : + (++) There are two modes of erase : (+++) Polling Mode using HAL_FLASHEx_Erase() (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() @@ -113,10 +113,10 @@ static uint16_t FLASH_OB_GetWRP(void); static FlagStatus FLASH_OB_GetRDP(void); static uint8_t FLASH_OB_GetBOR(void); -#if defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector); static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector); -#endif /* STM32F401xC || STM32F401xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); @@ -154,7 +154,7 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); * contains the configuration information on faulty sector in case of error * (0xFFFFFFFF means that all the sectors have been correctly erased) * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) { @@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { @@ -277,7 +277,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) * @param pOBInit: pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { @@ -355,13 +355,14 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) pOBInit->BORLevel = FLASH_OB_GetBOR(); } -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** * @brief Program option bytes * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) { @@ -378,20 +379,20 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO if ((pAdvOBInit->PCROPState) == PCROPSTATE_ENABLE) { /*Enable of Write protection on the selected Sector*/ -#if defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors); #else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); -#endif /* STM32F401xC || STM32F401xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ } else { /*Disable of Write protection on the selected Sector*/ -#if defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors); #else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); -#endif /* STM32F401xC || STM32F401xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ } } @@ -415,7 +416,7 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO */ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) { -#if defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /*Get Sector*/ pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); #else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ @@ -427,7 +428,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) /*Get Boot config OB*/ pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS; -#endif /* STM32F401xC || STM32F401xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ } /** @@ -440,7 +441,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) * @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices. * * @param None - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) { @@ -466,7 +467,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) * @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices. * * @param None - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) { @@ -481,7 +482,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) return HAL_OK; } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) @@ -522,7 +523,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) * @arg FLASH_BANK_2: Bank2 to be erased * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) { @@ -801,7 +802,7 @@ static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig) * @arg FLASH_BANK_2: WRP on all sectors of bank2 * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) { @@ -865,7 +866,7 @@ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t Sec * @arg FLASH_BANK_2: WRP on all sectors of bank2 * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) { @@ -914,7 +915,8 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** * @brief Mass erase of FLASH memory * @param VoltageRange: The device voltage range which defines the erase parallelism. @@ -1014,7 +1016,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) { @@ -1050,7 +1052,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) { @@ -1070,9 +1072,9 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) return status; } -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ -#if defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** * @brief Enable the read/write protection (PCROP) of the desired sectors. * @note This function can be used only for STM32F401xx devices. @@ -1080,7 +1082,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 * @arg OB_PCROP_Sector_All - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) { @@ -1108,7 +1110,7 @@ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 * @arg OB_PCROP_Sector_All - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) { @@ -1128,7 +1130,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) return status; } -#endif /* STM32F401xC || STM32F401xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ /** * @brief Set the read protection level. @@ -1140,7 +1142,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) * * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 * - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) { @@ -1174,7 +1176,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) * This parameter can be one of the following values: * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby) { @@ -1210,7 +1212,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) { diff --git a/stmhal/hal/src/stm32f4xx_hal_flash_ramfunc.c b/stmhal/hal/src/stm32f4xx_hal_flash_ramfunc.c new file mode 100644 index 000000000..6627b334c --- /dev/null +++ b/stmhal/hal/src/stm32f4xx_hal_flash_ramfunc.c @@ -0,0 +1,199 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ramfunc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-June-2014 + * @brief FLASH RAMFUNC module driver. + * This file provides a FLASH firmware functions which should be + * executed from internal SRAM + * + Stop/Start the flash interface while System Run + * + Enable/Disable the flash sleep while System Run + @verbatim + ============================================================================== + ##### APIs executed from Internal RAM ##### + ============================================================================== + [..] + *** ARM Compiler *** + -------------------- + [..] RAM functions are defined using the toolchain options. + Functions that are be executed in RAM should reside in a separate + source module. Using the 'Options for File' dialog you can simply change + the 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + Options for Target' dialog. + + *** ICCARM Compiler *** + ----------------------- + [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". + + *** GNU Compiler *** + -------------------- + [..] RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH_RAMFUNC + * @brief FLASH functions executed from RAM + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +#if defined(STM32F411xE) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_RAMFUNC_Private_Functions + * @{ + */ + +/** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### ramfunc functions ##### + =============================================================================== + [..] + This subsection provides a set of functions that should be executed from RAM + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Stop the flash interface while System Run + * @note This mode is only available for STM32F411xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @param None + * @retval None + */ +__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void) +{ + /* Enable Power ctrl clock */ + __PWR_CLK_ENABLE(); + /* Stop the flash interface while System Run */ + SET_BIT(PWR->CR, PWR_CR_FISSR); + + return HAL_OK; +} + +/** + * @brief Start the flash interface while System Run + * @note This mode is only available for STM32F411xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @param None + * @retval None + */ +__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void) +{ + /* Enable Power ctrl clock */ + __PWR_CLK_ENABLE(); + /* Start the flash interface while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FISSR); + + return HAL_OK; +} + +/** + * @brief Enable the flash sleep while System Run + * @note This mode is only available for STM32F411xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @param None + * @retval None + */ +__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void) +{ + /* Enable Power ctrl clock */ + __PWR_CLK_ENABLE(); + /* Enable the flash sleep while System Run */ + SET_BIT(PWR->CR, PWR_CR_FMSSR); + + return HAL_OK; +} + +/** + * @brief Disable the flash sleep while System Run + * @note This mode is only available for STM32F411xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @param None + * @retval None + */ +__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void) +{ + /* Enable Power ctrl clock */ + __PWR_CLK_ENABLE(); + /* Disable the flash sleep while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F411xE */ +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stmhal/hal/src/stm32f4xx_hal_gpio.c b/stmhal/hal/src/stm32f4xx_hal_gpio.c index 6aaf5a238..7d5ae24c8 100644 --- a/stmhal/hal/src/stm32f4xx_hal_gpio.c +++ b/stmhal/hal/src/stm32f4xx_hal_gpio.c @@ -2,18 +2,18 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + * @verbatim ============================================================================== ##### GPIO Peripheral features ##### - ============================================================================== + ============================================================================== [..] (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes: @@ -22,7 +22,7 @@ (++) Output mode (++) Alternate function mode (++) External interrupt/event lines - + (+) During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. @@ -31,27 +31,27 @@ (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. - + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an IO pin at a time. In this way, there can be no conflict between peripherals sharing the same IO pin. - + (+) All ports have external interrupt/event capability. To use external interrupt lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - + (+) The external interrupt/event controller consists of up to 23 edge detectors (16 lines are connected to GPIO) for generating event/interrupt requests (each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also be masked independently. - + ##### How to use this driver ##### ============================================================================== - [..] + [..] (#) Enable the GPIO AHB clock using the following function: __GPIOx_CLK_ENABLE(). - + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef @@ -65,7 +65,7 @@ (++) In case of external interrupt/event selection the "Mode" member from GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). - + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). @@ -135,7 +135,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ -#define __HAL_GET_GPIO_SOURCE(__GPIOx__) \ +#define GET_GPIO_SOURCE(__GPIOx__) \ (((uint32_t)(__GPIOx__) == ((uint32_t)GPIOA_BASE))? (uint32_t)0 :\ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0400)))? (uint32_t)1 :\ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0800)))? (uint32_t)2 :\ @@ -213,14 +213,17 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ - temp = ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[position >> 3] |= temp; + temp = GPIOx->AFR[position >> 3]; + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + GPIOx->AFR[position >> 3] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); - GPIOx->MODER |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + GPIOx->MODER = temp; /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || @@ -229,18 +232,23 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - GPIOx->OSPEEDR |= (GPIO_Init->Speed << (position * 2)); + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + temp |= (GPIO_Init->Speed << (position * 2)); + GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; - GPIOx->OTYPER |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + GPIOx->OTYPER = temp; } /* Activate the Pull-up or Pull down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - GPIOx->PUPDR |= ((GPIO_Init->Pull) << (position * 2)); - + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + temp |= ((GPIO_Init->Pull) << (position * 2)); + GPIOx->PUPDR = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ @@ -249,35 +257,44 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Enable SYSCFG Clock */ __SYSCFG_CLK_ENABLE(); - temp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~temp; - SYSCFG->EXTICR[position >> 2] |= ((uint32_t)(__HAL_GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03))); - - /* Clear EXTI line configuration */ - EXTI->IMR &= ~((uint32_t)iocurrent); - EXTI->EMR &= ~((uint32_t)iocurrent); + temp = SYSCFG->EXTICR[position >> 2]; + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + temp |= ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03))); + SYSCFG->EXTICR[position >> 2] = temp; + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~((uint32_t)iocurrent); if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { - EXTI->IMR |= iocurrent; + temp |= iocurrent; } + EXTI->IMR = temp; + + temp = EXTI->EMR; + temp &= ~((uint32_t)iocurrent); if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { - EXTI->EMR |= iocurrent; + temp |= iocurrent; } + EXTI->EMR = temp; /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~((uint32_t)iocurrent); - EXTI->FTSR &= ~((uint32_t)iocurrent); - + temp = EXTI->RTSR; + temp &= ~((uint32_t)iocurrent); if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { - EXTI->RTSR |= iocurrent; + temp |= iocurrent; } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~((uint32_t)iocurrent); if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { - EXTI->FTSR |= iocurrent; + temp |= iocurrent; } + EXTI->FTSR = temp; } } } @@ -324,7 +341,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - /*------------------------- EXTI Mode Configuration --------------------*/ /* Configure the External Interrupt or event for the current IO */ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); @@ -370,7 +386,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) GPIO_PinState bitstatus; /* Check the parameters */ - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) { @@ -396,14 +412,14 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @param PinState: specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_BIT_RESET: to clear the port pin - * @arg GPIO_BIT_SET: to set the port pin + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { /* Check the parameters */ - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) @@ -426,11 +442,50 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->ODR ^= GPIO_Pin; } +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + /** * @brief This function handles EXTI interrupt request. * @param GPIO_Pin: Specifies the pins connected EXTI line diff --git a/stmhal/hal/src/stm32f4xx_hal_hash.c b/stmhal/hal/src/stm32f4xx_hal_hash.c index 232ebff8e..6522148ba 100644 --- a/stmhal/hal/src/stm32f4xx_hal_hash.c +++ b/stmhal/hal/src/stm32f4xx_hal_hash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: @@ -148,7 +148,8 @@ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size); /** * @brief Initializes the HASH according to the specified parameters in the HASH_HandleTypeDef and creates the associated handle. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) @@ -192,7 +193,8 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /** * @brief DeInitializes the HASH peripheral. * @note This API must be called before starting a new processing. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) @@ -229,7 +231,8 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH MSP. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval None */ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) @@ -241,7 +244,8 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) /** * @brief DeInitializes HASH MSP. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval None */ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) @@ -253,7 +257,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Input data transfer complete callback. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval None */ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) @@ -265,7 +270,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Data transfer Error callback. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval None */ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) @@ -278,7 +284,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Digest computation complete callback. It is used only with interrupt. * @note This callback is not relevant with DMA. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval None */ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) @@ -311,9 +318,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param pOutBuffer: Pointer to the Output buffer (hashed buffer). * @param Size: Length of the input buffer in bytes. * If the Size is multiple of 64 bytes, appending the input buffer is possible. * If the Size is not multiple of 64 bytes, the padding is managed by hardware @@ -324,7 +331,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) */ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -352,20 +359,20 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -388,7 +395,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is multiple of 64 bytes, appending the input buffer is possible. @@ -434,9 +442,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: HASH handle - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param pOutBuffer: Pointer to the Output buffer (hashed buffer). + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module + * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. @@ -445,7 +453,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pI */ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -473,20 +481,20 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -510,7 +518,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -575,8 +584,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p /** * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: HASH handle - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pOutBuffer: Pointer to the Output buffer (hashed buffer). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -727,9 +736,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: HASH handle - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param pOutBuffer: Pointer to the Output buffer (hashed buffer). + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module + * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. @@ -880,7 +889,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief This function handles HASH interrupt request. - * @param hhash: hash handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval None */ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) @@ -923,11 +933,11 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to control data transfer. Use HAL_HASH_MD5_Finish() to get the digest. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -974,14 +984,15 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Returns the computed digest in MD5 mode - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -989,20 +1000,20 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu /* Change HASH peripheral state */ hhash->State = HAL_HASH_STATE_BUSY; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -1026,11 +1037,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu /** * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -1078,14 +1089,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Returns the computed digest in SHA1 mode. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -1093,19 +1105,19 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB /* Change HASH peripheral state */ hhash->State = HAL_HASH_STATE_BUSY; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -1150,7 +1162,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB /** * @brief Initializes the HASH peripheral in HMAC MD5 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -1160,7 +1173,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB */ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -1197,20 +1210,20 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -1227,20 +1240,20 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > Timeout) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -1257,20 +1270,20 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > Timeout) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -1294,7 +1307,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief Initializes the HASH peripheral in HMAC SHA1 mode * then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -1304,7 +1318,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -1341,20 +1355,20 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -1371,20 +1385,20 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > Timeout) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -1401,20 +1415,20 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > Timeout) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hhash); return HAL_TIMEOUT; @@ -1434,9 +1448,6 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf return HAL_OK; } - - - /** * @} */ @@ -1460,7 +1471,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** * @brief Initializes the HASH peripheral in HMAC MD5 mode * then enables DMA to control data transfer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -1526,7 +1538,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Initializes the HASH peripheral in HMAC SHA1 mode * then enables DMA to control data transfer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -1609,7 +1622,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief return the HASH state - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval HAL state */ HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) diff --git a/stmhal/hal/src/stm32f4xx_hal_hash_ex.c b/stmhal/hal/src/stm32f4xx_hal_hash_ex.c index 35c0d3788..85b44eaa0 100644 --- a/stmhal/hal/src/stm32f4xx_hal_hash_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_hash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HASH HAL Extension module driver. * This file provides firmware functions to manage the following * functionalities of HASH peripheral: @@ -143,9 +143,9 @@ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initializes the HASH peripheral in SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param pOutBuffer: Pointer to the output buffer (hashed buffer). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. @@ -154,7 +154,7 @@ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma); */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -182,15 +182,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -219,9 +219,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: HASH handle - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param pOutBuffer: Pointer to the output buffer (hashed buffer). + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module + * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes. @@ -230,7 +230,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -258,15 +258,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -296,7 +296,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -341,7 +342,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -406,9 +408,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initializes the HASH peripheral in HMAC SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: HASH handle - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param pOutBuffer: Pointer to the output buffer (hashed buffer). + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module + * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. @@ -416,7 +418,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -453,15 +455,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -483,15 +485,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > Timeout) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -513,15 +515,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > Timeout) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -549,9 +551,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in HMAC SHA256 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: HASH handle - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param pOutBuffer: Pointer to the output buffer (hashed buffer). + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module + * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. @@ -559,7 +561,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -599,15 +601,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -629,15 +631,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > Timeout) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -659,15 +661,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /* Start the digest calculation */ __HAL_HASH_START_DIGEST(); - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > Timeout) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -715,7 +717,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -858,7 +861,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -1000,7 +1004,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief This function handles HASH interrupt request. - * @param hhash: hash handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @retval None */ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash) @@ -1045,11 +1050,11 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -1096,13 +1101,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Returns the computed digest in SHA224 - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -1110,15 +1117,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /* Change HASH peripheral state */ hhash->State = HAL_HASH_STATE_BUSY; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -1147,11 +1154,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -1198,13 +1205,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Returns the computed digest in SHA256. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes. + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hhash); @@ -1212,15 +1221,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /* Change HASH peripheral state */ hhash->State = HAL_HASH_STATE_BUSY; - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hhash->State = HAL_HASH_STATE_TIMEOUT; @@ -1269,7 +1278,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initializes the HASH peripheral in HMAC SHA224 mode * then enables DMA to control data transfer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. @@ -1335,7 +1345,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initializes the HASH peripheral in HMAC SHA256 mode * then enables DMA to control data transfer. - * @param hhash: HASH handle + * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). * @param Size: Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. diff --git a/stmhal/hal/src/stm32f4xx_hal_hcd.c b/stmhal/hal/src/stm32f4xx_hal_hcd.c index 35f526583..dd1916baa 100644 --- a/stmhal/hal/src/stm32f4xx_hal_hcd.c +++ b/stmhal/hal/src/stm32f4xx_hal_hcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hcd.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -25,9 +25,9 @@ (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: - (##) Enable the HCD/USB Low Level interface clock using - (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE(); - (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode) + (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE() + (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode (##) Initialize the related GPIO clocks (##) Configure HCD pin-out @@ -113,8 +113,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); /** * @brief Initialize the host driver - * @param hhcd : HCD handle - * @retval HAL state + * @param hhcd: HCD handle + * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) { @@ -127,7 +127,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); - hhcd->State = HCD_BUSY; + hhcd->State = HAL_HCD_STATE_BUSY; /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_HCD_MspInit(hhcd); @@ -144,34 +144,34 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Init Host */ USB_HostInit(hhcd->Instance, hhcd->Init); - hhcd->State= HCD_READY; + hhcd->State= HAL_HCD_STATE_READY; return HAL_OK; } /** * @brief Initialize a host channel - * @param hhcd : HCD handle - * @param ch_num : Channel number + * @param hhcd: HCD handle + * @param ch_num: Channel number. * This parameter can be a value from 1 to 15 - * @param epnum : Endpoint number + * @param epnum: Endpoint number. * This parameter can be a value from 1 to 15 * @param dev_address : Current device address * This parameter can be a value from 0 to 255 - * @param speed : Current device speed - * This parameter can be one of the these values: - * @arg HCD_SPEED_HIGH: High speed mode - * @arg HCD_SPEED_FULL: Full speed mode - * @arg HCD_SPEED_LOW: Low speed mode - * @param ep_type : Endpoint Type - * This parameter can be one of the these values: - * @arg EP_TYPE_CTRL: Control type - * @arg EP_TYPE_ISOC: Isochrounous type - * @arg EP_TYPE_BULK: Bulk type - * @arg EP_TYPE_INTR: Interrupt type - * @param mps : Max Packet Size + * @param speed: Current device speed. + * This parameter can be one of these values: + * HCD_SPEED_HIGH: High speed mode, + * HCD_SPEED_FULL: Full speed mode, + * HCD_SPEED_LOW: Low speed mode + * @param ep_type: Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochrounous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps: Max Packet Size. * This parameter can be a value from 0 to32K - * @retval HAL state + * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, @@ -209,10 +209,10 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, /** * @brief Halt a host channel - * @param hhcd : HCD handle - * @param ch_num : Channel number + * @param hhcd: HCD handle + * @param ch_num: Channel number. * This parameter can be a value from 1 to 15 - * @retval HAL state + * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) @@ -227,8 +227,8 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, } /** * @brief DeInitialize the host driver - * @param hhcd : HCD handle - * @retval HAL state + * @param hhcd: HCD handle + * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) { @@ -238,14 +238,14 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) return HAL_ERROR; } - hhcd->State = HCD_BUSY; + hhcd->State = HAL_HCD_STATE_BUSY; /* DeInit the low level hardware */ HAL_HCD_MspDeInit(hhcd); __HAL_HCD_DISABLE(hhcd); - hhcd->State = HCD_READY; + hhcd->State = HAL_HCD_STATE_RESET; return HAL_OK; } @@ -294,30 +294,27 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhhcd) /** * @brief Submit a new URB for processing - * @param hhcd : HCD handle - * @param ch_num : Channel number + * @param hhcd: HCD handle + * @param ch_num: Channel number. * This parameter can be a value from 1 to 15 - * @param direction : Channel number - * This parameter can be one of the these values: - * 0 : Output - * 1 : Input - * @param ep_type : Endpoint Type - * This parameter can be one of the these values: - * @arg EP_TYPE_CTRL: Control type - * @arg EP_TYPE_ISOC: Isochrounous type - * @arg EP_TYPE_BULK: Bulk type - * @arg EP_TYPE_INTR: Interrupt type - * @param token : Endpoint Type - * This parameter can be one of the these values: - * @arg 0: HC_PID_SETUP - * @arg 1: HC_PID_DATA1 - * @param pbuff : pointer to URB data - * @param length : Length of URB data - * @param do_ping : activate do ping protocol (for high speed only) - * This parameter can be one of the these values: - * 0 : do ping inactive - * 1 : do ping active - * @retval HAL state + * @param direction: Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type: Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochrounous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token: Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff: pointer to URB data + * @param length: Length of URB data + * @param do_ping: activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, @@ -442,7 +439,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, /** * @brief This function handles HCD interrupt request. * @param hhcd: HCD handle - * @retval none + * @retval None */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { @@ -583,16 +580,16 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Notify URB state change callback. * @param hhcd: HCD handle - * @param chnum : Channel number + * @param chnum: Channel number. * This parameter can be a value from 1 to 15 * @param urb_state: - * This parameter can be one of the these values: - * @arg URB_IDLE - * @arg URB_DONE - * @arg URB_NOTREADY - * @arg URB_NYET - * @arg URB_ERROR - * @arg URB_STALL + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ * @retval None */ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) @@ -623,8 +620,8 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t /** * @brief Start the host driver - * @param hhcd : HCD handle - * @retval HAL state + * @param hhcd: HCD handle + * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { @@ -637,8 +634,8 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) /** * @brief Stop the host driver - * @param hhcd : HCD handle - * @retval HAL state + * @param hhcd: HCD handle + * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) @@ -651,8 +648,8 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) /** * @brief Reset the host port - * @param hhcd : HCD handle - * @retval HAL state + * @param hhcd: HCD handle + * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) { @@ -671,7 +668,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -680,7 +677,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) /** * @brief Return the HCD state - * @param hhcd : HCD handle + * @param hhcd: HCD handle * @retval HAL state */ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) @@ -690,17 +687,17 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) /** * @brief Return URB state for a channel - * @param hhcd : HCD handle - * @param chnum : Channel number + * @param hhcd: HCD handle + * @param chnum: Channel number. * This parameter can be a value from 1 to 15 - * @retval URB state - * This parameter can be one of the these values: - * @arg URB_IDLE - * @arg URB_DONE - * @arg URB_NOTREADY - * @arg URB_NYET - * @arg URB_ERROR - * @arg URB_STALL + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL */ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) { @@ -710,8 +707,8 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu /** * @brief Return the last host transfer size - * @param hhcd : HCD handle - * @param chnum : Channel number + * @param hhcd: HCD handle + * @param chnum: Channel number. * This parameter can be a value from 1 to 15 * @retval last transfer size in byte */ @@ -722,20 +719,20 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Return the Host Channel state - * @param hhcd : HCD handle - * @param chnum : Channel number + * @param hhcd: HCD handle + * @param chnum: Channel number. * This parameter can be a value from 1 to 15 * @retval Host channel state * This parameter can be one of the these values: - * @arg HC_IDLE - * @arg HC_XFRC - * @arg HC_HALTED - * @arg HC_NYET - * @arg HC_NAK - * @arg HC_STALL - * @arg HC_XACTERR - * @arg HC_BBLERR - * @arg HC_DATATGLERR + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR/ */ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) { @@ -744,8 +741,8 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Return the current Host frame number - * @param hhcd : HCD handle - * @retval current Host frame number + * @param hhcd: HCD handle + * @retval Current Host frame number */ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) { @@ -754,7 +751,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) /** * @brief Return the Host enumeration speed - * @param hhcd : HCD handle + * @param hhcd: HCD handle * @retval Enumeration speed */ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) @@ -769,7 +766,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) /** * @brief This function handles Host Channel IN interrupt requests. * @param hhcd: HCD handle - * @param chnum : Channel number + * @param chnum: Channel number. * This parameter can be a value from 1 to 15 * @retval none */ @@ -908,7 +905,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief This function handles Host Channel OUT interrupt requests. * @param hhcd: HCD handle - * @param chnum : Channel number + * @param chnum: Channel number. * This parameter can be a value from 1 to 15 * @retval none */ @@ -1100,7 +1097,7 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) /** * @brief This function handles Host Port interrupt requests. * @param hhcd: HCD handle - * @retval none + * @retval None */ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) { diff --git a/stmhal/hal/src/stm32f4xx_hal_i2c.c b/stmhal/hal/src/stm32f4xx_hal_i2c.c index b48590636..1c1a0d76d 100644 --- a/stmhal/hal/src/stm32f4xx_hal_i2c.c +++ b/stmhal/hal/src/stm32f4xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -36,18 +36,18 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx Stream (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the HAL_I2C_Init() API: - (+++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API. (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - (#) For I2C IO and IO MEM operations, three mode of operations are available within this driver : + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -141,9 +141,9 @@ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral (+) __HAL_I2C_DISABLE: Disable the I2C peripheral (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt + (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt [..] (@) You can refer to the I2C HAL driver header file for more useful macros @@ -270,8 +270,8 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); /** * @brief Initializes the I2C according to the specified parameters * in the I2C_InitTypeDef and create the associated handle. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) @@ -348,8 +348,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /** * @brief DeInitializes the I2C peripheral. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) @@ -383,8 +383,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief I2C MSP Init. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) @@ -396,8 +396,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief I2C MSP DeInit - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) @@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) This subsection provides a set of functions allowing to manage the I2C data transfers. - (#) There is two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. @@ -457,7 +457,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Mem_Write_DMA() (++) HAL_I2C_Mem_Read_DMA() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_I2C_MemTxCpltCallback() (++) HAL_I2C_MemRxCpltCallback() (++) HAL_I2C_MasterTxCpltCallback() @@ -472,8 +472,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -570,8 +570,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /** * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -762,8 +762,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /** * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -867,8 +867,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /** * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -959,8 +959,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /** * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -1030,8 +1030,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /** * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -1129,8 +1129,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /** * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1182,8 +1182,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /** * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1235,8 +1235,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /** * @brief Transmit in master mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -1311,8 +1311,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /** * @brief Receive in master mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -1398,8 +1398,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /** * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1483,8 +1483,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p /** * @brief Receive in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1549,8 +1549,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1649,8 +1649,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /** * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1842,8 +1842,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } /** * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1915,8 +1915,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /** * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -2018,8 +2018,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /** * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -2096,8 +2096,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /** * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -2189,8 +2189,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /** * @brief Checks if target device is ready for communication. * @note This function is used with Memory devices - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param Trials: Number of trials * @param Timeout: Timeout duration @@ -2198,7 +2198,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t timeout = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1; + uint32_t tickstart = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1; if(hi2c->State == HAL_I2C_STATE_READY) { @@ -2228,14 +2228,15 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress); /* Wait until ADDR or AF flag are set */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); tmp3 = hi2c->State; while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->State = HAL_I2C_STATE_TIMEOUT; } @@ -2299,8 +2300,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /** * @brief This function handles I2C event interrupt request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) @@ -2404,8 +2405,8 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /** * @brief This function handles I2C error interrupt request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) @@ -2474,8 +2475,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) /** * @brief Master Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2487,8 +2488,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) /** * @brief Master Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2499,8 +2500,8 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) } /** @brief Slave Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2512,8 +2513,8 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Slave Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2525,8 +2526,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Memory Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2538,8 +2539,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Memory Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2551,8 +2552,8 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief I2C error callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) @@ -2574,7 +2575,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) ##### Peripheral State and Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -2583,7 +2584,8 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Returns the I2C state. - * @param hi2c : I2C handle + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL state */ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) @@ -2608,15 +2610,12 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @brief Handle TXE flag for Master - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - /* Write data to DR */ hi2c->Instance->DR = (*hi2c->pBuffPtr++); hi2c->XferCount--; @@ -2627,31 +2626,22 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); } - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_OK; } /** * @brief Handle BTF flag for Master transmitter - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - if(hi2c->XferCount != 0) { /* Write data to DR */ hi2c->Instance->DR = (*hi2c->pBuffPtr++); hi2c->XferCount--; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); } else { @@ -2671,18 +2661,12 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) { hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - HAL_I2C_MemTxCpltCallback(hi2c); } else { hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - HAL_I2C_MasterTxCpltCallback(hi2c); } } @@ -2691,34 +2675,25 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) /** * @brief Handle RXNE flag for Master - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) { uint32_t tmp = 0; - /* Process Locked */ - __HAL_LOCK(hi2c); - tmp = hi2c->XferCount; if(tmp > 3) { /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); } else if((tmp == 2) || (tmp == 3)) { /* Disable BUF interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); } else { @@ -2739,18 +2714,12 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) { hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - HAL_I2C_MemRxCpltCallback(hi2c); } else { hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - HAL_I2C_MasterRxCpltCallback(hi2c); } } @@ -2759,15 +2728,12 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) /** * @brief Handle BTF flag for Master receiver - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - if(hi2c->XferCount == 3) { /* Disable Acknowledge */ @@ -2776,9 +2742,6 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); } else if(hi2c->XferCount == 2) { @@ -2806,18 +2769,12 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) { hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - HAL_I2C_MemRxCpltCallback(hi2c); } else { hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - HAL_I2C_MasterRxCpltCallback(hi2c); } } @@ -2826,135 +2783,100 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); } return HAL_OK; } /** * @brief Handle TXE flag for Slave - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(hi2c->XferCount != 0) + if(hi2c->XferCount != 0) { /* Write data to DR */ hi2c->Instance->DR = (*hi2c->pBuffPtr++); hi2c->XferCount--; } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Handle BTF flag for Slave transmitter - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(hi2c->XferCount != 0) + if(hi2c->XferCount != 0) { /* Write data to DR */ hi2c->Instance->DR = (*hi2c->pBuffPtr++); hi2c->XferCount--; } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Handle RXNE flag for Slave - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(hi2c->XferCount != 0) + if(hi2c->XferCount != 0) { /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Handle BTF flag for Slave receiver - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(hi2c->XferCount != 0) + if(hi2c->XferCount != 0) { /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Handle ADD flag for Slave - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Handle STOPF flag for Slave - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - /* Disable EVT, BUF and ERR interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -2972,24 +2894,18 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - HAL_I2C_SlaveRxCpltCallback(hi2c); return HAL_OK; } /** - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) { - /* Process Locked */ - __HAL_LOCK(hi2c); - /* Disable EVT, BUF and ERR interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -3007,17 +2923,14 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - HAL_I2C_SlaveTxCpltCallback(hi2c); return HAL_OK; } /** - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @retval HAL status */ @@ -3077,8 +2990,8 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_ /** * @brief Master sends target device address for read request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @retval HAL status */ @@ -3169,8 +3082,8 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t /** * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -3239,8 +3152,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /** * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -3622,8 +3535,8 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles I2C Communication Timeout. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param Flag: specifies the I2C flag to check. * @param Status: The new Flag status (SET or RESET). * @param Timeout: Timeout duration @@ -3631,9 +3544,10 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait until flag is set */ if(Status == RESET) @@ -3643,7 +3557,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; @@ -3662,7 +3576,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; @@ -3679,17 +3593,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /** * @brief This function handles I2C Communication Timeout for Master addressing phase. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @param Flag: specifies the I2C flag to check. * @param Timeout: Timeout duration * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) { @@ -3713,7 +3628,7 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; diff --git a/stmhal/hal/src/stm32f4xx_hal_i2c_ex.c b/stmhal/hal/src/stm32f4xx_hal_i2c_ex.c index 17cf28f33..06be48491 100644 --- a/stmhal/hal/src/stm32f4xx_hal_i2c_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_i2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief I2C Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C extension peripheral: @@ -14,8 +14,8 @@ ##### I2C peripheral extension features ##### ============================================================================== - [..] Comparing to other previous devices, the I2C interface for STM32F427X and - STM32F429X devices contains the following additional features + [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ + 429xx/439xx devices contains the following additional features : (+) Possibility to disable or enable Analog Noise Filter (+) Use of a configured Digital Noise Filter @@ -71,7 +71,8 @@ #ifdef HAL_I2C_MODULE_ENABLED -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -100,9 +101,9 @@ /** * @brief Configures I2C Analog noise filter. - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter : new state of the Analog filter. + * @param AnalogFilter: new state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) @@ -139,9 +140,9 @@ HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_ /** * @brief Configures I2C Digital noise filter. - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F. + * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) diff --git a/stmhal/hal/src/stm32f4xx_hal_i2s.c b/stmhal/hal/src/stm32f4xx_hal_i2s.c index bd7117626..e5e06462c 100644 --- a/stmhal/hal/src/stm32f4xx_hal_i2s.c +++ b/stmhal/hal/src/stm32f4xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -31,7 +31,7 @@ and HAL_I2S_Receive_DMA() APIs: (+++) Declare a DMA handle structure for the Tx/Rx stream. (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx Stream. (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the @@ -48,7 +48,7 @@ (+@) External clock source is configured after setting correctly the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. - (#) Three mode of operations are available within this driver : + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -56,7 +56,7 @@ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() - *** Interrupt mode IO operation *** + *** Interrupt mode IO operation *** =================================== [..] (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() @@ -68,11 +68,11 @@ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback + add his own code by customization of function pointer HAL_I2S_RxCpltCallback (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2S_ErrorCallback - *** DMA mode IO operation *** + *** DMA mode IO operation *** ============================== [..] (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() @@ -84,25 +84,25 @@ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback + add his own code by customization of function pointer HAL_I2S_RxCpltCallback (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2S_ErrorCallback - (+) Pause the DMA Transfer using HAL_I2S_DMAPause() - (+) Resume the DMA Transfer using HAL_I2S_DMAResume() - (+) Stop the DMA Transfer using HAL_I2S_DMAStop() - + (+) Pause the DMA Transfer using HAL_I2S_DMAPause() + (+) Resume the DMA Transfer using HAL_I2S_DMAResume() + (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + *** I2S HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in USART HAL driver. (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not - - [..] + + [..] (@) You can refer to the I2S HAL driver header file for more useful macros @endverbatim @@ -195,7 +195,8 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s); /** * @brief Initializes the I2S according to the specified parameters * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) @@ -375,7 +376,8 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /** * @brief DeInitializes the I2S peripheral - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) @@ -390,7 +392,8 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_I2S_MspDeInit(hi2s); - + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; hi2s->State = HAL_I2S_STATE_RESET; /* Release Lock */ @@ -401,7 +404,8 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP Init - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval None */ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) @@ -413,7 +417,8 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP DeInit - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval None */ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) @@ -438,7 +443,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) This subsection provides a set of functions allowing to manage the I2S data transfers. - (#) There is two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. @@ -460,7 +465,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) (++) HAL_I2S_Transmit_DMA() (++) HAL_I2S_Receive_DMA() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_I2S_TxCpltCallback() (++) HAL_I2S_RxCpltCallback() (++) HAL_I2S_ErrorCallback() @@ -471,7 +476,8 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief Transmit an amount of data in blocking mode - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pData: a 16-bit pointer to data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S @@ -550,7 +556,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin /** * @brief Receive an amount of data in blocking mode - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pData: a 16-bit pointer to data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S @@ -635,7 +642,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pData: a 16-bit pointer to data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S @@ -700,7 +708,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pData: a 16-bit pointer to the Receive data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S @@ -767,7 +776,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u /** * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pData: a 16-bit pointer to the Transmit data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S @@ -851,7 +861,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pData: a 16-bit pointer to the Receive data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S @@ -942,8 +953,9 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Pauses the audio stream playing from the Media. - * @param hi2s: I2S handle - * @retval None + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) { @@ -986,8 +998,9 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: I2S handle - * @retval None + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) { @@ -1037,8 +1050,9 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: I2S handle - * @retval None + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) { @@ -1086,8 +1100,9 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S interrupt request. - * @param hi2s: I2S handle - * @retval HAL status + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None */ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) { @@ -1106,7 +1121,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR); tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); - /* I2S Overrun error interrupt occured ---------------------------------*/ + /* I2S Overrun error interrupt occurred ---------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { __HAL_I2S_CLEAR_OVRFLAG(hi2s); @@ -1126,7 +1141,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR); tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); - /* I2S Underrun error interrupt occured --------------------------------*/ + /* I2S Underrun error interrupt occurred --------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { __HAL_I2S_CLEAR_UDRFLAG(hi2s); @@ -1158,7 +1173,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR; tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR; - /* I2Sext Overrun error interrupt occured ------------------------------*/ + /* I2Sext Overrun error interrupt occurred ------------------------------*/ if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR)) { /* Clear I2Sext OVR Flag */ @@ -1184,7 +1199,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR); tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); - /* I2S Underrun error interrupt occured --------------------------------*/ + /* I2S Underrun error interrupt occurred --------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { __HAL_I2S_CLEAR_UDRFLAG(hi2s); @@ -1211,7 +1226,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR); tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); - /* I2S Overrun error interrupt occured ---------------------------------*/ + /* I2S Overrun error interrupt occurred ---------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { __HAL_I2S_CLEAR_OVRFLAG(hi2s); @@ -1235,7 +1250,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR; tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR; - /* I2Sext Underrun error interrupt occured -----------------------------*/ + /* I2Sext Underrun error interrupt occurred -----------------------------*/ if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR)) { /* Clear I2Sext UDR Flag */ @@ -1256,7 +1271,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Tx Transfer Half completed callbacks - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval None */ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) @@ -1268,7 +1284,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Tx Transfer completed callbacks - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval None */ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) @@ -1280,7 +1297,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer half completed callbacks - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval None */ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) @@ -1292,7 +1310,8 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer completed callbacks - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval None */ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) @@ -1304,7 +1323,8 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief I2S error callbacks - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval None */ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) @@ -1326,7 +1346,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) ##### Peripheral State and Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1335,7 +1355,8 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S state - * @param hi2s : I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval HAL state */ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) @@ -1345,7 +1366,8 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S error code - * @param hi2s : I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval I2S Error Code */ HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) @@ -1359,7 +1381,8 @@ HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) /** * @brief DMA I2S transmit process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -1396,7 +1419,8 @@ void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S transmit process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1408,7 +1432,8 @@ void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -1444,7 +1469,8 @@ void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1456,7 +1482,8 @@ void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S communication error callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void I2S_DMAError(DMA_HandleTypeDef *hdma) @@ -1474,7 +1501,8 @@ void I2S_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval HAL status */ static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) @@ -1517,7 +1545,8 @@ static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval HAL status */ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s) @@ -1568,7 +1597,8 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S Communication Timeout. - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param Flag: Flag checked * @param State: Value of the flag expected * @param Timeout: Duration of the timeout @@ -1576,9 +1606,10 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s) */ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait until flag is set */ if(Status == RESET) @@ -1587,7 +1618,7 @@ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; @@ -1606,7 +1637,7 @@ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; diff --git a/stmhal/hal/src/stm32f4xx_hal_i2s_ex.c b/stmhal/hal/src/stm32f4xx_hal_i2s_ex.c index 64aa7441c..c57b6dbce 100644 --- a/stmhal/hal/src/stm32f4xx_hal_i2s_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_i2s_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2S extension peripheral: @@ -16,21 +16,21 @@ [..] (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving data simultaneously using two data lines. Each SPI peripheral has an extended block - called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3). + called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3). (#) The extension block is not a full SPI IP, it is used only as I2S slave to implement full duplex mode. The extension block uses the same clock sources as its master. (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers. - -@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where + [..] + (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where I2Sx can be I2S2 or I2S3. - =============================================================================== ##### How to use this driver ##### =============================================================================== [..] - Three mode of operations are available within this driver : + Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -137,7 +137,7 @@ This subsection provides a set of functions allowing to manage the I2S data transfers. - (#) There is two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. @@ -156,7 +156,7 @@ (#) No-Blocking mode functions with DMA are : (++) HAL_I2S_TransmitReceive_DMA() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_I2S_TxCpltCallback() (++) HAL_I2S_RxCpltCallback() (++) HAL_I2S_ErrorCallback() @@ -167,7 +167,8 @@ /** * @brief Full-Duplex Transmit/Receive data in blocking mode. - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pTxData: a 16-bit pointer to the Transmit data buffer. * @param pRxData: a 16-bit pointer to the Receive data buffer. * @param Size: number of data sample to be sent: @@ -182,8 +183,8 @@ */ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint32_t timeout = 0; - uint32_t tmp1 = 0, tmp2 = 0; + uint32_t tickstart = 0; + uint32_t tmp1 = 0, tmp2 = 0; if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { @@ -246,14 +247,15 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p } hi2s->Instance->DR = (*pTxData++); - /* Wait until RXNE flag is set */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until RXNE flag is set */ while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Process Unlocked */ __HAL_UNLOCK(hi2s); @@ -292,14 +294,15 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p } while(hi2s->TxXferCount > 0) { - /* Wait until TXE flag is set */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until TXE flag is set */ while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Process Unlocked */ __HAL_UNLOCK(hi2s); @@ -338,7 +341,8 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p /** * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pTxData: a 16-bit pointer to the Transmit data buffer. * @param pRxData: a 16-bit pointer to the Receive data buffer. * @param Size: number of data sample to be sent: @@ -346,7 +350,6 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -464,7 +467,8 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t /** * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @param pTxData: a 16-bit pointer to the Transmit data buffer. * @param pRxData: a 16-bit pointer to the Receive data buffer. * @param Size: number of data sample to be sent: @@ -472,7 +476,6 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -621,7 +624,8 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ /** * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt - * @param hi2s: I2S handle + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module * @retval HAL status */ HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s) diff --git a/stmhal/hal/src/stm32f4xx_hal_irda.c b/stmhal/hal/src/stm32f4xx_hal_irda.c index e5f7dd0ff..2d58313f3 100644 --- a/stmhal/hal/src/stm32f4xx_hal_irda.c +++ b/stmhal/hal/src/stm32f4xx_hal_irda.c @@ -2,24 +2,24 @@ ****************************************************************************** * @file stm32f4xx_hal_irda.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA SIR ENDEC block (IrDA): - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - @verbatim + * + Initialization and de-initialization methods + * + IO operation methods + * + Peripheral Control methods + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - The IRDA HAL driver can be used as follow: + The IRDA HAL driver can be used as follows: (#) Declare a IRDA_HandleTypeDef handle structure. - (#) Initialize the IRDA low level resources by implement the HAL_IRDA_MspInit() API: + (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API: (##) Enable the USARTx interface clock. (##) IRDA pins configuration: (+++) Enable the clock for the IRDA GPIOs. @@ -47,7 +47,7 @@ RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - (#) Three mode of operations are available within this driver : + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -148,7 +148,9 @@ static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); @@ -175,18 +177,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible IRDA frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | IRDA frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ + please refer to Reference manual for possible IRDA frame formats. (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may not be rejected. The receiver set up time should be managed by software. The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and @@ -204,7 +195,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, /** * @brief Initializes the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and create the associated handle. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) @@ -261,7 +253,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /** * @brief DeInitializes the IRDA peripheral - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) @@ -292,7 +285,8 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /** * @brief IRDA MSP Init. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) @@ -304,7 +298,8 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /** * @brief IRDA MSP DeInit. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) @@ -333,33 +328,33 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. - (#) There are two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. + or DMA, These APIs return the HAL status. The end of the data processing will be indicated through the dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks will be executed respectivelly at the end of the transmit or Receive process - The HAL_IRDA_ErrorCallback()user callback will be executed when a communication error is detected + The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected (#) Blocking mode API's are : (++) HAL_IRDA_Transmit() (++) HAL_IRDA_Receive() - (#) Non-Blocking mode API's with Interrupt are : + (#) Non Blocking mode APIs with Interrupt are : (++) HAL_IRDA_Transmit_IT() (++) HAL_IRDA_Receive_IT() (++) HAL_IRDA_IRQHandler() - (#) No-Blocking mode functions with DMA are : + (#) Non Blocking mode functions with DMA are : (++) HAL_IRDA_Transmit_DMA() (++) HAL_IRDA_Receive_DMA() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_IRDA_TxCpltCallback() (++) HAL_IRDA_RxCpltCallback() (++) HAL_IRDA_ErrorCallback() @@ -370,7 +365,8 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /** * @brief Sends an amount of data in blocking mode. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Specify timeout value @@ -461,7 +457,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @param Timeout: Specify timeout value @@ -554,7 +551,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui /** * @brief Send an amount of data in non blocking mode. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -595,8 +593,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); + /* Enable the IRDA Transmit Data Register Empty Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); return HAL_OK; } @@ -608,7 +606,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /** * @brief Receives an amount of data in non blocking mode. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @retval HAL status @@ -663,7 +662,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /** * @brief Sends an amount of data in non blocking mode. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -701,6 +701,9 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /* Set the IRDA DMA transfert complete callback */ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; + /* Set the IRDA DMA half transfert complete callback */ + hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; + /* Set the DMA error callback */ hirda->hdmatx->XferErrorCallback = IRDA_DMAError; @@ -725,7 +728,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /** * @brief Receives an amount of data in non blocking mode. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit. @@ -762,6 +766,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Set the IRDA DMA transfert complete callback */ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; + /* Set the IRDA DMA half transfert complete callback */ + hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; + /* Set the DMA error callback */ hirda->hdmarx->XferErrorCallback = IRDA_DMAError; @@ -783,10 +790,117 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData return HAL_BUSY; } } + +/** + * @brief Pauses the DMA Transfer. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + /* Disable the UART DMA Tx request */ + hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + /* Disable the UART DMA Rx request */ + hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + } + else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + /* Disable the UART DMA Tx & Rx requests */ + hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + hirda->Instance->CR3 |= USART_CR3_DMAT; + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_IRDA_CLEAR_OREFLAG(hirda); + /* Enable the UART DMA Rx request */ + hirda->Instance->CR3 |= USART_CR3_DMAR; + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_IRDA_CLEAR_OREFLAG(hirda); + /* Enable the UART DMA Tx & Rx request */ + hirda->Instance->CR3 |= USART_CR3_DMAT; + hirda->Instance->CR3 |= USART_CR3_DMAR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ + + /* Disable the UART Tx/Rx DMA requests */ + hirda->Instance->CR3 &= ~USART_CR3_DMAT; + hirda->Instance->CR3 &= ~USART_CR3_DMAR; + + /* Abort the UART DMA tx Stream */ + if(hirda->hdmatx != NULL) + { + HAL_DMA_Abort(hirda->hdmatx); + } + /* Abort the UART DMA rx Stream */ + if(hirda->hdmarx != NULL) + { + HAL_DMA_Abort(hirda->hdmarx); + } + + hirda->State = HAL_IRDA_STATE_READY; + + return HAL_OK; +} /** * @brief This function handles IRDA interrupt request. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) @@ -795,37 +909,37 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE); tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE); - /* IRDA parity error interrupt occured -------------------------------------*/ + /* IRDA parity error interrupt occurred -------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_PE); + __HAL_IRDA_CLEAR_PEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_PE; } tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE); tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); - /* IRDA frame error interrupt occured --------------------------------------*/ + /* IRDA frame error interrupt occurred --------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_FE); + __HAL_IRDA_CLEAR_FEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_FE; } tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE); tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); - /* IRDA noise error interrupt occured --------------------------------------*/ + /* IRDA noise error interrupt occurred --------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_NE); + __HAL_IRDA_CLEAR_NEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_NE; } tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE); tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); - /* IRDA Over-Run interrupt occured -----------------------------------------*/ + /* IRDA Over-Run interrupt occurred -----------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_ORE); + __HAL_IRDA_CLEAR_OREFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; } @@ -843,22 +957,21 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) if((tmp1 != RESET) && (tmp2 != RESET)) { IRDA_Receive_IT(hirda); - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_IT_RXNE); } - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC); + tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE); + tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE); /* IRDA in mode Transmitter ------------------------------------------------*/ if((tmp1 != RESET) &&(tmp2 != RESET)) { IRDA_Transmit_IT(hirda); - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_IT_TC); } } /** * @brief Tx Transfer complete callbacks. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) @@ -868,21 +981,49 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) */ } +/** + * @brief Tx Half Transfer completed callbacks. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ + __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file + */ +} + /** * @brief Rx Transfer complete callbacks. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback could be implemented in the user file + the HAL_IRDA_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer complete callbacks. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file */ } /** * @brief IRDA error callbacks. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) @@ -905,9 +1046,9 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) ============================================================================== [..] This subsection provides a set of functions allowing to return the State of IrDA - communication process, return Peripheral Errors occured during communication process + communication process and also return Peripheral Errors occurred during communication process (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral. - (+) HAL_IRDA_GetError() check in run-time errors that could be occured durung communication. + (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication. @endverbatim * @{ @@ -915,7 +1056,8 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Returns the IRDA state. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL state */ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) @@ -946,32 +1088,57 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - hirda->TxXferCount = 0; - - /* Wait for IRDA TC Flag */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK) + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) { - /* Timeout Occured */ - hirda->State = HAL_IRDA_STATE_TIMEOUT; - HAL_IRDA_ErrorCallback(hirda); - } - else - { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + hirda->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the IRDA CR3 register */ + hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); + + /* Wait for IRDA TC Flag */ + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK) { - hirda->State = HAL_IRDA_STATE_BUSY_RX; + /* Timeout occurred */ + hirda->State = HAL_IRDA_STATE_TIMEOUT; + HAL_IRDA_ErrorCallback(hirda); } else { - hirda->State = HAL_IRDA_STATE_READY; + /* No Timeout */ + /* Check if a receive process is ongoing or not */ + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + HAL_IRDA_TxCpltCallback(hirda); } + } + /* DMA Circular mode */ + else + { HAL_IRDA_TxCpltCallback(hirda); } } +/** + * @brief DMA IRDA receive process half complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_IRDA_TxHalfCpltCallback(hirda); +} + /** * @brief DMA IRDA receive process complete callback. * @param hdma: DMA handle @@ -980,21 +1147,41 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + hirda->RxXferCount = 0; - hirda->RxXferCount = 0; - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the IRDA CR3 register */ + hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - + HAL_IRDA_RxCpltCallback(hirda); } +/** + * @brief DMA IRDA receive process half complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_IRDA_RxHalfCpltCallback(hirda); +} + /** * @brief DMA IRDA communication error callback. * @param hdma: DMA handle @@ -1014,7 +1201,8 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles IRDA Communication Timeout. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @param Flag: specifies the IRDA flag to check. * @param Status: The new Flag status (SET or RESET). * @param Timeout: Timeout duration @@ -1022,9 +1210,10 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait until flag is set */ if(Status == RESET) @@ -1034,7 +1223,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); @@ -1059,7 +1248,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); @@ -1082,7 +1271,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, /** * @brief Send an amount of data in non blocking mode. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) @@ -1093,9 +1283,6 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) tmp1 = hirda->State; if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX)) { - /* Process Locked */ - __HAL_LOCK(hirda); - if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { tmp = (uint16_t*) hirda->pTxBuffPtr; @@ -1116,8 +1303,8 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) if(--hirda->TxXferCount == 0) { - /* Disable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); + /* Disable the IRDA Transmit Data Register Empty Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) { @@ -1133,17 +1320,16 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) hirda->State = HAL_IRDA_STATE_READY; } - /* Call the Process Unlocked before calling the Tx call back API to give the possibiity to - start again the Transmission under the Tx call back API */ - __HAL_UNLOCK(hirda); - + /* Wait on TC flag to be able to start a second transfer */ + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } HAL_IRDA_TxCpltCallback(hirda); return HAL_OK; } - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - + return HAL_OK; } else @@ -1154,7 +1340,8 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) /** * @brief Receives an amount of data in non blocking mode. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) @@ -1165,9 +1352,6 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) tmp1 = hirda->State; if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX)) { - /* Process Locked */ - __HAL_LOCK(hirda); - if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { tmp = (uint16_t*) hirda->pRxBuffPtr; @@ -1196,9 +1380,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) if(--hirda->RxXferCount == 0) { - while(HAL_IS_BIT_SET(hirda->Instance->SR, IRDA_FLAG_RXNE)) - { - } + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) @@ -1215,18 +1397,10 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) hirda->State = HAL_IRDA_STATE_READY; } - /* Call the Process Unlocked before calling the Rx call back API to give the possibiity to - start again the receiption under the Rx call back API */ - __HAL_UNLOCK(hirda); - HAL_IRDA_RxCpltCallback(hirda); return HAL_OK; } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - return HAL_OK; } else @@ -1237,7 +1411,8 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) /** * @brief Configures the IRDA peripheral. - * @param hirda: IRDA handle + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) diff --git a/stmhal/hal/src/stm32f4xx_hal_iwdg.c b/stmhal/hal/src/stm32f4xx_hal_iwdg.c index c76acedf4..2fdd73b3e 100644 --- a/stmhal/hal/src/stm32f4xx_hal_iwdg.c +++ b/stmhal/hal/src/stm32f4xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: @@ -43,13 +43,28 @@ ##### How to use this driver ##### ============================================================================== + [..] + If Window option is disabled + (+) Use IWDG using HAL_IWDG_Init() function to : + (++) Enable write access to IWDG_PR, IWDG_RLR. + (++) Configure the IWDG prescaler, counter reload value. + This reload value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. [..] (+) Use IWDG using HAL_IWDG_Start() function to: - (++) Enable write access to IWDG_PR and IWDG_RLR registers. - (++) Configure the IWDG prescaler and counter reload values. (++) Reload IWDG counter with value defined in the IWDG_RLR register. (++) Start the IWDG, when the IWDG is used in software mode (no need to enable the LSI, it will be enabled by hardware). + (+) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. + [..] + if Window option is enabled: + + (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter + (+) Use IWDG using HAL_IWDG_Init() function to : + (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + (++) Configure the IWDG prescaler, reload value and window value. (+) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using HAL_IWDG_Refresh() function. @@ -64,8 +79,7 @@ (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status - (+) __HAL_IWDG_CLEAR_FLAG: Clear the IWDG's pending flags - + @endverbatim ****************************************************************************** * @attention @@ -113,6 +127,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define IWDG_TIMEOUT_FLAG ((uint32_t)1000) /* 1 s */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -142,13 +157,12 @@ /** * @brief Initializes the IWDG according to the specified * parameters in the IWDG_InitTypeDef and creates the associated handle. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { - uint32_t tmp; - /* Check the IWDG handle allocation */ if(hiwdg == NULL) { @@ -156,6 +170,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) } /* Check the parameters */ + assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); @@ -168,34 +183,12 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_BUSY; - /* Set IWDG counter clock prescaler */ - /* Get the PR register value */ - tmp = hiwdg->Instance->PR; - - /* Clear PR[2:0] bits */ - tmp &= ((uint32_t)~(IWDG_PR_PR)); - - /* Prepare the IWDG Prescaler parameter */ - tmp |= hiwdg->Init.Prescaler; - /* Enable write access to IWDG_PR and IWDG_RLR registers */ __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg); - /* Write to IWDG PR */ - hiwdg->Instance->PR = tmp; - - /* Set IWDG counter reload value */ - /* Get the RLR register value */ - tmp = hiwdg->Instance->RLR; - - /* Clear RL[11:0] bits */ - tmp &= ((uint32_t)~(IWDG_RLR_RL)); - - /* Prepare the IWDG Prescaler parameter */ - tmp |= hiwdg->Init.Reload; - - /* Write to IWDG RLR */ - hiwdg->Instance->RLR = tmp; + /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ + MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler); + MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload); /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_READY; @@ -206,7 +199,8 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /** * @brief Initializes the IWDG MSP. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval None */ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) @@ -237,7 +231,8 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) /** * @brief Starts the IWDG. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) @@ -266,19 +261,36 @@ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) /** * @brief Refreshes the IWDG. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { + uint32_t tickstart = 0; + /* Process Locked */ - __HAL_LOCK(hiwdg); - + __HAL_LOCK(hiwdg); + /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_BUSY; - - /* Clear the RVU flag */ - __HAL_IWDG_CLEAR_FLAG(hiwdg, IWDG_FLAG_RVU); + + tickstart = HAL_GetTick(); + + /* Wait until RVU flag is RESET */ + while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) + { + if((HAL_GetTick() - tickstart ) > IWDG_TIMEOUT_FLAG) + { + /* Set IWDG state */ + hiwdg->State = HAL_IWDG_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hiwdg); + + return HAL_TIMEOUT; + } + } /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); @@ -314,7 +326,8 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) /** * @brief Returns the IWDG state. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL state */ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) diff --git a/stmhal/hal/src/stm32f4xx_hal_ltdc.c b/stmhal/hal/src/stm32f4xx_hal_ltdc.c index 307b42897..71176f98e 100644 --- a/stmhal/hal/src/stm32f4xx_hal_ltdc.c +++ b/stmhal/hal/src/stm32f4xx_hal_ltdc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief LTDC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral: @@ -13,16 +13,16 @@ * + Peripheral State and Errors functions * @verbatim - ============================================================================== + ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - (#) Program the required configuration through following parameters: + (#) Program the required configuration through the following parameters: the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity, Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function - (#) Program the required configuration through following parameters: + (#) Program the required configuration through the following parameters: the pixel format, the blending factors, input alpha value, the window size and the image size using HAL_LTDC_ConfigLayer() function for foreground or/and background layer. @@ -38,7 +38,7 @@ (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineInterrupt() function - (#) If needed, Reconfigure and change the pixel format value, the alpha value + (#) If needed, reconfigure and change the pixel format value, the alpha value value, the window size, the window position and the layer start address for foreground or/and background layer using respectively the following functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), @@ -57,10 +57,10 @@ (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer. (+) __HAL_LTDC_RELOAD_CONFIG: Reload Layer Configuration. (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. - (+) __HAL_LTDC_CLEAR_FLAG: Clears the LTDC pending flags. - (+) __HAL_LTDC_ENABLE_IT: Enables the specified LTDC interrupts. - (+) __HAL_LTDC_DISABLE_IT: Disables the specified LTDC interrupts. - (+) __HAL_LTDC_GET_IT_SOURCE: Checks whether the specified LTDC interrupt has occurred or not. + (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. + (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. [..] (@) You can refer to the LTDC HAL driver header file for more useful macros @@ -421,9 +421,9 @@ __weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc) (+) Enable / Disable the C-LUT. (+) Update the layer position. (+) Update the layer size. - (+) update pixel format on the fly the. - (+) update transparency on the fly the. - (+) update address on the fly. + (+) Update pixel format on the fly. + (+) Update transparency on the fly. + (+) Update address on the fly. @endverbatim * @{ @@ -436,7 +436,7 @@ __weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains * the configuration information for the Layer. - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -485,10 +485,10 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgT * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param RGBValue: the color key value - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) { @@ -523,10 +523,10 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * the configuration information for the LTDC. * @param pCLUT: pointer to the color lookup table address. * @param CLUTSize: the color lookup table size. - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) { @@ -566,10 +566,10 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT * @brief Enable the color keying. * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) { @@ -601,10 +601,10 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * @brief Disable the color keying. * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) { @@ -636,10 +636,10 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_ * @brief Enable the color lookup table. * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) { @@ -672,10 +672,10 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerI * @brief Disable the color lookup table. * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) { @@ -708,7 +708,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer * @brief Enables Dither. * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) @@ -735,7 +735,7 @@ HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) * @brief Disables Dither. * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) @@ -764,10 +764,10 @@ HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @param XSize: LTDC Pixel per line * @param YSize: LTDC Line number - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) { @@ -826,10 +826,10 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi * the configuration information for the LTDC. * @param X0: LTDC window X offset * @param Y0: LTDC window Y offset - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) { @@ -882,7 +882,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) { @@ -924,10 +924,10 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pi * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param Alpha: new alpha value. - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) { @@ -971,7 +971,7 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: * 0 or 1. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) { @@ -1012,7 +1012,7 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param Line: Line Interrupt Position. - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) { @@ -1091,7 +1091,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) * @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param pLayerCfg: Pointer LTDC Layer Configuration strusture - * @param LayerIdx: LTDC Layer index + * @param LayerIdx: LTDC Layer index. * This parameter can be one of the following values: 0 or 1 * @retval None */ diff --git a/stmhal/hal/src/stm32f4xx_hal_msp_template.c b/stmhal/hal/src/stm32f4xx_hal_msp_template.c index eee9d0ce9..4b9950dd6 100644 --- a/stmhal/hal/src/stm32f4xx_hal_msp_template.c +++ b/stmhal/hal/src/stm32f4xx_hal_msp_template.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_msp_template.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief HAL MSP module. * This file template is located in the HAL folder and should be copied * to the user folder. diff --git a/stmhal/hal/src/stm32f4xx_hal_nand.c b/stmhal/hal/src/stm32f4xx_hal_nand.c index 7b7ac85e1..35661931e 100644 --- a/stmhal/hal/src/stm32f4xx_hal_nand.c +++ b/stmhal/hal/src/stm32f4xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_nand.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -125,7 +125,8 @@ /** * @brief Perform NAND memory Initialization sequence - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param ComSpace_Timing: pointer to Common space timing structure * @param AttSpace_Timing: pointer to Attribute space timing structure * @retval HAL status @@ -164,7 +165,8 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT /** * @brief Perform NAND memory De-Initialization sequence - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) @@ -186,7 +188,8 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) /** * @brief NAND MSP Init - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval None */ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) @@ -198,7 +201,8 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) /** * @brief NAND MSP DeInit - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval None */ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) @@ -211,7 +215,8 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) /** * @brief This function handles NAND device interrupt request. - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval HAL status */ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) @@ -260,7 +265,8 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) /** * @brief NAND interrupt feature callback - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval None */ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) @@ -291,7 +297,8 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) /** * @brief Read the NAND memory electronic signature - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param pNAND_ID: NAND ID structure * @retval HAL status */ @@ -323,17 +330,17 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN hnand->State = HAL_NAND_STATE_BUSY; /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x90; + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; /* Read the electronic signature from NAND flash */ data = *(__IO uint32_t *)deviceAddress; /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1st_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2nd_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3rd_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4th_CYCLE(data); + pNAND_ID->Maker_Id = __ADDR_1st_CYCLE(data); + pNAND_ID->Device_Id = __ADDR_2nd_CYCLE(data); + pNAND_ID->Third_Id = __ADDR_3rd_CYCLE(data); + pNAND_ID->Fourth_Id = __ADDR_4th_CYCLE(data); /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -346,7 +353,8 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN /** * @brief NAND memory reset - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) @@ -392,7 +400,8 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) /** * @brief Read Page(s) from NAND memory block - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @param pBuffer : pointer to destination read buffer * @param NumPageToRead : number of pages to read from block @@ -401,7 +410,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) { __IO uint32_t index = 0; - uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; + uint32_t deviceAddress = 0, numPagesRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS; /* Process Locked */ __HAL_LOCK(hnand); @@ -425,33 +434,30 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) read loop */ - while((NumPageToRead != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.PageSize))) + /* Page(s) read loop */ + while((NumPageToRead != 0) && (addressStatus == NAND_VALID_ADDRESS)) { - /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead); + /* NAND raw address calculation */ + nandAddress = __ARRAY_ADDRESS(pAddress, hnand); /* Send read page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress); /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + if(hnand->Info.BlockNbr > 1024) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x30; + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; /* Get Data into Buffer */ - for(; index < size; index++) + for(index = 0 ; index < hnand->Info.PageSize; index++) { *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; } @@ -463,7 +469,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType NumPageToRead--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); + HAL_NAND_Address_Inc(hnand, pAddress); } @@ -479,7 +485,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType /** * @brief Write Page(s) to NAND memory block - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @param pBuffer : pointer to source buffer to write * @param NumPageToWrite : number of pages to write to block @@ -487,9 +494,9 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType */ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) { - __IO uint32_t index = 0; - uint32_t timeout = 0; - uint32_t deviceAddress = 0, size = 0 , numPagesWritten = 0, nandAddress = 0; + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0 , numPagesWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS; /* Process Locked */ __HAL_LOCK(hnand); @@ -513,45 +520,42 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - /* Page(s) write loop */ - while((NumPageToWrite != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.PageSize))) + while((NumPageToWrite != 0) && (addressStatus == NAND_VALID_ADDRESS)) { - /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten); + /* NAND raw address calculation */ + nandAddress = __ARRAY_ADDRESS(pAddress, hnand); /* Send write page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x80; + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress); /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + if(hnand->Info.BlockNbr > 1024) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress); } /* Write data to memory */ - for(; index < size; index++) + for(index = 0 ; index < hnand->Info.PageSize; index++) { *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x10; + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { - /* Check for timeout value */ - timeout = HAL_GetTick() + NAND_WRITE_TIMEOUT; + /* Get tick */ + tickstart = HAL_GetTick(); - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; } @@ -564,7 +568,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp NumPageToWrite--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); + HAL_NAND_Address_Inc(hnand, pAddress); } @@ -580,7 +584,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp /** * @brief Read Spare area(s) from NAND memory - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @param pBuffer: pointer to source buffer to write * @param NumSpareAreaToRead: Number of spare area to read @@ -589,7 +594,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { __IO uint32_t index = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; + uint32_t deviceAddress = 0, numSpareAreaRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS; /* Process Locked */ __HAL_LOCK(hnand); @@ -611,36 +616,32 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres } /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + hnand->State = HAL_NAND_STATE_BUSY; /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize))) - { - - /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numSpareAreaRead); - + while((NumSpareAreaToRead != 0) && (addressStatus == NAND_VALID_ADDRESS)) + { + /* NAND raw address calculation */ + nandAddress = __ARRAY_ADDRESS(pAddress, hnand); + /* Send read spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress); /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + if(hnand->Info.BlockNbr > 1024) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x30; + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; /* Get Data into Buffer */ - for ( ;index < size; index++) + for(index = 0 ; index < hnand->Info.SpareAreaSize; index++) { *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; } @@ -652,7 +653,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres NumSpareAreaToRead--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize)); + HAL_NAND_Address_Inc(hnand, pAddress); } /* Update the NAND controller state */ @@ -666,7 +667,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres /** * @brief Write Spare area(s) to NAND memory - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @param pBuffer : pointer to source buffer to write * @param NumSpareAreaTowrite : number of spare areas to write to block @@ -675,8 +677,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { __IO uint32_t index = 0; - uint32_t timeout = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, numSpareAreaWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS; /* Process Locked */ __HAL_LOCK(hnand); @@ -698,48 +700,45 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre } /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + hnand->State = HAL_NAND_STATE_BUSY; /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize))) + while((NumSpareAreaTowrite != 0) && (addressStatus == NAND_VALID_ADDRESS)) { - /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numSpareAreaWritten); - + /* NAND raw address calculation */ + nandAddress = __ARRAY_ADDRESS(pAddress, hnand); + /* Send write Spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x80; + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress); } /* Write data to memory */ - for(; index < size; index++) + for(index = 0 ; index < hnand->Info.SpareAreaSize; index++) { *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x10; + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { - /* Check for timeout value */ - timeout = HAL_GetTick() + NAND_WRITE_TIMEOUT; + /* Get tick */ + tickstart = HAL_GetTick(); - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; } @@ -752,7 +751,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre NumSpareAreaTowrite--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize)); + HAL_NAND_Address_Inc(hnand, pAddress); } @@ -767,7 +766,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre /** * @brief NAND memory Block erase - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @retval HAL status */ @@ -798,19 +798,19 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy hnand->State = HAL_NAND_STATE_BUSY; /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0x60; + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(__ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand)); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(__ARRAY_ADDRESS(pAddress, hnand)); } - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0xD0; + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -824,7 +824,8 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy /** * @brief NAND memory read status - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval NAND status */ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) @@ -843,7 +844,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) } /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0x70; + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; /* Read status register data */ data = *(__IO uint8_t *)DeviceAddress; @@ -864,7 +865,8 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) /** * @brief Increment the NAND memory address - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param pAddress: pointer to NAND adress structure * @retval The new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address @@ -921,7 +923,8 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pA /** * @brief Enables dynamically NAND ECC feature. - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) @@ -947,7 +950,8 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) @@ -972,7 +976,8 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) /** * @brief Disables dynamically NAND ECC feature. - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @param ECCval: pointer to ECC value * @param Timeout: maximum timeout to wait * @retval HAL status @@ -1012,7 +1017,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, ##### NAND State functions ##### ============================================================================== [..] - This subsection permit to get in run-time the status of the NAND controller + This subsection permits to get in run-time the status of the NAND controller and the data flow. @endverbatim @@ -1021,7 +1026,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** * @brief return the NAND state - * @param hnand: pointer to NAND handle + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. * @retval HAL state */ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) diff --git a/stmhal/hal/src/stm32f4xx_hal_nor.c b/stmhal/hal/src/stm32f4xx_hal_nor.c index 3d36b3d3e..1b2bc49ca 100644 --- a/stmhal/hal/src/stm32f4xx_hal_nor.c +++ b/stmhal/hal/src/stm32f4xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_nor.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -126,7 +126,7 @@ /** * @brief Perform the NOR memory Initialization sequence - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @param Timing: pointer to NOR control timing structure * @param ExtTiming: pointer to NOR extended mode timing structure * @retval HAL status @@ -165,7 +165,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /** * @brief Perform NOR memory De-Initialization sequence - * @param hnor: pointer to NOR handle + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) @@ -187,7 +188,8 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) /** * @brief NOR MSP Init - * @param hnor: pointer to NOR handle + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. * @retval None */ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) @@ -199,7 +201,8 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) /** * @brief NOR MSP DeInit - * @param hnor: pointer to NOR handle + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. * @retval None */ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) @@ -211,7 +214,8 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) /** * @brief NOR BSP Wait fro Ready/Busy signal - * @param hnor: pointer to NOR handle + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. * @param Timeout: Maximum timeout value * @retval None */ @@ -242,12 +246,14 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) /** * @brief Read NOR flash IDs - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @param pNOR_ID : pointer to NOR ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) { + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -256,20 +262,38 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send read ID command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0090); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090); /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE3_ADDR); + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -282,11 +306,13 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /** * @brief Returns the NOR memory to Read mode. - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -296,7 +322,25 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) return HAL_BUSY; } - __NOR_WRITE(NOR_MEMORY_ADRESS, 0x00F0); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } + + __NOR_WRITE(deviceAddress, 0x00F0); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -309,13 +353,15 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) /** * @brief Read data from NOR memory - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @param pAddress: pointer to Device address * @param pData : pointer to read data * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -324,14 +370,32 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send read data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(0x00555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x002AA), 0x0055); - __NOR_WRITE(*pAddress, 0x00F0); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055); + __NOR_WRITE(pAddress, 0x00F0); /* Read the data */ *pData = *(__IO uint32_t *)pAddress; @@ -347,13 +411,15 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /** * @brief Program data to NOR memory - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @param pAddress: Device address * @param pData : pointer to the data to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -362,14 +428,32 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send program data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00A0); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0); /* Write the data */ __NOR_WRITE(pAddress, *pData); @@ -384,8 +468,8 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u } /** - * @brief Reads a block of data from the FMC NOR memory. - * @param hnor: pointer to NOR handle + * @brief Reads a half-word buffer from the NOR memory. + * @param hnor: pointer to the NOR handle * @param uwAddress: NOR memory internal address to read from. * @param pData: pointer to the buffer that receives the data read from the * NOR memory. @@ -394,6 +478,8 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u */ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -402,13 +488,31 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send read data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(0x00555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x002AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055); __NOR_WRITE(uwAddress, 0x00F0); /* Read buffer */ @@ -429,12 +533,12 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress } /** - * @brief Writes a half-word buffer to the FMC NOR memory. This function - * must be used only with S29GL128P NOR memory. - * @param hnor: pointer to NOR handle - * @param uwAddress: NOR memory internal address from which the data + * @brief Writes a half-word buffer to the NOR memory. This function must be used + only with S29GL128P NOR memory. + * @param hnor: pointer to the NOR handle + * @param uwAddress: NOR memory internal start write address * @param pData: pointer to source data buffer. - * @param uwBufferSize: number of Half words to write. The maximum allowed + * @param uwBufferSize: Size of the buffer to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) @@ -442,7 +546,8 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr uint32_t lastloadedaddress = 0; uint32_t currentaddress = 0; uint32_t endaddress = 0; - + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -451,6 +556,24 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; @@ -461,12 +584,12 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr lastloadedaddress = uwAddress; /* Issue unlock command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); /* Write Buffer Load Command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwAddress), 0x25); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwAddress), (uwBufferSize - 1)); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1)); /* Load Data into NOR Buffer */ while(currentaddress <= endaddress) @@ -474,12 +597,12 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /* Store last loaded address & data value (for polling) */ lastloadedaddress = currentaddress; - __NOR_WRITE(__NOR_ADDR_SHIFT(currentaddress), *pData++); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++); currentaddress += 1; } - __NOR_WRITE(__NOR_ADDR_SHIFT(lastloadedaddress), 0x29); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -493,13 +616,15 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /** * @brief Erase the specified block of the NOR memory - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @param BlockAddress : Block to erase address * @param Address: Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -508,16 +633,34 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send block erase command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0080); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30); /* Check the NOR memory status and update the controller state */ @@ -532,12 +675,14 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /** * @brief Erase the entire NOR chip. - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @param Address : Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -546,17 +691,35 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send NOR chip erase command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0080); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0010); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010); /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -569,12 +732,14 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /** * @brief Read NOR flash CFI IDs - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @param pNOR_CFI : pointer to NOR CFI IDs structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) { + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -583,18 +748,36 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceAddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceAddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send read CFI query command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(0x0055), 0x0098); + __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098); /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI4_ADDRESS); + pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -626,7 +809,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR /** * @brief Enables dynamically NOR write operation. - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) @@ -648,7 +831,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) /** * @brief Disables dynamically NOR write operation. - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) @@ -683,7 +866,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) ##### NOR State functions ##### ============================================================================== [..] - This subsection permit to get in run-time the status of the NOR controller + This subsection permits to get in run-time the status of the NOR controller and the data flow. @endverbatim @@ -692,7 +875,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) /** * @brief return the NOR controller state - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @retval NOR controller state */ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) @@ -702,7 +885,7 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) /** * @brief Returns the NOR operation status. - * @param hnor: pointer to NOR handle + * @param hnor: pointer to the NOR handle * @param Address: Device address * @param Timeout: NOR progamming Timeout * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR @@ -712,22 +895,25 @@ NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, u { NOR_StatusTypedef status = NOR_ONGOING; uint16_t tmpSR1 = 0, tmpSR2 = 0; - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ - HAL_NOR_MspWait(hnor, timeout); + HAL_NOR_MspWait(hnor, Timeout); /* Get the NOR memory operation status -------------------------------------*/ while(status != NOR_SUCCESS) { - /* Check for timeout value */ - timeout = HAL_GetTick() + Timeout; - - if(HAL_GetTick() >= timeout) + /* Get tick */ + tickstart = HAL_GetTick(); + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - status = NOR_TIMEOUT; - } - + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + status = NOR_TIMEOUT; + } + } + /* Read NOR status register (DQ6 and DQ5) */ tmpSR1 = *(__IO uint16_t *)Address; tmpSR2 = *(__IO uint16_t *)Address; diff --git a/stmhal/hal/src/stm32f4xx_hal_pccard.c b/stmhal/hal/src/stm32f4xx_hal_pccard.c index e667e9551..364e06288 100644 --- a/stmhal/hal/src/stm32f4xx_hal_pccard.c +++ b/stmhal/hal/src/stm32f4xx_hal_pccard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pccard.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief PCCARD HAL module driver. * This file provides a generic firmware to drive PCCARD memories mounted * as external device. @@ -116,7 +116,8 @@ /** * @brief Perform the PCCARD memory Initialization sequence - * @param hpccard : pointer to PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @param ComSpaceTiming: Common space timing structure * @param AttSpaceTiming: Attribute space timing structure * @param IOSpaceTiming: IO space timing structure @@ -163,7 +164,8 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti /** * @brief Perform the PCCARD memory De-initialization sequence - * @param hpccard : pointer to PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard) @@ -185,7 +187,8 @@ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard) /** * @brief PCCARD MSP Init - * @param hpccard : pointer to PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @retval None */ __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard) @@ -197,7 +200,8 @@ __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard) /** * @brief PCCARD MSP DeInit - * @param hpccard : pointer to PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @retval None */ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard) @@ -227,8 +231,9 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard) /** * @brief Read Compact Flash's ID. - * @param hpccard : pointer to PCCARD handle - * @param CF_ID: Compact flash ID structure. + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. + * @param CompactFlash_ID: Compact flash ID structure. * @param pStatus: pointer to compact flash status * @retval HAL status * @@ -289,10 +294,11 @@ HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactF /** * @brief Read sector from PCCARD memory - * @param hpccard : pointer to PCCARD handle - * @param pBuffer : pointer to destination read buffer - * @param SectorAddress : Sector address to read - * @param pStatus : pointer to CF status + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to destination read buffer + * @param SectorAddress: Sector address to read + * @param pStatus: pointer to CF status * @retval HAL status */ HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) @@ -364,10 +370,11 @@ HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pB /** * @brief Write sector to PCCARD memory - * @param hpccard : pointer to PCCARD handle - * @param pBuffer : pointer to source write buffer - * @param SectorAddress : Sector address to write - * @param pStatus : pointer to CF status + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to source write buffer + * @param SectorAddress: Sector address to write + * @param pStatus: pointer to CF status * @retval HAL status */ HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) @@ -437,9 +444,10 @@ HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *p /** * @brief Erase sector from PCCARD memory - * @param hpccard : pointer to PCCARD handle - * @param SectorAddress : Sector address to erase - * @param pStatus : pointer to CF status + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. + * @param SectorAddress: Sector address to erase + * @param pStatus: pointer to CF status * @retval HAL status */ HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus) @@ -495,7 +503,8 @@ HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t S /** * @brief Reset the PCCARD memory - * @param hpccard : pointer to PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard) @@ -533,7 +542,8 @@ HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard) /** * @brief This function handles PCCARD device interrupt request. - * @param hpccard : pointer to PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @retval HAL status */ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) @@ -582,7 +592,8 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) /** * @brief PCCARD interrupt feature callback - * @param hpccard : pointer to PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @retval None */ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard) @@ -604,7 +615,7 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard) ##### PCCARD State functions ##### ============================================================================== [..] - This subsection permit to get in run-time the status of the PCCARD controller + This subsection permits to get in run-time the status of the PCCARD controller and the data flow. @endverbatim @@ -613,8 +624,9 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard) /** * @brief return the PCCARD controller state - * @param hpccard : pointer to PCCARD handle - * @retval PCCARD controller state + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. + * @retval HAL state */ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard) { @@ -623,7 +635,8 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard) /** * @brief Get the compact flash memory status - * @param hpccard: PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @retval New status of the CF operation. This parameter can be: * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate * a Timeout error @@ -659,7 +672,8 @@ CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard) /** * @brief Reads the Compact Flash memory status using the Read status command - * @param hpccard : pointer to PCCARD handle + * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * the configuration information for PCCARD module. * @retval The status of the Compact Flash memory. This parameter can be: * - CompactFlash_BUSY: when memory is busy * - CompactFlash_READY: when memory is ready for the next operation diff --git a/stmhal/hal/src/stm32f4xx_hal_pcd.c b/stmhal/hal/src/stm32f4xx_hal_pcd.c index d35e38cb2..d4d506bfe 100644 --- a/stmhal/hal/src/stm32f4xx_hal_pcd.c +++ b/stmhal/hal/src/stm32f4xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -132,7 +132,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - hpcd->State = PCD_BUSY; + hpcd->State = HAL_PCD_STATE_BUSY; /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); @@ -177,7 +177,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Init Device */ USB_DevInit(hpcd->Instance, hpcd->Init); - hpcd->State= PCD_READY; + hpcd->State= HAL_PCD_STATE_READY; USB_DevDisconnect (hpcd->Instance); return HAL_OK; @@ -196,7 +196,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) return HAL_ERROR; } - hpcd->State = PCD_BUSY; + hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ HAL_PCD_Stop(hpcd); @@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) /* DeInit the low level hardware */ HAL_PCD_MspDeInit(hpcd); - hpcd->State = PCD_READY; + hpcd->State = HAL_PCD_STATE_RESET; return HAL_OK; } @@ -297,18 +297,18 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) { /* avoid spurious interrupt */ - if(__HAL_IS_INVALID_INTERRUPT(hpcd)) + if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) { return; } - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { epnum = 0; @@ -359,7 +359,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } } - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); @@ -375,7 +375,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { fifoemptymsk = 0x1 << epnum; - USBx_DEVICE->DIEPEMPMSK = ~fifoemptymsk; + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); @@ -423,18 +423,18 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /* Handle Resume Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; HAL_PCD_ResumeCallback(hpcd); - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); } /* Handle Suspend Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) { if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) @@ -442,13 +442,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) HAL_PCD_SuspendCallback(hpcd); } - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } /* Handle Reset Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; USB_FlushTxFifo(hpcd->Instance , 0 ); @@ -478,11 +478,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* setup EP0 to receive SETUP packets */ USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); } /* Handle Enumeration done Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) { USB_ActivateSetup(hpcd->Instance); hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; @@ -502,12 +502,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) HAL_PCD_ResetCallback(hpcd); - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } /* Handle RxQLevel Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); temp = USBx->GRXSTSP; @@ -531,35 +531,35 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /* Handle SOF Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) { HAL_PCD_SOFCallback(hpcd); - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } /* Handle Incomplete ISO IN Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } /* Handle Incomplete ISO OUT Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } /* Handle Connection event Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) { HAL_PCD_ConnectCallback(hpcd); - __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); } /* Handle Disconnection event Interrupt */ - if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { temp = hpcd->Instance->GOTGINT; @@ -597,7 +597,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /** * @brief Setup stage callback - * @param hpcd: ppp handle + * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -694,7 +694,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Disconnection event callbacks - * @param hpcd: ppp handle + * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -726,8 +726,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Send an amount of data in blocking mode * @param hpcd: PCD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) @@ -741,8 +739,6 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) /** * @brief Send an amount of data in blocking mode * @param hpcd: PCD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) @@ -1022,68 +1018,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) return HAL_OK; } -/** - * @brief Update FIFO configuration - * @param hpcd: PCD handle - * @retval status - */ -HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) -{ - uint8_t i = 0; - uint32_t Tx_Offset = 0; - - - /* TXn min size = 16 words. (n : Transmit FIFO index) - * When a TxFIFO is not used, the Configuration should be as follows: - * case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) - * --> Txm can use the space allocated for Txn. - * case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) - * --> Txn should be configured with the minimum space of 16 words - * The FIFO is used optimally when used TxFIFOs are allocated in the top - * of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. - * When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - - Tx_Offset = hpcd->Instance->GRXFSIZ; - - if(fifo == 0) - { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; - } - else - { - Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (i = 0; i < (fifo - 1); i++) - { - Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); - } - - /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; - - } - - return HAL_OK; -} - - -/** - * @brief Update FIFO configuration - * @param hpcd: PCD handle - * @retval status - */ -HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) -{ - - hpcd->Instance->GRXFSIZ = size; - - return HAL_OK; -} - - /** * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling * @param hpcd: PCD handle - * @retval status + * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) { @@ -1100,7 +1038,7 @@ HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling * @param hpcd: PCD handle - * @retval status + * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) { @@ -1122,7 +1060,7 @@ HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1131,7 +1069,7 @@ HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief Return the PCD state - * @param hpcd : PCD handle + * @param hpcd: PCD handle * @retval HAL state */ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) @@ -1146,7 +1084,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) * @brief DCD_WriteEmptyTxFifo * check FIFO for the next packet to be loaded * @param hpcd: PCD handle - * @retval status + * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { diff --git a/stmhal/hal/src/stm32f4xx_hal_pcd_ex.c b/stmhal/hal/src/stm32f4xx_hal_pcd_ex.c new file mode 100644 index 000000000..1a7fdc00f --- /dev/null +++ b/stmhal/hal/src/stm32f4xx_hal_pcd_ex.c @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pcd_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-June-2014 + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PCDEx_Private_Functions + * @{ + */ + + +/** @defgroup PCDEx_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update FIFO configuration + +@endverbatim + * @{ + */ + +/** + * @brief Update FIFO configuration + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i = 0; + uint32_t Tx_Offset = 0; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if(fifo == 0) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0; i < (fifo - 1); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; + + } + + return HAL_OK; +} + +/** + * @brief Update FIFO configuration + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PCD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stmhal/hal/src/stm32f4xx_hal_pwr.c b/stmhal/hal/src/stm32f4xx_hal_pwr.c index a834cf736..6f9d91b2f 100644 --- a/stmhal/hal/src/stm32f4xx_hal_pwr.c +++ b/stmhal/hal/src/stm32f4xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -276,6 +276,9 @@ void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) { __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD); } + /* Clear the edge trigger for the EXTI Line 16 (PVD) */ + EXTI->RTSR &= ~EXTI_RTSR_TR16; + EXTI->FTSR &= ~EXTI_FTSR_TR16; /* Configure the rising edge */ if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\ (sConfigPVD->Mode == PWR_MODE_IT_RISING)) @@ -312,7 +315,7 @@ void HAL_PWR_DisablePVD(void) /** * @brief Enables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable + * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @retval None @@ -326,7 +329,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) /** * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable + * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @retval None @@ -363,10 +366,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Disable SysTick Timer */ - SysTick->CTRL &= 0xFE; - + /* Select SLEEP mode entry -------------------------------------------------*/ if(SLEEPEntry == PWR_SLEEPENTRY_WFI) { @@ -376,11 +376,10 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) else { /* Request Wait For Event */ + __SEV(); + __WFE(); __WFE(); } - - /* Enable SysTick Timer */ - SysTick->CTRL |= 0x01; } /** @@ -452,9 +451,6 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) */ void HAL_PWR_EnterSTANDBYMode(void) { - /* Clear Wakeup flag */ - PWR->CR |= PWR_CR_CWUF; - /* Select Standby mode */ PWR->CR |= PWR_CR_PDDS; @@ -490,8 +486,8 @@ void HAL_PWR_PVD_IRQHandler(void) /** * @brief PWR PVD interrupt callback - * @param none - * @retval none + * @param None + * @retval None */ __weak void HAL_PWR_PVDCallback(void) { diff --git a/stmhal/hal/src/stm32f4xx_hal_pwr_ex.c b/stmhal/hal/src/stm32f4xx_hal_pwr_ex.c index 955214885..5cadf1dc5 100644 --- a/stmhal/hal/src/stm32f4xx_hal_pwr_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -56,6 +56,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 +#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 #define PWR_BKPREG_TIMEOUT_VALUE 1000 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -152,16 +153,17 @@ */ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) { - uint32_t timeout = 0; + uint32_t tickstart = 0; *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; - /* Get timeout */ - timeout = HAL_GetTick() + PWR_BKPREG_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till Backup regulator ready flag is set */ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -172,20 +174,21 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) /** * @brief Disables the Backup Regulator. * @param None - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) { - uint32_t timeout = 0; + uint32_t tickstart = 0; *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; - /* Get timeout */ - timeout = HAL_GetTick() + PWR_BKPREG_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till Backup regulator ready flag is set */ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -213,10 +216,57 @@ void HAL_PWREx_DisableFlashPowerDown(void) *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; } +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +/** + * @brief Enables Main Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * @param None + * @retval None + */ +void HAL_PWREx_EnableMainRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables Main Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * @param None + * @retval None + */ +void HAL_PWREx_DisableMainRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables Low Power Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * @param None + * @retval None + */ +void HAL_PWREx_EnableLowRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables Low Power Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * @param None + * @retval None + */ +void HAL_PWREx_DisableLowRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; +} + +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** * @brief Activates the Over-Drive mode. - * @note These macros can be used only for STM32F42xx/STM32F43xx devices. + * @note This function can be used only for STM32F42xx/STM32F43xx devices. * This mode allows the CPU and the core logic to operate at a higher frequency * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). * @note It is recommended to enter or exit Over-drive mode when the application is not running @@ -228,18 +278,19 @@ void HAL_PWREx_DisableFlashPowerDown(void) */ HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void) { - uint32_t timeout = 0; - + uint32_t tickstart = 0; + __PWR_CLK_ENABLE(); /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ __HAL_PWR_OVERDRIVE_ENABLE(); - - /* Get timeout */ - timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -247,12 +298,13 @@ HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void) /* Enable the Over-drive switch */ __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); - - /* Get timeout */ - timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -262,7 +314,7 @@ HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void) /** * @brief Deactivates the Over-Drive mode. - * @note These macros can be used only for STM32F42xx/STM32F43xx devices. + * @note This function can be used only for STM32F42xx/STM32F43xx devices. * This mode allows the CPU and the core logic to operate at a higher frequency * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). * @note It is recommended to enter or exit Over-drive mode when the application is not running @@ -274,19 +326,19 @@ HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void) */ HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void) { - uint32_t timeout = 0; + uint32_t tickstart = 0; __PWR_CLK_ENABLE(); /* Disable the Over-drive switch */ __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -295,12 +347,12 @@ HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void) /* Disable the Over-drive */ __HAL_PWR_OVERDRIVE_DISABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -308,6 +360,107 @@ HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void) return HAL_OK; } + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode is only available for STM32F42xxx/STM324F3xxx devices. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + * @retval None + */ +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Enable Power ctrl clock */ + __PWR_CLK_ENABLE(); + /* Enable the Under-drive Mode ---------------------------------------------*/ + /* Clear Under-drive flag */ + __HAL_PWR_CLEAR_ODRUDR_FLAG(); + + /* Enable the Under-drive */ + __HAL_PWR_UNDERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for UnderDrive mode is ready */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ + tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); + + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + return HAL_OK; +} + #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** * @} diff --git a/stmhal/hal/src/stm32f4xx_hal_rcc.c b/stmhal/hal/src/stm32f4xx_hal_rcc.c index 5f2ce34e0..bda08db3f 100644 --- a/stmhal/hal/src/stm32f4xx_hal_rcc.c +++ b/stmhal/hal/src/stm32f4xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -115,7 +115,7 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, ##### Initialization and de-initialization functions ##### =============================================================================== [..] - This section provide functions allowing to configure the internal/external oscillators + This section provides functions allowing to configure the internal/external oscillators (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 and APB2). @@ -176,77 +176,17 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should - be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| - +-------------------------------------------------------------------------------------+ + be adapted accordingly (refer to the product datasheets for more details). + (#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum frequency should - be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|150< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| - |-------------------------------------------------------------------------------------| - |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 180| - +-------------------------------------------------------------------------------------+ + be adapted accordingly (refer to the product datasheets for more details). + (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should - be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | - +-------------------------------------------------------------------------------------+ + be adapted accordingly (refer to the product datasheets for more details). @endverbatim * @{ */ @@ -301,8 +241,7 @@ void HAL_RCC_DeInit(void) */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); @@ -324,16 +263,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); - /* Get timeout */ - timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } /* Set the new HSE configuration ---------------------------------------*/ @@ -342,30 +281,30 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON) { - /* Get timeout */ - timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { - /* Get timeout */ - timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); /* Wait till HSE is bypassed or disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -377,13 +316,20 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - /* When the HSI is used as system clock it will not disabled */ + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) { + /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) { return HAL_ERROR; } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } } else { @@ -393,16 +339,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ @@ -413,16 +359,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -438,34 +384,34 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - - /* Get timeout */ - timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE; - + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - - /* Get timeout */ - timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -482,29 +428,29 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) PWR->CR |= PWR_CR_DBP; /* Wait for Backup domain Write protection disable */ - timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE; + tickstart = HAL_GetTick(); while((PWR->CR & PWR_CR_DBP) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } - + /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - /* Get timeout */ - timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE; - + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } /* Set the new LSE configuration -----------------------------------------*/ @@ -512,30 +458,30 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON) { - /* Get timeout */ - timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { - /* Get timeout */ - timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -558,17 +504,17 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - - /* Get timeout */ - timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE; - + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } /* Configure the main PLL clock source, multiplication and division factors. */ @@ -580,32 +526,33 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE; - + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - /* Get timeout */ - timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE; - + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -644,8 +591,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); @@ -668,6 +614,13 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui return HAL_ERROR; } + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { @@ -702,34 +655,34 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - /* Get timeout */ - timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -740,7 +693,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Decreasing the CPU frequency */ else { - /*------------------------- SYSCLK Configuration ---------------------------*/ + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration -------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); @@ -774,14 +734,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - /* Get timeout */ - timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE; + /* Get Start Tick*/ + tickstart = HAL_GetTick(); if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -791,7 +751,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -801,10 +761,10 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -819,14 +779,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui return HAL_ERROR; } } - - /*-------------------------- HCLK Configuration ----------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { @@ -841,16 +794,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } - /* Setup SysTick Timer for 1 msec interrupts. - ------------------------------------------ - The SysTick_Config() function is a CMSIS function which configure: - - The SysTick Reload register with value passed as function parameter. - - Configure the SysTick IRQ priority to the lowest value (0x0F). - - Reset the SysTick Counter register. - - Configure the SysTick Counter clock source to be Core Clock Source (HCLK). - - Enable the SysTick Interrupt. - - Start the SysTick Counter.*/ - SysTick_Config(HAL_RCC_GetHCLKFreq() / 1000); + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); return HAL_OK; } diff --git a/stmhal/hal/src/stm32f4xx_hal_rcc_ex.c b/stmhal/hal/src/stm32f4xx_hal_rcc_ex.c index a58e8cb24..a1938a97e 100644 --- a/stmhal/hal/src/stm32f4xx_hal_rcc_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief Extension RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -102,7 +102,7 @@ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t tmpreg = 0; /* Check the parameters */ @@ -121,14 +121,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); - /* Get new Timeout value */ - timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } @@ -168,23 +168,23 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); - /* Get new Timeout value */ - timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } } - /*----------------------- SAI/LTDC Configuration (PLLSAI) -------------------------*/ + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ - /*----------------------- Common configuration SAI/LTDC ---------------------------*/ - /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division + /*----------------------- Common configuration SAI/LTDC --------------------*/ + /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division factor is common parameters for both peripherals */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) @@ -194,19 +194,19 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); - /* Get new Timeout value */ - timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - /*---------------------------- SAI configuration -------------------------------*/ + /*---------------------------- SAI configuration -------------------------*/ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) @@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); } - /*---------------------------- LTDC configuration -------------------------------*/ + /*---------------------------- LTDC configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); @@ -241,21 +241,21 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); - /* Get new Timeout value */ - timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till PLLSAI is ready */ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } } - /*---------------------------- RTC configuration -------------------------------*/ + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Enable Power Clock*/ @@ -264,12 +264,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - /* Wait for Backup domain Write protection disable */ - timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); while((PWR->CR & PWR_CR_DBP) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -290,13 +290,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* If LSE is selected as RTC clock source, wait for LSE reactivation */ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) { - /* Get timeout */ - timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -305,7 +305,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } - /*---------------------------- TIM configuration -------------------------------*/ + /*---------------------------- TIM configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) { __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); @@ -316,8 +316,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that - * will be configured. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -354,7 +354,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the * RCC_PeriphCLKInitTypeDef. @@ -369,53 +370,63 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - /*---------------------------- I2S configuration -------------------------------*/ + /*---------------------------- I2S configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - +#if defined(STM32F411xE) + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); +#endif /* STM32F411xE */ /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - /* Get new Timeout value */ - timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE; + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } + +#if defined(STM32F411xE) + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); +#else /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); +#endif /* STM32F411xE */ /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); - /* Get new Timeout value */ - timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } } - /*---------------------------- RTC configuration -------------------------------*/ + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Enable Power Clock*/ @@ -423,13 +434,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - - /* Wait for Backup domain Write protection disable */ - timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE; - + + /* Get tick */ + tickstart = HAL_GetTick(); + while((PWR->CR & PWR_CR_DBP) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -450,16 +461,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* If LSE is selected as RTC clock source, wait for LSE reactivation */ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) { - /* Get timeout */ - timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE; - + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); @@ -471,7 +482,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ @@ -485,13 +496,44 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the PLLI2S Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - +#if defined(STM32F411xE) + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); +#endif /* STM32F411xE */ /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); } -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F411xE) +/** + * @brief Select LSE mode + * + * @note This mode is only available for STM32F411xx devices. + * + * @param Mode: specifies the LSE mode. + * This parameter can be one of the following values: + * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection + * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection + * @retval None + */ +void HAL_RCCEx_SelectLSEMode(uint8_t Mode) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_MODE(Mode)); + if(Mode == RCC_LSE_HIGHDRIVE_MODE) + { + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } +} + +#endif /* STM32F411xE */ + /** * @} */ diff --git a/stmhal/hal/src/stm32f4xx_hal_rng.c b/stmhal/hal/src/stm32f4xx_hal_rng.c index 83ec34912..d9372ed91 100644 --- a/stmhal/hal/src/stm32f4xx_hal_rng.c +++ b/stmhal/hal/src/stm32f4xx_hal_rng.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rng.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -69,6 +69,9 @@ #ifdef HAL_RNG_MODULE_ENABLED +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define RNG_TIMEOUT_VALUE 1000 @@ -102,7 +105,8 @@ /** * @brief Initializes the RNG according to the specified * parameters in the RNG_InitTypeDef and creates the associated handle. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) @@ -118,20 +122,23 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Init the low level hardware */ HAL_RNG_MspInit(hrng); } + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); - + /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; - + /* Return function status */ return HAL_OK; } /** * @brief DeInitializes the RNG peripheral. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) @@ -168,7 +175,8 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) /** * @brief Initializes the RNG MSP. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval None */ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) @@ -180,7 +188,8 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) /** * @brief DeInitializes the RNG MSP. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval None */ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) @@ -215,23 +224,25 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) * @brief Returns a 32-bit random number. * @note Each time the random number data is read the RNG_FLAG_DRDY flag * is automatically cleared. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval 32-bit random number */ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) { uint32_t random32bit = 0; - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hrng); - timeout = HAL_GetTick() + RNG_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -249,7 +260,8 @@ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) /** * @brief Returns a 32-bit random number with interrupt enabled. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval 32-bit random number */ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) @@ -286,13 +298,14 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) * not have enough entropy. In this case, it is recommended to clear the * SEIS bit using __HAL_RNG_CLEAR_FLAG(), then disable and enable * the RNG peripheral to reinitialize and restart the RNG. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval None */ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { - /* RNG clock error interrupt occured */ + /* RNG clock error interrupt occurred */ if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_CEI) != RESET) { HAL_RNG_ErrorCallback(hrng); @@ -307,7 +320,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) __HAL_UNLOCK(hrng); } - /* RNG seed error interrupt occured */ + /* RNG seed error interrupt occurred */ if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_SEI) != RESET) { HAL_RNG_ErrorCallback(hrng); @@ -341,7 +354,8 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /** * @brief Data Ready callback in non-blocking mode. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval None */ @@ -354,7 +368,8 @@ __weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng) /** * @brief RNG error callbacks. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval None */ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) @@ -385,7 +400,8 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) /** * @brief Returns the RNG state. - * @param hrng: RNG handle + * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. * @retval HAL state */ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) @@ -401,6 +417,8 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @} */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + #endif /* HAL_RNG_MODULE_ENABLED */ /** * @} @@ -411,4 +429,3 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stmhal/hal/src/stm32f4xx_hal_rtc.c b/stmhal/hal/src/stm32f4xx_hal_rtc.c index cce04de4f..83413921f 100644 --- a/stmhal/hal/src/stm32f4xx_hal_rtc.c +++ b/stmhal/hal/src/stm32f4xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -24,7 +24,7 @@ the RTC when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. - [..] To allow the RTC to operate even when the main digital supply (VDD) is turned + [..] To allow the RTC operating even when the main digital supply (VDD) is turned off, the VBAT pin powers the following blocks: (#) The RTC (#) The LSE oscillator @@ -32,13 +32,13 @@ (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following functions are available: + the following pins are available: (#) PC14 and PC15 can be used as either GPIO or LSE pins (#) PC13 can be used as a GPIO or as the RTC_AF1 pin (#) PI8 can be used as a GPIO or as the RTC_AF2 pin [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following functions are available: + because VDD is not present), the following pins are available: (#) PC14 and PC15 can be used as LSE pins only (#) PC13 can be used as the RTC_AF1 pin (#) PI8 can be used as the RTC_AF2 pin @@ -47,7 +47,7 @@ ================================================================== [..] The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. The BKPSRAM is not affected by this reset. The only - way of resetting the BKPSRAM is through the Flash interface by requesting + way to reset the BKPSRAM is through the Flash interface by requesting a protection level change from 1 to 0. [..] A backup domain reset is generated when one of the following events occurs: (#) Software reset, triggered by setting the BDRST bit in the @@ -101,7 +101,7 @@ or the RTC wakeup events. [..] The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC clock source + Wakeup from STOP and STANDBY modes is possible only when the RTC clock source is LSE or LSI. @endverbatim @@ -167,18 +167,18 @@ =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This section provide functions allowing to initialize and configure the + [..] This section provides functions allowing to initialize and configure the RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers Write protection, enter and exit the RTC initialization mode, RTC registers synchronization check and reference clock detection enable. (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize consumption. + asynchronous prescaler to a high value to minimize power consumption. (#) All RTC registers are Write protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To Configure the RTC Calendar, user application should enter + (#) To configure the RTC Calendar, user application should enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated. When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles. @@ -196,7 +196,8 @@ /** * @brief Initializes the RTC peripheral - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) @@ -267,13 +268,14 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /** * @brief DeInitializes the RTC peripheral - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @note This function doesn't reset the RTC Backup Data registers. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; @@ -299,13 +301,14 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) hrtc->Instance->DR = (uint32_t)0x00002101; /* Reset All CR bits except CR[2:0] */ hrtc->Instance->CR &= (uint32_t)0x00000007; - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; - + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till WUTWF flag is set and if Time out is reached exit */ while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -366,7 +369,8 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /** * @brief Initializes the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) @@ -378,7 +382,8 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /** * @brief DeInitializes the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) @@ -400,7 +405,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) ##### RTC Time and Date functions ##### =============================================================================== - [..] This section provide functions allowing to configure Time and Date features + [..] This section provides functions allowing to configure Time and Date features @endverbatim * @{ @@ -408,12 +413,13 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /** * @brief Sets RTC current time. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sTime: Pointer to Time structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg Format_BIN: Binary data format - * @arg Format_BCD: BCD data format + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -532,12 +538,13 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Gets RTC current time. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sTime: Pointer to Time structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg Format_BIN: Binary data format - * @arg Format_BCD: BCD data format + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values * in the higher-order calendar shadow registers. * @retval HAL status @@ -575,12 +582,13 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Sets RTC current date. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sDate: Pointer to date structure * @param Format: specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg Format_BIN: Binary data format - * @arg Format_BCD: BCD data format + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -683,12 +691,13 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /** * @brief Gets RTC current date. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sDate: Pointer to Date structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg Format_BIN : Binary data format - * @arg Format_BCD : BCD data format + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -730,24 +739,25 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat ##### RTC Alarm functions ##### =============================================================================== - [..] This section provide functions allowing to configure Alarm feature + [..] This section provides functions allowing to configure Alarm feature @endverbatim * @{ */ /** * @brief Sets the specified RTC Alarm. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sAlarm: Pointer to Alarm structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg Format_BIN: Binary data format - * @arg Format_BCD: BCD data format + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t tmpreg = 0, subsecondtmpreg = 0; /* Check the parameters */ @@ -846,12 +856,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -878,12 +890,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -918,17 +932,18 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Sets the specified RTC Alarm with Interrupt - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sAlarm: Pointer to Alarm structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg Format_BIN: Binary data format - * @arg Format_BCD: BCD data format + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t timeout = 0; + uint32_t tickstart = 0; uint32_t tmpreg = 0, subsecondtmpreg = 0; /* Check the parameters */ @@ -1025,11 +1040,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Clear flag alarm A */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1059,11 +1076,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Clear flag alarm B */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1087,7 +1106,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT); + __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT); EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; @@ -1104,16 +1123,17 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /** * @brief Deactive the specified RTC Alarm - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param Alarm: Specifies the Alarm. * This parameter can be one of the following values: - * @arg ALARM_A : AlarmA - * @arg ALARM_B : AlarmB + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_ALARM(Alarm)); @@ -1133,13 +1153,14 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; - + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1160,13 +1181,14 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; - + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1193,16 +1215,17 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /** * @brief Gets the RTC Alarm value and masks. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm + * @param Alarm: Specifies the Alarm. * This parameter can be one of the following values: - * @arg ALARM_A: AlarmA - * @arg ALARM_B: AlarmB + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg Format_BIN: Binary data format - * @arg Format_BCD: BCD data format + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) @@ -1252,7 +1275,8 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief This function handles Alarm interrupt request. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) @@ -1284,7 +1308,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) } /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT); + __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1292,7 +1316,8 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) @@ -1304,23 +1329,23 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles AlarmA Polling request. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ +{ + uint32_t tickstart = 0; - uint32_t timeout = 0; + /* Get tick */ + tickstart = HAL_GetTick(); - /* Get Timeout value */ - timeout = HAL_GetTick() + Timeout; - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1367,22 +1392,24 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait the registers to be synchronised */ while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -1406,8 +1433,9 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) * @{ */ /** - * @brief Returns the Alarm state. - * @param hrtc: RTC handle + * @brief Returns the RTC state. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL state */ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) @@ -1423,24 +1451,27 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) * @brief Enters the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check if the Initialization mode is set */ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) { /* Set the Initialization mode */ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { return HAL_TIMEOUT; } diff --git a/stmhal/hal/src/stm32f4xx_hal_rtc_ex.c b/stmhal/hal/src/stm32f4xx_hal_rtc_ex.c index 51014306d..864dd903c 100644 --- a/stmhal/hal/src/stm32f4xx_hal_rtc_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: @@ -26,7 +26,7 @@ ================================ [..] (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer with interrupt mode + function. You can also configure the RTC Wakeup timer in interrupt mode using the HAL_RTC_SetWakeUpTimer_IT() function. (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() function. @@ -34,7 +34,7 @@ *** TimeStamp configuration *** =============================== [..] - (+) Configure the RTC_AFx trigger and enables the RTC TimeStamp using the + (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with interrupt mode using the HAL_RTC_SetTimeStamp_IT() function. (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp() @@ -47,10 +47,10 @@ *** Tamper configuration *** ============================ [..] - (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge + (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge or Level according to the Tamper filter (if equal to 0 Edge else Level) value, sampling frequency, precharge or discharge and Pull-UP using the - HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt + HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt mode using HAL_RTC_SetTamper_IT() function. (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13) or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in @@ -130,7 +130,7 @@ ##### RTC TimeStamp and Tamper functions ##### =============================================================================== - [..] This section provide functions allowing to configure TimeStamp feature + [..] This section provides functions allowing to configure TimeStamp feature @endverbatim * @{ @@ -139,13 +139,14 @@ /** * @brief Sets TimeStamp. * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is * activated. - * This parameter can be one of the following: - * @arg TimeStampEdge_Rising: the Time stamp event occurs on the + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. - * @arg TimeStampEdge_Falling: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: @@ -196,14 +197,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /** * @brief Sets TimeStamp with Interrupt. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @note This API must be called before enabling the TimeStamp feature. * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is * activated. - * This parameter can be one of the following: - * @arg TimeStampEdge_Rising: the Time stamp event occurs on the + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. - * @arg TimeStampEdge_Falling: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: @@ -244,7 +246,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; @@ -261,7 +263,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /** * @brief Deactivates TimeStamp. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) @@ -298,13 +301,14 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Gets the RTC TimeStamp value. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sTimeStamp: Pointer to Time structure * @param sTimeStampDate: Pointer to Date structure * @param Format: specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg Format_BIN: Binary data format - * @arg Format_BCD: BCD data format + * FORMAT_BIN: Binary data format + * FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) @@ -354,7 +358,8 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe /** * @brief Sets Tamper * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sTamper: Pointer to Tamper Structure. * @retval HAL status */ @@ -403,7 +408,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /** * @brief Sets Tamper with interrupt. * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param sTamper: Pointer to RTC Tamper. * @retval HAL status */ @@ -427,11 +433,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType hrtc->State = HAL_RTC_STATE_BUSY; /* Configure the tamper trigger */ - if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL)) - { - sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE; - } - else + if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) { sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); } @@ -450,7 +452,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; @@ -464,7 +466,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /** * @brief Deactivates Tamper. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param Tamper: Selected tamper pin. * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2. * @retval HAL status @@ -491,7 +494,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T /** * @brief This function handles TimeStamp interrupt request. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) @@ -537,7 +541,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } } /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -545,7 +549,8 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief TimeStamp callback. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) @@ -557,7 +562,8 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 1 callback. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) @@ -569,7 +575,8 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 2 callback. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) @@ -581,16 +588,17 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles TimeStamp polling request. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - /* Get Timeout value */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) { @@ -607,7 +615,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -623,23 +631,24 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** * @brief This function handles Tamper1 Polling. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - /* Get Timeout value */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -658,23 +667,24 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief This function handles Tamper2 Polling. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - /* Get Timeout value */ - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -703,7 +713,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ ##### RTC Wake-up functions ##### =============================================================================== - [..] This section provide functions allowing to configure Wake-up feature + [..] This section provides functions allowing to configure Wake-up feature @endverbatim * @{ @@ -711,14 +721,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief Sets wake up timer. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param WakeUpCounter: Wake up counter * @param WakeUpClock: Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); @@ -733,13 +744,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -778,14 +790,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /** * @brief Sets wake up timer with interrupt - * @param hrtc: RTC handle - * @param WakeUpCounter: wake up counter - * @param WakeUpClock: wake up clock + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param WakeUpCounter: Wake up counter + * @param WakeUpClock: Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); @@ -800,13 +813,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; - + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -830,7 +844,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t hrtc->Instance->CR |= (uint32_t)WakeUpClock; /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; @@ -853,12 +867,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /** * @brief Deactivates wake up timer counter. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hrtc); @@ -873,12 +888,14 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -905,7 +922,8 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Gets wake up timer counter. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval Counter value */ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) @@ -916,7 +934,8 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief This function handles Wake Up Timer interrupt request. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) @@ -935,7 +954,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) } /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -943,7 +962,8 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief Wake Up Timer callback. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) @@ -955,22 +975,23 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles Wake Up Timer Polling. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); - /* Get Timeout value */ - timeout = HAL_GetTick() + Timeout; - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -1002,18 +1023,18 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin =============================================================================== [..] This subsection provides functions allowing to - (+) Writes a data in a specified RTC Backup data register + (+) Write a data in a specified RTC Backup data register (+) Read a data in a specified RTC Backup data register - (+) Sets the Coarse calibration parameters. - (+) Deactivates the Coarse calibration parameters - (+) Sets the Smooth calibration parameters. - (+) Configures the Synchronization Shift Control Settings. - (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Enables the RTC reference clock detection. + (+) Set the Coarse calibration parameters. + (+) Deactivate the Coarse calibration parameters + (+) Set the Smooth calibration parameters. + (+) Configure the Synchronization Shift Control Settings. + (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enable the RTC reference clock detection. (+) Disable the RTC reference clock detection. - (+) Enables the Bypass Shadow feature. - (+) Disables the Bypass Shadow feature. + (+) Enable the Bypass Shadow feature. + (+) Disable the Bypass Shadow feature. @endverbatim * @{ @@ -1021,7 +1042,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param BackupRegister: RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. @@ -1044,7 +1066,8 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /** * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param BackupRegister: RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. @@ -1066,7 +1089,8 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /** * @brief Sets the Coarse calibration parameters. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param CalibSign: Specifies the sign of the coarse calibration value. * This parameter can be one of the following values : * @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive @@ -1134,7 +1158,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t Cal /** * @brief Deactivates the Coarse calibration parameters. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) @@ -1184,7 +1209,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) /** * @brief Sets the Smooth calibration parameters. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param SmoothCalibPeriod: Select the Smooth Calibration Period. * This parameter can be can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s. @@ -1198,12 +1224,12 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmouthCalibMinusPulsesValue mut be equal to 0. + * SmouthCalibMinusPulsesValue must be equal to 0. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); @@ -1221,12 +1247,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo /* check if a calibration is pending*/ if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) { - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; - + /* Get tick */ + tickstart = HAL_GetTick(); + /* check if a calibration is pending*/ while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1260,7 +1287,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo /** * @brief Configures the Synchronization Shift Control Settings. * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. * This parameter can be one of the following values : * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. @@ -1271,7 +1299,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo */ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); @@ -1284,13 +1312,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE; + + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait until the shift is completed*/ while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1355,8 +1384,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /** * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @param CalibOutput : Select the Calibration output Selection . + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param CalibOutput: Select the Calibration output Selection . * This parameter can be one of the following values: * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. @@ -1397,7 +1427,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 /** * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) @@ -1426,7 +1457,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) /** * @brief Enables the RTC reference clock detection. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) @@ -1475,7 +1507,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Disable the RTC reference clock detection. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) @@ -1524,7 +1557,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Enables the Bypass Shadow feature. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @retval HAL status @@ -1556,7 +1590,8 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Disables the Bypass Shadow feature. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @retval HAL status @@ -1607,7 +1642,8 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Alarm B callback. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) @@ -1619,22 +1655,23 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles AlarmB Polling request. - * @param hrtc: RTC handle + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); - /* Get Timeout value */ - timeout = HAL_GetTick() + Timeout; - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; diff --git a/stmhal/hal/src/stm32f4xx_hal_sai.c b/stmhal/hal/src/stm32f4xx_hal_sai.c index c1b1fae6c..d1b7bb8ff 100644 --- a/stmhal/hal/src/stm32f4xx_hal_sai.c +++ b/stmhal/hal/src/stm32f4xx_hal_sai.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sai.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief SAI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral: @@ -18,10 +18,10 @@ ============================================================================== [..] - The SAI HAL driver can be used as follow: + The SAI HAL driver can be used as follows: (#) Declare a SAI_HandleTypeDef handle structure. - (#) Initialize the SAI low level resources by implement the HAL_SAI_MspInit() API: + (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API: (##) Enable the SAI interface clock. (##) SAI pins configuration: (+++) Enable the clock for the SAI GPIOs. @@ -56,12 +56,12 @@ the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. [..] - (@) In master TX mode: enabling the audio block immediately generates the bit clock + (@) In master Tx mode: enabling the audio block immediately generates the bit clock for the external slaves even if there is no data in the FIFO, However FS signal generation is conditioned by the presence of data in the FIFO. [..] - (@) In master RX mode: enabling the audio block immediately generates the bit clock + (@) In master Rx mode: enabling the audio block immediately generates the bit clock and FS signal for the external slaves. [..] @@ -72,7 +72,7 @@ (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. [..] - Three mode of operations are available within this driver : + Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -110,7 +110,7 @@ *** SAI HAL driver macros list *** ============================================= [..] - Below the list of most used macros in USART HAL driver. + Below the list of most used macros in USART HAL driver : (+) __HAL_SAI_ENABLE: Enable the SAI peripheral (+) __HAL_SAI_DISABLE: Disable the SAI peripheral @@ -174,6 +174,7 @@ #define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000) #define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020) +#define SAI_TIMEOUT_VALUE 10 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -199,7 +200,7 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma); [..] This subsection provides a set of functions allowing to initialize and de-initialize the SAIx peripheral: - (+) User must Implement HAL_SAI_MspInit() function in which he configures + (+) User must implement HAL_SAI_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). (+) Call the function HAL_SAI_Init() to configure the selected device with @@ -223,7 +224,8 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initializes the SAI according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) @@ -453,7 +455,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /** * @brief DeInitializes the SAI peripheral. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) @@ -483,7 +486,8 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /** * @brief SAI MSP Init. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) @@ -495,7 +499,8 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) /** * @brief SAI MSP DeInit. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) @@ -520,7 +525,7 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) This subsection provides a set of functions allowing to manage the SAI data transfers. - (+) There is two mode of transfer: + (+) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. @@ -535,17 +540,17 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) (++) HAL_SAI_Receive() (++) HAL_SAI_TransmitReceive() - (+) No-Blocking mode functions with Interrupt are : + (+) Non Blocking mode functions with Interrupt are : (++) HAL_SAI_Transmit_IT() (++) HAL_SAI_Receive_IT() (++) HAL_SAI_TransmitReceive_IT() - (+) No-Blocking mode functions with DMA are : + (+) Non Blocking mode functions with DMA are : (++) HAL_SAI_Transmit_DMA() (++) HAL_SAI_Receive_DMA() (++) HAL_SAI_TransmitReceive_DMA() - (+) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SAI_TxCpltCallback() (++) HAL_SAI_RxCpltCallback() (++) HAL_SAI_ErrorCallback() @@ -556,7 +561,8 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) /** * @brief Transmits an amount of data in blocking mode. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -564,7 +570,7 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) */ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uint16_t Size, uint32_t Timeout) { - uint32_t timeout = 0x00; + uint32_t tickstart = 0; if((pData == NULL ) || (Size == 0)) { @@ -587,17 +593,17 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uin while(Size > 0) { + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait the FIFO to be empty */ - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ) == RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) - { - + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; @@ -630,7 +636,8 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uin /** * @brief Receives an amount of data in blocking mode. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @param Timeout: Timeout duration @@ -638,7 +645,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uin */ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t timeout = 0x00; + uint32_t tickstart = 0; if((pData == NULL ) || (Size == 0)) { @@ -662,18 +669,17 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint /* Receive data */ while(Size > 0) { + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until RXNE flag is set */ - /* Get timeout */ - timeout = HAL_GetTick() + Timeout; - while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ) == RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) - { - + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; @@ -707,7 +713,8 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint /** * @brief Transmits an amount of data in no-blocking mode with Interrupt. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -784,7 +791,8 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, /** * @brief Receives an amount of data in no-blocking mode with Interrupt. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @retval HAL status @@ -855,8 +863,9 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, u /** * @brief Pauses the audio stream playing from the Media. - * @param hsai: SAI handle - * @retval None + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) { @@ -875,8 +884,9 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) /** * @brief Resumes the audio stream playing from the Media. - * @param hsai: SAI handle - * @retval None + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) { @@ -901,9 +911,10 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) } /** - * @brief Resumes the audio stream playing from the Media. - * @param hsai: SAI handle - * @retval None + * @brief Stops the audio stream playing from the Media. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) { @@ -936,7 +947,8 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) } /** * @brief Transmits an amount of data in no-blocking mode with DMA. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -996,8 +1008,9 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, } /** - * @brief Receive an amount of data in no-blocking mode with DMA. - * @param hsai: SAI handle + * @brief Receives an amount of data in no-blocking mode with DMA. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @retval HAL status @@ -1058,7 +1071,8 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, /** * @brief This function handles SAI interrupt request. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval HAL status */ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) @@ -1120,7 +1134,8 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer completed callbacks. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) @@ -1132,7 +1147,8 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer Half completed callbacks - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) @@ -1144,7 +1160,8 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer completed callbacks. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) @@ -1156,7 +1173,8 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer half completed callbacks - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) @@ -1168,7 +1186,8 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief SAI error callbacks. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) @@ -1191,7 +1210,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) ##### Peripheral State and Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1200,7 +1219,8 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) /** * @brief Returns the SAI state. - * @param hsai: SAI handle + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. * @retval HAL state */ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) @@ -1224,12 +1244,13 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) /** * @brief DMA SAI transmit process complete callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) { - uint32_t timeout = 0x00; + uint32_t tickstart = 0; SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent; @@ -1241,14 +1262,15 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) /* Disable SAI Tx DMA Request */ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Set timeout: 10 is the max delay to send the remaining data in the SAI FIFO */ - timeout = HAL_GetTick() + 10; - /* Wait until FIFO is empty */ while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FLVL) != RESET) { /* Check for the Timeout */ - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; @@ -1265,7 +1287,8 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI transmit process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1277,7 +1300,8 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process complete callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -1296,7 +1320,8 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1307,7 +1332,8 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) } /** * @brief DMA SAI communication error callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMAError(DMA_HandleTypeDef *hdma) diff --git a/stmhal/hal/src/stm32f4xx_hal_sd.c b/stmhal/hal/src/stm32f4xx_hal_sd.c index 1a50ba09c..08be7f689 100644 --- a/stmhal/hal/src/stm32f4xx_hal_sd.c +++ b/stmhal/hal/src/stm32f4xx_hal_sd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sd.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -76,10 +76,6 @@ (#) Configure the SD Card Data transfer frequency. By Default, the card transfer frequency is set to 24MHz. You can change or adapt this frequency by adjusting the "ClockDiv" field. - The SD Card frequency (SDIO_CK) is computed as follows: - - SDIO_CK = SDIOCLK / (ClockDiv + 2) - In transfer mode and according to the SD Card standard, make sure that the SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. To be able to use a frequency higher than 24MHz, you should use the SDIO @@ -196,11 +192,18 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - +/** @defgroup SD_Private_Define + * @{ + */ + /** * @brief SDIO Static flags, TimeOut, FIFO Address */ -#define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF) +#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ + SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ + SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ + SDIO_FLAG_DBCKEND)) + #define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) /** @@ -268,12 +271,17 @@ * SDIO_APP_CMD should be sent before sending these commands. */ #define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD) - +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd); static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr); static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); @@ -294,7 +302,10 @@ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma); static void SD_DMA_RxError(DMA_HandleTypeDef *hdma); static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma); static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); - +/** + * @} + */ + /** @defgroup SD_Private_Functions * @{ */ @@ -324,52 +335,52 @@ static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); */ HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo) { - __IO HAL_SD_ErrorTypedef errorState = SD_OK; - SD_InitTypeDef tmpInit; + __IO HAL_SD_ErrorTypedef errorstate = SD_OK; + SD_InitTypeDef tmpinit; /* Initialize the low level hardware (MSP) */ HAL_SD_MspInit(hsd); /* Default SDIO peripheral configuration for SD card initialization */ - tmpInit.ClockEdge = SDIO_CLOCK_EDGE_RISING; - tmpInit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - tmpInit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - tmpInit.BusWide = SDIO_BUS_WIDE_1B; - tmpInit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - tmpInit.ClockDiv = SDIO_INIT_CLK_DIV; + tmpinit.ClockEdge = SDIO_CLOCK_EDGE_RISING; + tmpinit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + tmpinit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + tmpinit.BusWide = SDIO_BUS_WIDE_1B; + tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + tmpinit.ClockDiv = SDIO_INIT_CLK_DIV; /* Initialize SDIO peripheral interface with default configuration */ - SDIO_Init(hsd->Instance, tmpInit); + SDIO_Init(hsd->Instance, tmpinit); /* Identify card operating voltage */ - errorState = SD_PowerON(hsd); + errorstate = SD_PowerON(hsd); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Initialize the present SDIO card(s) and put them in idle state */ - errorState = SD_Initialize_Cards(hsd); + errorstate = SD_Initialize_Cards(hsd); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Read CSD/CID MSD registers */ - errorState = HAL_SD_Get_CardInfo(hsd, SDCardInfo); + errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo); - if (errorState == SD_OK) + if (errorstate == SD_OK) { /* Select the Card */ - errorState = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16)); + errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16)); } /* Configure SDIO peripheral interface */ SDIO_Init(hsd->Instance, hsd->Init); - return errorState; + return errorstate; } /** @@ -446,9 +457,9 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) */ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - SDIO_DataInitTypeDef SDIO_DataInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer; /* Initialize data control register */ @@ -461,53 +472,53 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff } /* Set Block Size for Card */ - SDIO_CmdInitStructure.Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t) BlockSize; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Configure the SD DPSM (Data Path State Machine) */ - SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.DataLength = NumberOfBlocks * BlockSize; - SDIO_DataInitStructure.DataBlockSize = (uint32_t)(9 << 4); - SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure); + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; + sdio_datainitstructure.DataBlockSize = (uint32_t)(9 << 4); + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); if(NumberOfBlocks > 1) { /* Send CMD18 READ_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; + sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; } else { /* Send CMD17 READ_SINGLE_BLOCK */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; } - SDIO_CmdInitStructure.Argument = (uint32_t)ReadAddr; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Read block(s) in polling mode */ if(NumberOfBlocks > 1) { /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Poll on SDIO flags */ @@ -528,11 +539,11 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff else { /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* In case of single block transfer, no need of stop transfer at all */ @@ -559,7 +570,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff (hsd->CardType == HIGH_CAPACITY_SD_CARD)) { /* Send stop transmission command */ - errorState = HAL_SD_StopTransfer(hsd); + errorstate = HAL_SD_StopTransfer(hsd); } } @@ -568,33 +579,37 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - errorState = SD_DATA_TIMEOUT; + errorstate = SD_DATA_TIMEOUT; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - errorState = SD_DATA_CRC_FAIL; + errorstate = SD_DATA_CRC_FAIL; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - errorState = SD_RX_OVERRUN; + errorstate = SD_RX_OVERRUN; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - errorState = SD_START_BIT_ERR; + errorstate = SD_START_BIT_ERR; - return errorState; + return errorstate; + } + else + { + /* No error flag set */ } count = SD_DATATIMEOUT; @@ -610,7 +625,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff /* Clear all the static flags */ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - return errorState; + return errorstate; } /** @@ -626,10 +641,10 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff */ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - SDIO_DataInitTypeDef SDIO_DataInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; - uint32_t TotalNumberOfBytes = 0, bytestransferred = 0, count = 0, restwords = 0; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0; uint32_t *tempbuff = (uint32_t *)pWriteBuffer; uint8_t cardstate = 0; @@ -643,61 +658,61 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu } /* Set Block Size for Card */ - SDIO_CmdInitStructure.Argument = (uint32_t)BlockSize; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } if(NumberOfBlocks > 1) { /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; + sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; } else { /* Send CMD24 WRITE_SINGLE_BLOCK */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; + sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; } - SDIO_CmdInitStructure.Argument = (uint32_t)WriteAddr; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ if(NumberOfBlocks > 1) { - errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); } else { - errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); } - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Set total number of bytes to write */ - TotalNumberOfBytes = NumberOfBlocks * BlockSize; + totalnumberofbytes = NumberOfBlocks * BlockSize; /* Configure the SD DPSM (Data Path State Machine) */ - SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.DataLength = NumberOfBlocks * BlockSize; - SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; - SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure); + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); /* Write block(s) in polling mode */ if(NumberOfBlocks > 1) @@ -706,9 +721,9 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu { if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) { - if ((TotalNumberOfBytes - bytestransferred) < 32) + if ((totalnumberofbytes - bytestransferred) < 32) { - restwords = ((TotalNumberOfBytes - bytestransferred) % 4 == 0) ? ((TotalNumberOfBytes - bytestransferred) / 4) : (( TotalNumberOfBytes - bytestransferred) / 4 + 1); + restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); /* Write data to SDIO Tx FIFO */ for (count = 0; count < restwords; count++) @@ -739,9 +754,9 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu { if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) { - if ((TotalNumberOfBytes - bytestransferred) < 32) + if ((totalnumberofbytes - bytestransferred) < 32) { - restwords = ((TotalNumberOfBytes - bytestransferred) % 4 == 0) ? ((TotalNumberOfBytes - bytestransferred) / 4) : (( TotalNumberOfBytes - bytestransferred) / 4 + 1); + restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); /* Write data to SDIO Tx FIFO */ for (count = 0; count < restwords; count++) @@ -773,7 +788,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu (hsd->CardType == HIGH_CAPACITY_SD_CARD)) { /* Send stop transmission command */ - errorState = HAL_SD_StopTransfer(hsd); + errorstate = HAL_SD_StopTransfer(hsd); } } @@ -782,47 +797,51 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - errorState = SD_DATA_TIMEOUT; + errorstate = SD_DATA_TIMEOUT; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - errorState = SD_DATA_CRC_FAIL; + errorstate = SD_DATA_CRC_FAIL; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR); - errorState = SD_TX_UNDERRUN; + errorstate = SD_TX_UNDERRUN; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - errorState = SD_START_BIT_ERR; + errorstate = SD_START_BIT_ERR; - return errorState; + return errorstate; + } + else + { + /* No error flag set */ } /* Clear all the static flags */ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); /* Wait till the card is in programming state */ - errorState = SD_IsCardProgramming(hsd, &cardstate); + errorstate = SD_IsCardProgramming(hsd, &cardstate); - while ((errorState == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) + while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) { - errorState = SD_IsCardProgramming(hsd, &cardstate); + errorstate = SD_IsCardProgramming(hsd, &cardstate); } - return errorState; + return errorstate; } /** @@ -840,9 +859,9 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu */ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - SDIO_DataInitTypeDef SDIO_DataInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; /* Initialize data control register */ hsd->Instance->DCTRL = 0; @@ -877,7 +896,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead hsd->hdmarx->XferErrorCallback = SD_DMA_RxError; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)SDIO_FIFO_ADDRESS, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)); + HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)); if (hsd->CardType == HIGH_CAPACITY_SD_CARD) { @@ -886,59 +905,59 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead } /* Set Block Size for Card */ - SDIO_CmdInitStructure.Argument = (uint32_t)BlockSize; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Configure the SD DPSM (Data Path State Machine) */ - SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.DataLength = BlockSize * NumberOfBlocks; - SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure); + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); /* Check number of blocks command */ if(NumberOfBlocks > 1) { /* Send CMD18 READ_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; + sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; } else { /* Send CMD17 READ_SINGLE_BLOCK */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; } - SDIO_CmdInitStructure.Argument = (uint32_t)ReadAddr; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ if(NumberOfBlocks > 1) { - errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); } else { - errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); } /* Update the SD transfer error in SD handle */ - hsd->SdTransferErr = errorState; + hsd->SdTransferErr = errorstate; - return errorState; + return errorstate; } @@ -957,9 +976,9 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead */ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - SDIO_DataInitTypeDef SDIO_DataInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; /* Initialize data control register */ hsd->Instance->DCTRL = 0; @@ -991,7 +1010,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri hsd->hdmatx->XferErrorCallback = SD_DMA_TxError; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)SDIO_FIFO_ADDRESS, (uint32_t)(BlockSize * NumberOfBlocks)); + HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)); /* Enable SDIO DMA transfer */ __HAL_SD_SDIO_DMA_ENABLE(); @@ -1003,63 +1022,63 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri } /* Set Block Size for Card */ - SDIO_CmdInitStructure.Argument = (uint32_t)BlockSize; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Check number of blocks command */ if(NumberOfBlocks <= 1) { /* Send CMD24 WRITE_SINGLE_BLOCK */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; + sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; } else { /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; + sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; } - SDIO_CmdInitStructure.Argument = (uint32_t)WriteAddr; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ if(NumberOfBlocks > 1) { - errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); } else { - errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); } - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Configure the SD DPSM (Data Path State Machine) */ - SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.DataLength = BlockSize * NumberOfBlocks; - SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; - SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure); + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - hsd->SdTransferErr = errorState; + hsd->SdTransferErr = errorstate; - return errorState; + return errorstate; } /** @@ -1073,7 +1092,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri */ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) { - HAL_SD_ErrorTypedef errorState = SD_OK; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t timeout = Timeout; uint32_t tmp1, tmp2; HAL_SD_ErrorTypedef tmp3; @@ -1102,12 +1121,12 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti /* Send stop command in multiblock read */ if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK) { - errorState = HAL_SD_StopTransfer(hsd); + errorstate = HAL_SD_StopTransfer(hsd); } - if ((timeout == 0) && (errorState == SD_OK)) + if ((timeout == 0) && (errorstate == SD_OK)) { - errorState = SD_DATA_TIMEOUT; + errorstate = SD_DATA_TIMEOUT; } /* Clear all the static flags */ @@ -1119,7 +1138,7 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); } - return errorState; + return errorstate; } /** @@ -1133,7 +1152,7 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti */ HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) { - HAL_SD_ErrorTypedef errorState = SD_OK; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t timeout = Timeout; uint32_t tmp1, tmp2; HAL_SD_ErrorTypedef tmp3; @@ -1162,12 +1181,12 @@ HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t T /* Send stop command in multiblock write */ if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK) { - errorState = HAL_SD_StopTransfer(hsd); + errorstate = HAL_SD_StopTransfer(hsd); } - if ((timeout == 0) && (errorState == SD_OK)) + if ((timeout == 0) && (errorstate == SD_OK)) { - errorState = SD_DATA_TIMEOUT; + errorstate = SD_DATA_TIMEOUT; } /* Clear all the static flags */ @@ -1184,7 +1203,7 @@ HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t T { } - return errorState; + return errorstate; } /** @@ -1196,8 +1215,8 @@ HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t T */ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr) { - HAL_SD_ErrorTypedef errorState = SD_OK; - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; uint32_t delay = 0; __IO uint32_t maxdelay = 0; @@ -1206,9 +1225,9 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint /* Check if the card command class supports erase command */ if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0) { - errorState = SD_REQUEST_NOT_APPLICABLE; + errorstate = SD_REQUEST_NOT_APPLICABLE; - return errorState; + return errorstate; } /* Get max delay value */ @@ -1216,9 +1235,9 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) { - errorState = SD_LOCK_UNLOCK_FAILED; + errorstate = SD_LOCK_UNLOCK_FAILED; - return errorState; + return errorstate; } /* Get start and end block for high capacity cards */ @@ -1233,46 +1252,46 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint (hsd->CardType == HIGH_CAPACITY_SD_CARD)) { /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - SDIO_CmdInitStructure.Argument =(uint32_t)startaddr; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument =(uint32_t)startaddr; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - SDIO_CmdInitStructure.Argument = (uint32_t)endaddr; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)endaddr; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } } /* Send CMD38 ERASE */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_ERASE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_ERASE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_ERASE); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } for (; delay < maxdelay; delay++) @@ -1280,17 +1299,17 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint } /* Wait untill the card is in programming state */ - errorState = SD_IsCardProgramming(hsd, &cardstate); + errorstate = SD_IsCardProgramming(hsd, &cardstate); delay = SD_DATATIMEOUT; - while ((delay > 0) && (errorState == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) + while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) { - errorState = SD_IsCardProgramming(hsd, &cardstate); + errorstate = SD_IsCardProgramming(hsd, &cardstate); delay--; } - return errorState; + return errorstate; } /** @@ -1354,6 +1373,10 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) HAL_SD_XferErrorCallback(hsd); } + else + { + /* No error flag set */ + } /* Disable all SDIO peripheral interrupt sources */ __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\ @@ -1388,7 +1411,8 @@ __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) /** * @brief SD Transfer complete Rx callback in non blocking mode. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) @@ -1400,7 +1424,8 @@ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief SD DMA transfer complete Rx error callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) @@ -1412,7 +1437,8 @@ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief SD Transfer complete Tx callback in non blocking mode. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) @@ -1424,7 +1450,8 @@ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief SD DMA transfer complete error Tx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) @@ -1462,7 +1489,7 @@ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) */ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo) { - HAL_SD_ErrorTypedef errorState = SD_OK; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t tmp = 0; pCardInfo->CardType = (uint8_t)(hsd->CardType); @@ -1554,7 +1581,12 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024; pCardInfo->CardBlockSize = 512; } - + else + { + /* Not supported card type */ + errorstate = SD_ERROR; + } + pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; @@ -1657,7 +1689,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; pCardInfo->SD_cid.Reserved2 = 1; - return errorState; + return errorstate; } /** @@ -1673,64 +1705,51 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy */ HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode) { - HAL_SD_ErrorTypedef errorState = SD_OK; - SDIO_InitTypeDef Init; + HAL_SD_ErrorTypedef errorstate = SD_OK; + SDIO_InitTypeDef tmpinit; /* MMC Card does not support this feature */ if (hsd->CardType == MULTIMEDIA_CARD) { - errorState = SD_UNSUPPORTED_FEATURE; + errorstate = SD_UNSUPPORTED_FEATURE; - return errorState; + return errorstate; } else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ (hsd->CardType == HIGH_CAPACITY_SD_CARD)) { if (WideMode == SDIO_BUS_WIDE_8B) { - errorState = SD_UNSUPPORTED_FEATURE; - - return errorState; + errorstate = SD_UNSUPPORTED_FEATURE; } else if (WideMode == SDIO_BUS_WIDE_4B) { - errorState = SD_WideBus_Enable(hsd); - - if (errorState == SD_OK) - { - /* Configure the SDIO peripheral */ - Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; - Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - Init.BusWide = SDIO_BUS_WIDE_4B; - Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - Init.ClockDiv = SDIO_TRANSFER_CLK_DIV; - - /* Configure SDIO peripheral interface */ - SDIO_Init(hsd->Instance, Init); - } + errorstate = SD_WideBus_Enable(hsd); + } + else if (WideMode == SDIO_BUS_WIDE_1B) + { + errorstate = SD_WideBus_Disable(hsd); } else { - errorState = SD_WideBus_Disable(hsd); + /* WideMode is not a valid argument*/ + errorstate = SD_INVALID_PARAMETER; + } - if (errorState == SD_OK) - { - /* Configure the SDIO peripheral */ - Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; - Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - Init.BusWide = SDIO_BUS_WIDE_1B; - Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - Init.ClockDiv = SDIO_TRANSFER_CLK_DIV; - - /* Configure SDIO peripheral interface */ - SDIO_Init(hsd->Instance, Init); - } + if (errorstate == SD_OK) + { + /* Configure the SDIO peripheral */ + tmpinit.ClockEdge = hsd->Init.ClockEdge; + tmpinit.ClockBypass = hsd->Init.ClockBypass; + tmpinit.ClockPowerSave = hsd->Init.ClockPowerSave; + tmpinit.BusWide = WideMode; + tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl; + tmpinit.ClockDiv = hsd->Init.ClockDiv; + SDIO_Init(hsd->Instance, tmpinit); } } - return errorState; + return errorstate; } /** @@ -1740,21 +1759,21 @@ HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32 */ HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; /* Send CMD12 STOP_TRANSMISSION */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_STOP_TRANSMISSION; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION); - return errorState; + return errorstate; } /** @@ -1767,9 +1786,9 @@ HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd) */ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorState = SD_OK; - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - SDIO_DataInitTypeDef SDIO_DataInitStructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; uint8_t SD_hs[64] = {0}; uint32_t SD_scr[2] = {0, 0}; @@ -1780,11 +1799,11 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) hsd->Instance->DCTRL = 0; /* Get SCR Register */ - errorState = SD_FindSCR(hsd, SD_scr); + errorstate = SD_FindSCR(hsd, SD_scr); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Test the Version supported by the card*/ @@ -1793,41 +1812,41 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) if (SD_SPEC != SD_ALLZERO) { /* Set Block Size for Card */ - SDIO_CmdInitStructure.Argument = (uint32_t)64; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)64; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Configure the SD DPSM (Data Path State Machine) */ - SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.DataLength = 64; - SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ; - SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure); + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = 64; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); /* Send CMD6 switch mode */ - SDIO_CmdInitStructure.Argument = 0x80FFFF01; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_HS_SWITCH; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0x80FFFF01; + sdio_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) @@ -1847,35 +1866,39 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - errorState = SD_DATA_TIMEOUT; + errorstate = SD_DATA_TIMEOUT; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - errorState = SD_DATA_CRC_FAIL; + errorstate = SD_DATA_CRC_FAIL; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - errorState = SD_RX_OVERRUN; + errorstate = SD_RX_OVERRUN; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - errorState = SD_START_BIT_ERR; + errorstate = SD_START_BIT_ERR; - return errorState; + return errorstate; } - + else + { + /* No error flag set */ + } + count = SD_DATATIMEOUT; while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) @@ -1891,11 +1914,11 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) /* Test if the switch mode HS is ok */ if ((SD_hs[13]& 2) != 2) { - errorState = SD_UNSUPPORTED_FEATURE; + errorstate = SD_UNSUPPORTED_FEATURE; } } - return errorState; + return errorstate; } /** @@ -1926,68 +1949,68 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) */ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - SDIO_DataInitTypeDef SDIO_DataInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t count = 0; /* Check SD response */ if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) { - errorState = SD_LOCK_UNLOCK_FAILED; + errorstate = SD_LOCK_UNLOCK_FAILED; - return errorState; + return errorstate; } /* Set block size for card if it is not equal to current block size for card */ - SDIO_CmdInitStructure.Argument = 64; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 64; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Send CMD55 */ - SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16); - SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Configure the SD DPSM (Data Path State Machine) */ - SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.DataLength = 64; - SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B; - SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure); + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = 64; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_APP_STAUS; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STAUS; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Get status data */ @@ -2008,34 +2031,38 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - errorState = SD_DATA_TIMEOUT; + errorstate = SD_DATA_TIMEOUT; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - errorState = SD_DATA_CRC_FAIL; + errorstate = SD_DATA_CRC_FAIL; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - errorState = SD_RX_OVERRUN; + errorstate = SD_RX_OVERRUN; - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - errorState = SD_START_BIT_ERR; + errorstate = SD_START_BIT_ERR; - return errorState; + return errorstate; } + else + { + /* No error flag set */ + } count = SD_DATATIMEOUT; while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) @@ -2048,7 +2075,7 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat /* Clear all the static status flags*/ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - return errorState; + return errorstate; } /** @@ -2087,87 +2114,96 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd) */ HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus) { - HAL_SD_ErrorTypedef errorState = SD_OK; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t tmp = 0; - uint32_t SD_STATUS[16]; + uint32_t sd_status[16]; - errorState = HAL_SD_SendSDStatus(hsd, SD_STATUS); + errorstate = HAL_SD_SendSDStatus(hsd, sd_status); - if (errorState != SD_OK) + if (errorstate != SD_OK) { - return errorState; + return errorstate; } /* Byte 0 */ - tmp = (SD_STATUS[0] & 0xC0) >> 6; + tmp = (sd_status[0] & 0xC0) >> 6; pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp; /* Byte 0 */ - tmp = (SD_STATUS[0] & 0x20) >> 5; + tmp = (sd_status[0] & 0x20) >> 5; pCardStatus->SECURED_MODE = (uint8_t)tmp; /* Byte 2 */ - tmp = (SD_STATUS[2] & 0xFF); + tmp = (sd_status[2] & 0xFF); pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8); /* Byte 3 */ - tmp = (SD_STATUS[3] & 0xFF); + tmp = (sd_status[3] & 0xFF); pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp; /* Byte 4 */ - tmp = (SD_STATUS[4] & 0xFF); + tmp = (sd_status[4] & 0xFF); pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24); /* Byte 5 */ - tmp = (SD_STATUS[5] & 0xFF); + tmp = (sd_status[5] & 0xFF); pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16); /* Byte 6 */ - tmp = (SD_STATUS[6] & 0xFF); + tmp = (sd_status[6] & 0xFF); pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8); /* Byte 7 */ - tmp = (SD_STATUS[7] & 0xFF); + tmp = (sd_status[7] & 0xFF); pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp; /* Byte 8 */ - tmp = (SD_STATUS[8] & 0xFF); + tmp = (sd_status[8] & 0xFF); pCardStatus->SPEED_CLASS = (uint8_t)tmp; /* Byte 9 */ - tmp = (SD_STATUS[9] & 0xFF); + tmp = (sd_status[9] & 0xFF); pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp; /* Byte 10 */ - tmp = (SD_STATUS[10] & 0xF0) >> 4; + tmp = (sd_status[10] & 0xF0) >> 4; pCardStatus->AU_SIZE = (uint8_t)tmp; /* Byte 11 */ - tmp = (SD_STATUS[11] & 0xFF); + tmp = (sd_status[11] & 0xFF); pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8); /* Byte 12 */ - tmp = (SD_STATUS[12] & 0xFF); + tmp = (sd_status[12] & 0xFF); pCardStatus->ERASE_SIZE |= (uint8_t)tmp; /* Byte 13 */ - tmp = (SD_STATUS[13] & 0xFC) >> 2; + tmp = (sd_status[13] & 0xFC) >> 2; pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp; /* Byte 13 */ - tmp = (SD_STATUS[13] & 0x3); + tmp = (sd_status[13] & 0x3); pCardStatus->ERASE_OFFSET = (uint8_t)tmp; - return errorState; + return errorstate; } /** * @} */ - + +/** + * @} + */ + +/** @addtogroup SD_Private_Functions + * @{ + */ + /** * @brief SD DMA transfer complete Rx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) @@ -2188,7 +2224,8 @@ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) /** * @brief SD DMA transfer Error Rx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SD_DMA_RxError(DMA_HandleTypeDef *hdma) @@ -2201,7 +2238,8 @@ static void SD_DMA_RxError(DMA_HandleTypeDef *hdma) /** * @brief SD DMA transfer complete Tx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) @@ -2222,7 +2260,8 @@ static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) /** * @brief SD DMA transfer Error Tx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SD_DMA_TxError(DMA_HandleTypeDef *hdma) @@ -2260,33 +2299,33 @@ static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint16_t sd_rca = 1; if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */ { - errorState = SD_REQUEST_NOT_APPLICABLE; + errorstate = SD_REQUEST_NOT_APPLICABLE; - return errorState; + return errorstate; } if(hsd->CardType != SECURE_DIGITAL_IO_CARD) { /* Send CMD2 ALL_SEND_CID */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_ALL_SEND_CID; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_LONG; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp2Error(hsd); + errorstate = SD_CmdResp2Error(hsd); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Get Card identification number data */ @@ -2301,16 +2340,16 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_REL_ADDR; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca); + errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } } @@ -2320,17 +2359,17 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) hsd->RCA = sd_rca; /* Send CMD9 SEND_CSD with argument as card's RCA */ - SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16); - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SEND_CSD; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_LONG; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp2Error(hsd); + errorstate = SD_CmdResp2Error(hsd); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Get Card Specific Data */ @@ -2341,7 +2380,7 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) } /* All cards are initialized */ - return errorState; + return errorstate; } /** @@ -2352,21 +2391,21 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; /* Send CMD7 SDIO_SEL_DESEL_CARD */ - SDIO_CmdInitStructure.Argument = (uint32_t)addr; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SEL_DESEL_CARD; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)addr; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD); - return errorState; + return errorstate; } /** @@ -2378,10 +2417,10 @@ static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t ad */ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - __IO HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + __IO HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t response = 0, count = 0, validvoltage = 0; - uint32_t SDType = SD_STD_CAPACITY; + uint32_t sdtype = SD_STD_CAPACITY; /* Power ON Sequence -------------------------------------------------------*/ /* Disable SDIO Clock */ @@ -2395,20 +2434,20 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/ /* No CMD response required */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_GO_IDLE_STATE; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_NO; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_NO; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdError(hsd); + errorstate = SD_CmdError(hsd); - if(errorState != SD_OK) + if(errorstate != SD_OK) { /* CMD Response TimeOut (wait for CMDSENT flag) */ - return errorState; + return errorstate; } /* CMD8: SEND_IF_COND ------------------------------------------------------*/ @@ -2417,33 +2456,33 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - [7:0]: Check Pattern (recommended 0xAA) */ /* CMD Response: R7 */ - SDIO_CmdInitStructure.Argument = SD_CHECK_PATTERN; - SDIO_CmdInitStructure.CmdIndex = SD_SDIO_SEND_IF_COND; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = SD_CHECK_PATTERN; + sdio_cmdinitstructure.CmdIndex = SD_SDIO_SEND_IF_COND; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp7Error(hsd); + errorstate = SD_CmdResp7Error(hsd); - if (errorState == SD_OK) + if (errorstate == SD_OK) { /* SD Card 2.0 */ hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; - SDType = SD_HIGH_CAPACITY; + sdtype = SD_HIGH_CAPACITY; } /* Send CMD55 */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - /* If errorState is Command TimeOut, it is a MMC card */ - /* If errorState is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) + /* If errorstate is Command TimeOut, it is a MMC card */ + /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) or SD card 1.x */ - if(errorState == SD_OK) + if(errorstate == SD_OK) { /* SD CARD */ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ @@ -2451,35 +2490,35 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) { /* SEND CMD55 APP_CMD with RCA as 0 */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Send CMD41 */ - SDIO_CmdInitStructure.Argument = SD_VOLTAGE_WINDOW_SD | SDType; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_APP_OP_COND; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp3Error(hsd); + errorstate = SD_CmdResp3Error(hsd); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Get command response */ @@ -2493,9 +2532,9 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) if(count >= SD_MAX_VOLT_TRIAL) { - errorState = SD_INVALID_VOLTRANGE; + errorstate = SD_INVALID_VOLTRANGE; - return errorState; + return errorstate; } if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ @@ -2505,7 +2544,7 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) } /* else MMC Card */ - return errorState; + return errorstate; } /** @@ -2515,12 +2554,12 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorState = SD_OK; + HAL_SD_ErrorTypedef errorstate = SD_OK; /* Set Power State to OFF */ SDIO_PowerState_OFF(hsd->Instance); - return errorState; + return errorstate; } /** @@ -2532,36 +2571,36 @@ static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; if(pCardStatus == NULL) { - errorState = SD_INVALID_PARAMETER; + errorstate = SD_INVALID_PARAMETER; - return errorState; + return errorstate; } /* Send Status command */ - SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16); - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SEND_STATUS; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Get SD card status */ *pCardStatus = SDIO_GetResponse(SDIO_RESP1); - return errorState; + return errorstate; } /** @@ -2571,7 +2610,7 @@ static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardS */ static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorState = SD_OK; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t timeout, tmp; timeout = SDIO_CMD0TIMEOUT; @@ -2586,14 +2625,14 @@ static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd) if(timeout == 0) { - errorState = SD_CMD_RSP_TIMEOUT; - return errorState; + errorstate = SD_CMD_RSP_TIMEOUT; + return errorstate; } /* Clear all the static flags */ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - return errorState; + return errorstate; } /** @@ -2603,7 +2642,7 @@ static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorState = SD_ERROR; + HAL_SD_ErrorTypedef errorstate = SD_ERROR; uint32_t timeout = SDIO_CMD0TIMEOUT, tmp; tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); @@ -2619,24 +2658,24 @@ static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd) if((timeout == 0) || tmp) { /* Card is not V2.0 compliant or card does not support the set voltage range */ - errorState = SD_CMD_RSP_TIMEOUT; + errorstate = SD_CMD_RSP_TIMEOUT; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - return errorState; + return errorstate; } if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND)) { /* Card is SD V2.0 compliant */ - errorState = SD_OK; + errorstate = SD_OK; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND); - return errorState; + return errorstate; } - return errorState; + return errorstate; } /** @@ -2647,8 +2686,8 @@ static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD) { - HAL_SD_ErrorTypedef errorState = SD_OK; - uint32_t response_R1; + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t response_r1; while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) { @@ -2656,136 +2695,136 @@ static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CM if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) { - errorState = SD_CMD_RSP_TIMEOUT; + errorstate = SD_CMD_RSP_TIMEOUT; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - return errorState; + return errorstate; } else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) { - errorState = SD_CMD_CRC_FAIL; + errorstate = SD_CMD_CRC_FAIL; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - return errorState; + return errorstate; } /* Check response received is of desired command */ if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD) { - errorState = SD_ILLEGAL_CMD; + errorstate = SD_ILLEGAL_CMD; - return errorState; + return errorstate; } /* Clear all the static flags */ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); /* We have received response, retrieve it for analysis */ - response_R1 = SDIO_GetResponse(SDIO_RESP1); + response_r1 = SDIO_GetResponse(SDIO_RESP1); - if((response_R1 & SD_OCR_ERRORBITS) == SD_ALLZERO) + if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) { - return errorState; + return errorstate; } - if((response_R1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) + if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) { return(SD_ADDR_OUT_OF_RANGE); } - if((response_R1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) + if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) { return(SD_ADDR_MISALIGNED); } - if((response_R1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) + if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) { return(SD_BLOCK_LEN_ERR); } - if((response_R1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) + if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) { return(SD_ERASE_SEQ_ERR); } - if((response_R1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) + if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) { return(SD_BAD_ERASE_PARAM); } - if((response_R1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) + if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) { return(SD_WRITE_PROT_VIOLATION); } - if((response_R1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) + if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) { return(SD_LOCK_UNLOCK_FAILED); } - if((response_R1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) + if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) { return(SD_COM_CRC_FAILED); } - if((response_R1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) + if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) { return(SD_ILLEGAL_CMD); } - if((response_R1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) + if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) { return(SD_CARD_ECC_FAILED); } - if((response_R1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) + if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) { return(SD_CC_ERROR); } - if((response_R1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) + if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) { return(SD_GENERAL_UNKNOWN_ERROR); } - if((response_R1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) + if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) { return(SD_STREAM_READ_UNDERRUN); } - if((response_R1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) + if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) { return(SD_STREAM_WRITE_OVERRUN); } - if((response_R1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE) + if((response_r1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE) { return(SD_CID_CSD_OVERWRITE); } - if((response_R1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) + if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) { return(SD_WP_ERASE_SKIP); } - if((response_R1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) + if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) { return(SD_CARD_ECC_DISABLED); } - if((response_R1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) + if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) { return(SD_ERASE_RESET); } - if((response_R1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) + if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) { return(SD_AKE_SEQ_ERROR); } - return errorState; + return errorstate; } /** @@ -2795,7 +2834,7 @@ static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CM */ static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorState = SD_OK; + HAL_SD_ErrorTypedef errorstate = SD_OK; while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) { @@ -2803,17 +2842,17 @@ static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd) if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) { - errorState = SD_CMD_RSP_TIMEOUT; + errorstate = SD_CMD_RSP_TIMEOUT; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - return errorState; + return errorstate; } /* Clear all the static flags */ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - return errorState; + return errorstate; } /** @@ -2823,7 +2862,7 @@ static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorState = SD_OK; + HAL_SD_ErrorTypedef errorstate = SD_OK; while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) { @@ -2831,25 +2870,29 @@ static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd) if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) { - errorState = SD_CMD_RSP_TIMEOUT; + errorstate = SD_CMD_RSP_TIMEOUT; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - return errorState; + return errorstate; } else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) { - errorState = SD_CMD_CRC_FAIL; + errorstate = SD_CMD_CRC_FAIL; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - return errorState; + return errorstate; } + else + { + /* No error flag set */ + } /* Clear all the static flags */ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - return errorState; + return errorstate; } /** @@ -2862,8 +2905,8 @@ static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA) { - HAL_SD_ErrorTypedef errorState = SD_OK; - uint32_t response_R1; + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t response_r1; while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) { @@ -2871,58 +2914,62 @@ static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CM if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) { - errorState = SD_CMD_RSP_TIMEOUT; + errorstate = SD_CMD_RSP_TIMEOUT; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - return errorState; + return errorstate; } else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) { - errorState = SD_CMD_CRC_FAIL; + errorstate = SD_CMD_CRC_FAIL; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - return errorState; + return errorstate; } + else + { + /* No error flag set */ + } /* Check response received is of desired command */ if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD) { - errorState = SD_ILLEGAL_CMD; + errorstate = SD_ILLEGAL_CMD; - return errorState; + return errorstate; } /* Clear all the static flags */ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); /* We have received response, retrieve it. */ - response_R1 = SDIO_GetResponse(SDIO_RESP1); + response_r1 = SDIO_GetResponse(SDIO_RESP1); - if((response_R1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO) + if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO) { - *pRCA = (uint16_t) (response_R1 >> 16); + *pRCA = (uint16_t) (response_r1 >> 16); - return errorState; + return errorstate; } - if((response_R1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR) + if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR) { return(SD_GENERAL_UNKNOWN_ERROR); } - if((response_R1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD) + if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD) { return(SD_ILLEGAL_CMD); } - if((response_R1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED) + if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED) { return(SD_COM_CRC_FAILED); } - return errorState; + return errorstate; } /** @@ -2932,65 +2979,65 @@ static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CM */ static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t scr[2] = {0, 0}; if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) { - errorState = SD_LOCK_UNLOCK_FAILED; + errorstate = SD_LOCK_UNLOCK_FAILED; - return errorState; + return errorstate; } /* Get SCR Register */ - errorState = SD_FindSCR(hsd, scr); + errorstate = SD_FindSCR(hsd, scr); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* If requested card supports wide bus operation */ if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ - SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16); - SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDIO_CmdInitStructure.Argument = 2; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 2; + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } - return errorState; + return errorstate; } else { - errorState = SD_REQUEST_NOT_APPLICABLE; + errorstate = SD_REQUEST_NOT_APPLICABLE; - return errorState; + return errorstate; } } @@ -3001,65 +3048,65 @@ static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t scr[2] = {0, 0}; if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) { - errorState = SD_LOCK_UNLOCK_FAILED; + errorstate = SD_LOCK_UNLOCK_FAILED; - return errorState; + return errorstate; } /* Get SCR Register */ - errorState = SD_FindSCR(hsd, scr); + errorstate = SD_FindSCR(hsd, scr); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* If requested card supports 1 bit mode operation */ if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16); - SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } - return errorState; + return errorstate; } else { - errorState = SD_REQUEST_NOT_APPLICABLE; + errorstate = SD_REQUEST_NOT_APPLICABLE; - return errorState; + return errorstate; } } @@ -3072,60 +3119,60 @@ static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd) */ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - SDIO_DataInitTypeDef SDIO_DataInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t index = 0; uint32_t tempscr[2] = {0, 0}; /* Set Block Size To 8 Bytes */ /* Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.Argument = (uint32_t)8; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)8; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } /* Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.Argument = (uint32_t)((hsd->RCA) << 16); - SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } - SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.DataLength = 8; - SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B; - SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure); + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = 8; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - SDIO_CmdInitStructure.Argument = 0; - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR); - if(errorState != SD_OK) + if(errorstate != SD_OK) { - return errorState; + return errorstate; } while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) @@ -3141,33 +3188,37 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - errorState = SD_DATA_TIMEOUT; + errorstate = SD_DATA_TIMEOUT; - return errorState; + return errorstate; } else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - errorState = SD_DATA_CRC_FAIL; + errorstate = SD_DATA_CRC_FAIL; - return errorState; + return errorstate; } else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - errorState = SD_RX_OVERRUN; + errorstate = SD_RX_OVERRUN; - return errorState; + return errorstate; } else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) { __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - errorState = SD_START_BIT_ERR; + errorstate = SD_START_BIT_ERR; - return errorState; + return errorstate; + } + else + { + /* No error flag set */ } /* Clear all the static flags */ @@ -3179,7 +3230,7 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\ ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - return errorState; + return errorstate; } /** @@ -3190,16 +3241,16 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) */ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus) { - SDIO_CmdInitTypeDef SDIO_CmdInitStructure; - HAL_SD_ErrorTypedef errorState = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; __IO uint32_t responseR1 = 0; - SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16); - SDIO_CmdInitStructure.CmdIndex = SD_CMD_SEND_STATUS; - SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT; - SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO; - SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) { @@ -3207,27 +3258,31 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t * if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) { - errorState = SD_CMD_RSP_TIMEOUT; + errorstate = SD_CMD_RSP_TIMEOUT; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - return errorState; + return errorstate; } else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) { - errorState = SD_CMD_CRC_FAIL; + errorstate = SD_CMD_CRC_FAIL; __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - return errorState; + return errorstate; + } + else + { + /* No error flag set */ } /* Check response received is of desired command */ if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS) { - errorState = SD_ILLEGAL_CMD; + errorstate = SD_ILLEGAL_CMD; - return errorState; + return errorstate; } /* Clear all the static flags */ @@ -3242,7 +3297,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t * if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) { - return errorState; + return errorstate; } if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) @@ -3340,7 +3395,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t * return(SD_AKE_SEQ_ERROR); } - return errorState; + return errorstate; } /** diff --git a/stmhal/hal/src/stm32f4xx_hal_sdram.c b/stmhal/hal/src/stm32f4xx_hal_sdram.c index a6ebf485f..e45a765a5 100644 --- a/stmhal/hal/src/stm32f4xx_hal_sdram.c +++ b/stmhal/hal/src/stm32f4xx_hal_sdram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sdram.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief SDRAM HAL module driver. * This file provides a generic firmware to drive SDRAM memories mounted * as external device. @@ -20,7 +20,7 @@ with SDRAM memories: (#) Declare a SDRAM_HandleTypeDef handle structure, for example: - SDRAM_HandleTypeDef hdsram; and: + SDRAM_HandleTypeDef hdsram (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed values of the structure member. @@ -133,7 +133,8 @@ /** * @brief Performs the SDRAM device initialization sequence. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param Timing: Pointer to SDRAM control timing structure * @retval HAL status */ @@ -168,7 +169,8 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy /** * @brief Perform the SDRAM device initialization sequence. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) @@ -190,7 +192,8 @@ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM MSP Init. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval None */ __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) @@ -202,7 +205,8 @@ __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM MSP DeInit. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval None */ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) @@ -214,7 +218,8 @@ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) /** * @brief This function handles SDRAM refresh error interrupt request. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval HAL status */ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) @@ -232,7 +237,8 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM Refresh error callback. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval None */ __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) @@ -244,7 +250,8 @@ __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) /** * @brief DMA transfer complete callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) @@ -286,7 +293,8 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief Reads 8-bit data buffer from the SDRAM memory. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory @@ -326,7 +334,8 @@ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddr /** * @brief Writes 8-bit data buffer to SDRAM memory. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory @@ -369,7 +378,8 @@ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Reads 16-bit data buffer from the SDRAM memory. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory @@ -408,7 +418,8 @@ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes 16-bit data buffer to SDRAM memory. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory @@ -450,7 +461,8 @@ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Reads 32-bit data buffer from the SDRAM memory. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory @@ -489,7 +501,8 @@ HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes 32-bit data buffer to SDRAM memory. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory @@ -531,7 +544,8 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Reads a Words data from the SDRAM memory using DMA transfer. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory @@ -571,7 +585,8 @@ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory @@ -630,7 +645,8 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Enables dynamically SDRAM write protection. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) @@ -655,7 +671,8 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) /** * @brief Disables dynamically SDRAM write protection. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) @@ -680,10 +697,11 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) /** * @brief Sends Command to the SDRAM bank. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param Command: SDRAM command structure * @param Timeout: Timeout duration - * @retval HAL state + * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { @@ -714,9 +732,10 @@ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_C /** * @brief Programs the SDRAM Memory Refresh rate. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param RefreshRate: The SDRAM refresh rate value - * @retval HAL state + * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) { @@ -740,9 +759,10 @@ HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint /** * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @param AutoRefreshNumber: The SDRAM auto Refresh number - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) { @@ -766,7 +786,8 @@ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, ui /** * @brief Returns the SDRAM memory current mode. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval The SDRAM memory mode. */ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) @@ -796,7 +817,8 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) /** * @brief Returns the SDRAM state. - * @param hsdram: SDRAM handle + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. * @retval HAL state */ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) diff --git a/stmhal/hal/src/stm32f4xx_hal_smartcard.c b/stmhal/hal/src/stm32f4xx_hal_smartcard.c index 3a93ac7c7..73bb80fb8 100644 --- a/stmhal/hal/src/stm32f4xx_hal_smartcard.c +++ b/stmhal/hal/src/stm32f4xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_smartcard.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -16,10 +16,10 @@ ##### How to use this driver ##### ============================================================================== [..] - The SMARTCARD HAL driver can be used as follow: + The SMARTCARD HAL driver can be used as follows: (#) Declare a SMARTCARD_HandleTypeDef handle structure. - (#) Initialize the SMARTCARD low level resources by implement the HAL_SMARTCARD_MspInit ()API: + (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: (##) Enable the USARTx interface clock. (##) SMARTCARD pins configuration: (+++) Enable the clock for the SMARTCARD GPIOs. @@ -28,10 +28,6 @@ and HAL_SMARTCARD_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. - - -@@- The specific SMARTCARD interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __SMARTCARD_ENABLE_IT() and __SMARTCARD_DISABLE_IT() inside the transmit and receive process. (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() and HAL_SMARTCARD_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx stream. @@ -42,13 +38,18 @@ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream. (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the hsc Init structure. + flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API: - (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SMARTCARD_MspInit(&hsc) API. - - (#) Three mode of operations are available within this driver : + (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SMARTCARD_MspInit() API. + [..] + (@) The specific SMARTCARD interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __SMARTCARD_ENABLE_IT() and __SMARTCARD_DISABLE_IT() inside the transmit and receive process. + + [..] + Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -87,10 +88,10 @@ (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral - (+) __HAL_SMARTCARD_GET_FLAG : Checks whether the specified SMARTCARD flag is set or not - (+) __HAL_SMARTCARD_CLEAR_FLAG : Clears the specified SMARTCARD pending flag - (+) __HAL_SMARTCARD_ENABLE_IT: Enables the specified SMARTCARD interrupt - (+) __HAL_SMARTCARD_DISABLE_IT: Disables the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not + (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag + (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt [..] (@) You can refer to the SMARTCARD HAL driver header file for more useful macros @@ -182,18 +183,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible SmartCard frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ + please refer to Reference manual for possible SMARTDARD frame formats. (++) USART polarity (++) USART phase (++) USART LastBit @@ -225,7 +215,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /** * @brief Initializes the SmartCard mode according to the specified * parameters in the SMARTCARD_InitTypeDef and create the associated handle . - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) @@ -287,7 +278,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) /** * @brief DeInitializes the USART SmartCard peripheral - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) @@ -317,7 +309,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /** * @brief SMARTCARD MSP Init - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc) @@ -329,7 +322,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /** * @brief SMARTCARD MSP DeInit - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) @@ -358,33 +352,33 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. - (#) There are two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. + (++) Non Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected + will be executed respectivelly at the end of the Transmit or Receive process + The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected - (#) Blocking mode API's are : + (#) Blocking mode APIs are : (++) HAL_SMARTCARD_Transmit() (++) HAL_SMARTCARD_Receive() - (#) Non-Blocking mode API's with Interrupt are : + (#) Non Blocking mode APIs with Interrupt are : (++) HAL_SMARTCARD_Transmit_IT() (++) HAL_SMARTCARD_Receive_IT() (++) HAL_SMARTCARD_IRQHandler() - (#) No-Blocking mode functions with DMA are : + (#) Non Blocking mode functions with DMA are : (++) HAL_SMARTCARD_Transmit_DMA() (++) HAL_SMARTCARD_Receive_DMA() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SMARTCARD_TxCpltCallback() (++) HAL_SMARTCARD_RxCpltCallback() (++) HAL_SMARTCARD_ErrorCallback() @@ -395,16 +389,20 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /** * @brief Send an amount of data in blocking mode - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - - if(hsc->State == HAL_SMARTCARD_STATE_READY) + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) { if((pData == NULL) || (Size == 0)) { @@ -415,8 +413,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * __HAL_LOCK(hsc); hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + hsc->TxXferSize = Size; hsc->TxXferCount = Size; while(hsc->TxXferCount > 0) @@ -454,8 +460,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * return HAL_TIMEOUT; } - hsc->State = HAL_SMARTCARD_STATE_READY; - + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } /* Process Unlocked */ __HAL_UNLOCK(hsc); @@ -469,16 +482,20 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * /** * @brief Receive an amount of data in blocking mode - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @param pData: pointer to data buffer * @param Size: amount of data to be received + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - - if(hsc->State == HAL_SMARTCARD_STATE_READY) + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) { if((pData == NULL) || (Size == 0)) { @@ -489,7 +506,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p __HAL_LOCK(hsc); hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } hsc->RxXferSize = Size; hsc->RxXferCount = Size; @@ -531,7 +557,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p } } } - hsc->State = HAL_SMARTCARD_STATE_READY; + + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } /* Process Unlocked */ __HAL_UNLOCK(hsc); @@ -546,14 +581,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p /** * @brief Send an amount of data in non blocking mode - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - if(hsc->State == HAL_SMARTCARD_STATE_READY) + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) { if((pData == NULL) || (Size == 0)) { @@ -568,7 +607,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ hsc->TxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } /* Enable the SMARTCARD Parity Error Interrupt */ __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); @@ -579,8 +626,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ /* Process Unlocked */ __HAL_UNLOCK(hsc); - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC); + /* Enable the SMARTCARD Transmit data register empty Interrupt */ + __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE); return HAL_OK; } @@ -592,14 +639,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ /** * @brief Receive an amount of data in non blocking mode - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @param pData: pointer to data buffer * @param Size: amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - if(hsc->State == HAL_SMARTCARD_STATE_READY) + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) { if((pData == NULL) || (Size == 0)) { @@ -614,7 +665,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t hsc->RxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } /* Enable the SMARTCARD Data Register not empty Interrupt */ __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); @@ -638,7 +697,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t /** * @brief Send an amount of data in non blocking mode - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status @@ -646,10 +706,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - uint32_t tmpstate; + uint32_t tmp1 = 0; - tmpstate = hsc->State; - if((tmpstate == HAL_SMARTCARD_STATE_READY) || (tmpstate == HAL_SMARTCARD_STATE_BUSY_RX)) + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) { if((pData == NULL) || (Size == 0)) { @@ -664,7 +724,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 hsc->TxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } /* Set the SMARTCARD DMA transfert complete callback */ hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; @@ -693,7 +761,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 /** * @brief Receive an amount of data in non blocking mode - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @param pData: pointer to data buffer * @param Size: amount of data to be received * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s @@ -702,10 +771,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - uint32_t tmpstate; + uint32_t tmp1 = 0; - tmpstate = hsc->State; - if((tmpstate == HAL_SMARTCARD_STATE_READY) || (tmpstate == HAL_SMARTCARD_STATE_BUSY_TX)) + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) { if((pData == NULL) || (Size == 0)) { @@ -719,7 +788,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ hsc->RxXferSize = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } /* Set the SMARTCARD DMA transfert complete callback */ hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; @@ -748,65 +825,60 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ /** * @brief This function handles SMARTCARD interrupt request. - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) { uint32_t tmp1 = 0, tmp2 = 0; - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE); + tmp1 = hsc->Instance->SR; tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE); + /* SMARTCARD parity error interrupt occured --------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET)) { - __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_PE); + __HAL_SMARTCARD_CLEAR_PEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE); tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); /* SMARTCARD frame error interrupt occured ---------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET)) { - __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_FE); + __HAL_SMARTCARD_CLEAR_FEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE); tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); /* SMARTCARD noise error interrupt occured ---------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET)) { - __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_NE); + __HAL_SMARTCARD_CLEAR_NEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; } - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE); + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); /* SMARTCARD Over-Run interrupt occured ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET)) { - __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_ORE); + __HAL_SMARTCARD_CLEAR_OREFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE); tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE); /* SMARTCARD in mode Receiver ----------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if(((tmp1 & SMARTCARD_FLAG_RXNE) != RESET) && (tmp2 != RESET)) { SMARTCARD_Receive_IT(hsc); - __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_RXNE); } - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC); + + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE); /* SMARTCARD in mode Transmitter -------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if(((tmp1 & SMARTCARD_FLAG_TXE) != RESET) && (tmp2 != RESET)) { SMARTCARD_Transmit_IT(hsc); - __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC); } /* Call the Error call Back in case of Errors */ @@ -820,7 +892,8 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /** * @brief Tx Transfer completed callbacks - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc) @@ -832,7 +905,8 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /** * @brief Rx Transfer completed callbacks - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) @@ -844,7 +918,8 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) /** * @brief SMARTCARD error callbacks - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc) @@ -875,7 +950,8 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) /** * @brief return the SMARTCARD state - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL state */ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) @@ -900,7 +976,8 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) /** * @brief DMA SMARTCARD transmit process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -923,14 +1000,23 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) else { /* No Timeout */ - hsc->State= HAL_SMARTCARD_STATE_READY; + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } HAL_SMARTCARD_TxCpltCallback(hsc); } } /** * @brief DMA SMARTCARD receive process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -943,14 +1029,23 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) in the USART CR3 register */ hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - hsc->State= HAL_SMARTCARD_STATE_READY; - + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } + HAL_SMARTCARD_RxCpltCallback(hsc); } /** * @brief DMA SMARTCARD communication error callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) @@ -975,10 +1070,11 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t timeout = 0; - - timeout = HAL_GetTick() + Timeout; - + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until flag is set */ if(Status == RESET) { @@ -987,7 +1083,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE and RXNE interrupts for the interrupt process */ __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); @@ -1010,7 +1106,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE and RXNE interrupts for the interrupt process */ __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); @@ -1031,18 +1127,18 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /** * @brief Send an amount of data in non blocking mode - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) { uint16_t* tmp; - - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX)) { - /* Process Locked */ - __HAL_LOCK(hsc); - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) { tmp = (uint16_t*) hsc->pTxBuffPtr; @@ -1063,8 +1159,8 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) if(--hsc->TxXferCount == 0) { - /* Disable the SMARTCARD Transmit Complete Interrupt */ - __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TC); + /* Disable the SMARTCARD Transmit data register empty Interrupt */ + __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); /* Disable the SMARTCARD Parity Error Interrupt */ __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); @@ -1072,20 +1168,26 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); - hsc->State = HAL_SMARTCARD_STATE_READY; - - /* Call the Process Unlocked before calling the Tx call back API to give the possibiity to - start again the Transmission under the Tx call back API */ - __HAL_UNLOCK(hsc); - + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } + HAL_SMARTCARD_TxCpltCallback(hsc); return HAL_OK; } - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - return HAL_OK; } else @@ -1096,18 +1198,18 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) /** * @brief Receive an amount of data in non blocking mode - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) { uint16_t* tmp; - - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX)) { - /* Process Locked */ - __HAL_LOCK(hsc); - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) { tmp = (uint16_t*) hsc->pRxBuffPtr; @@ -1136,9 +1238,6 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) if(--hsc->RxXferCount == 0) { - while(HAL_IS_BIT_SET(hsc->Instance->SR, SMARTCARD_FLAG_RXNE)) - { - } __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); /* Disable the SMARTCARD Parity Error Interrupt */ @@ -1147,20 +1246,20 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); - hsc->State = HAL_SMARTCARD_STATE_READY; - - /* Call the Process Unlocked before calling the Rx call back API to give the possibiity to - start again the receiption under the Rx call back API */ - __HAL_UNLOCK(hsc); + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } HAL_SMARTCARD_RxCpltCallback(hsc); return HAL_OK; } - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - return HAL_OK; } else @@ -1171,7 +1270,8 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) /** * @brief Configure the SMARTCARD peripheral - * @param hsc: usart handle + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) diff --git a/stmhal/hal/src/stm32f4xx_hal_spi.c b/stmhal/hal/src/stm32f4xx_hal_spi.c index 4bf70f5af..226ec6254 100644 --- a/stmhal/hal/src/stm32f4xx_hal_spi.c +++ b/stmhal/hal/src/stm32f4xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief SPI HAL module driver. * * This file provides firmware functions to manage the following @@ -22,7 +22,7 @@ (#) Declare a SPI_HandleTypeDef handle structure, for example: SPI_HandleTypeDef hspi; - (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API: + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: (##) Enable the SPIx interface clock (##) SPI pins configuration (+++) Enable the clock for the SPI GPIOs @@ -43,7 +43,17 @@ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SPI_MspInit(&hspi) API. + by calling the customed HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + + @endverbatim ****************************************************************************** @@ -104,6 +114,9 @@ static void SPI_RxISR(SPI_HandleTypeDef *hspi); static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); @@ -123,7 +136,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin [..] This subsection provides a set of functions allowing to initialize and de-initialiaze the SPIx peripheral: - (+) User must Implement HAL_SPI_MspInit() function in which he configures + (+) User must implement HAL_SPI_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). (+) Call the function HAL_SPI_Init() to configure the selected device with @@ -149,7 +162,8 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin /** * @brief Initializes the SPI according to the specified parameters * in the SPI_InitTypeDef and create the associated handle. - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) @@ -209,7 +223,8 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief DeInitializes the SPI peripheral - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) @@ -237,7 +252,8 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief SPI MSP Init - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) @@ -249,7 +265,8 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief SPI MSP DeInit - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) @@ -275,12 +292,12 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) [..] The SPI supports master and slave mode : - (#) There are two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. + or DMA, These APIs return the HAL status. The end of the data processing will be indicated through the dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -288,23 +305,23 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) will be executed respectivelly at the end of the transmit or Receive process The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected - (#) Blocking mode API's are : + (#) Blocking mode APIs are : (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_TransmitReceive() in full duplex mode - (#) Non-Blocking mode API's with Interrupt are : + (#) Non Blocking mode API's with Interrupt are : (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_TransmitReceive_IT()in full duplex mode (++) HAL_SPI_IRQHandler() - (#) No-Blocking mode functions with DMA are : + (#) Non Blocking mode functions with DMA are : (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SPI_TxCpltCallback() (++) HAL_SPI_RxCpltCallback() (++) HAL_SPI_ErrorCallback() @@ -316,7 +333,8 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @param Timeout: Timeout duration @@ -374,10 +392,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 8 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) { - - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - + if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } while(hspi->TxXferCount > 0) { /* Wait until TXE flag is set to send data */ @@ -397,10 +416,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 16 Bit mode */ else { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - hspi->TxXferCount--; - + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } while(hspi->TxXferCount > 0) { /* Wait until TXE flag is set to send data */ @@ -454,7 +475,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /** * @brief Receive an amount of data in blocking mode - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @param Timeout: Timeout duration @@ -628,7 +650,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /** * @brief Transmit and Receive an amount of data in blocking mode - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer * @param pRxData: pointer to reception data buffer to be * @param Size: amount of data to be sent @@ -638,10 +661,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { __IO uint16_t tmpreg; - uint32_t tmp = 0; + uint32_t tmpstate = 0, tmp = 0; - tmp = hspi->State; - if((tmp == HAL_SPI_STATE_READY) || (tmp == HAL_SPI_STATE_BUSY_RX)) + tmpstate = hspi->State; + if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX)) { if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { @@ -691,10 +714,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Transmit and Receive data in 16 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - hspi->TxXferCount--; - + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } if(hspi->TxXferCount == 0) { /* Enable CRC Transmission */ @@ -738,30 +763,34 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { return HAL_TIMEOUT; } - + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr+=2; hspi->RxXferCount--; } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + /* Receive the last byte */ + if(hspi->Init.Mode == SPI_MODE_SLAVE) { - return HAL_TIMEOUT; + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - hspi->RxXferCount--; } } /* Transmit and Receive data in 8 Bit mode */ else { - - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } if(hspi->TxXferCount == 0) { /* Enable CRC Transmission */ @@ -798,24 +827,26 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; hspi->RxXferCount--; } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - hspi->RxXferCount--; } } @@ -873,7 +904,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /** * @brief Transmit an amount of data in no-blocking mode with Interrupt - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status @@ -947,7 +979,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /** * @brief Receive an amount of data in no-blocking mode with Interrupt - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status @@ -1025,7 +1058,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /** * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer * @param pRxData: pointer to reception data buffer to be * @param Size: amount of data to be sent @@ -1033,10 +1067,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t tmp = 0; + uint32_t tmpstate = 0; - tmp = hspi->State; - if((tmp == HAL_SPI_STATE_READY) || (tmp == HAL_SPI_STATE_BUSY_RX)) + tmpstate = hspi->State; + if((tmpstate == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX))) { if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { @@ -1050,7 +1085,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_LOCK(hspi); /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if(hspi->State == HAL_SPI_STATE_READY) + if(hspi->State != HAL_SPI_STATE_BUSY_RX) { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; } @@ -1097,7 +1132,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /** * @brief Transmit an amount of data in no-blocking mode with DMA - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status @@ -1143,6 +1179,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_RESET_CRC(hspi); } + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + /* Set the SPI TxDMA transfer complete callback */ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; @@ -1175,7 +1214,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /** * @brief Receive an amount of data in no-blocking mode with DMA - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pData: pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. * @param Size: amount of data to be sent @@ -1227,6 +1267,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_RESET_CRC(hspi); } + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + /* Set the SPI Rx DMA transfer complete callback */ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; @@ -1259,7 +1302,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /** * @brief Transmit and Receive an amount of data in no-blocking mode with DMA - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer * @param pRxData: pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 @@ -1270,7 +1314,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { uint32_t tmpstate = 0; tmpstate = hspi->State; - if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX)) + if((tmpstate == HAL_SPI_STATE_READY) || ((hspi->Init.Mode == SPI_MODE_MASTER) && \ + (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX))) { if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { @@ -1284,7 +1329,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * __HAL_LOCK(hspi); /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if(hspi->State == HAL_SPI_STATE_READY) + if(hspi->State != HAL_SPI_STATE_BUSY_RX) { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; } @@ -1313,10 +1358,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ if(hspi->State == HAL_SPI_STATE_BUSY_RX) { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; } else { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; } @@ -1339,19 +1390,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable the Tx DMA Stream */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - /* Enable Tx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + /* Enable Tx DMA Request */ + hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); return HAL_OK; } else @@ -1360,9 +1410,87 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } } + +/** + * @brief Pauses the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; + hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream */ + if(hspi->hdmatx != NULL) + { + HAL_DMA_Abort(hspi->hdmatx); + } + /* Abort the SPI DMA rx Stream */ + if(hspi->hdmarx != NULL) + { + HAL_DMA_Abort(hspi->hdmarx); + } + + /* Disable the SPI DMA Tx & Rx requests */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); + + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + /** * @brief This function handles SPI interrupt request. - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval HAL status */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) @@ -1390,20 +1518,20 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) { - /* SPI CRC error interrupt occured ---------------------------------------*/ + /* SPI CRC error interrupt occurred ---------------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->ErrorCode |= HAL_SPI_ERROR_CRC; __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } - /* SPI Mode Fault error interrupt occured --------------------------------*/ + /* SPI Mode Fault error interrupt occurred --------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) { hspi->ErrorCode |= HAL_SPI_ERROR_MODF; __HAL_SPI_CLEAR_MODFFLAG(hspi); } - /* SPI Overrun error interrupt occured -----------------------------------*/ + /* SPI Overrun error interrupt occurred -----------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) { if(hspi->State != HAL_SPI_STATE_BUSY_TX) @@ -1413,7 +1541,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } } - /* SPI Frame error interrupt occured -------------------------------------*/ + /* SPI Frame error interrupt occurred -------------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) { hspi->ErrorCode |= HAL_SPI_ERROR_FRE; @@ -1431,7 +1559,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /** * @brief Tx Transfer completed callbacks - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) @@ -1443,7 +1572,8 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Transfer completed callbacks - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) @@ -1455,7 +1585,8 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Transfer completed callbacks - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) @@ -1465,9 +1596,49 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) */ } +/** + * @brief Tx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file + */ +} + /** * @brief SPI error callbacks - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) @@ -1475,7 +1646,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* NOTE : - This function Should not be modified, when the callback is needed, the HAL_SPI_ErrorCallback() could be implenetd in the user file. - The ErrorCode parameter in the hspi handle is updated by the SPI processes - and user can use HAL_SPI_GetError() API to check the latest error occured. + and user can use HAL_SPI_GetError() API to check the latest error occurred. */ } @@ -1500,8 +1671,9 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI state - * @param hspi : SPI handle - * @retval SPI state + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL state */ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) { @@ -1510,7 +1682,8 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code - * @param hspi : SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval SPI Error Code */ HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi) @@ -1524,7 +1697,8 @@ HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi) /** * @brief Interrupt Handler to close Tx transfer - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval void */ static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) @@ -1584,7 +1758,8 @@ static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) /** * @brief Interrupt Handler to transmit amount of data in no-blocking mode - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval void */ static void SPI_TxISR(SPI_HandleTypeDef *hspi) @@ -1615,7 +1790,8 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi) /** * @brief Interrupt Handler to close Rx transfer - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval void */ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) @@ -1674,7 +1850,8 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) /* Set state to READY before run the Callback Complete */ hspi->State = HAL_SPI_STATE_READY; HAL_SPI_TxRxCpltCallback(hspi); - }else + } + else { /* Set state to READY before run the Callback Complete */ hspi->State = HAL_SPI_STATE_READY; @@ -1693,7 +1870,8 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) /** * @brief Interrupt Handler to receive amount of data in 2Lines mode - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval void */ static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) @@ -1719,7 +1897,8 @@ static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) /** * @brief Interrupt Handler to receive amount of data in no-blocking mode - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval void */ static void SPI_RxISR(SPI_HandleTypeDef *hspi) @@ -1752,36 +1931,40 @@ static void SPI_RxISR(SPI_HandleTypeDef *hspi) /** * @brief DMA SPI transmit process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + /* DMA Normal Mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + } + /* Disable Tx DMA Request */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + } + + hspi->TxXferCount = 0; + + hspi->State = HAL_SPI_STATE_READY; } - /* Disable Tx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - } - - hspi->TxXferCount = 0; - - hspi->State = HAL_SPI_STATE_READY; - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { - __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_OVRFLAG(hspi); } /* Check if Errors has been detected during transfer */ @@ -1797,58 +1980,69 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI receive process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { __IO uint16_t tmpreg; - + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Disable Rx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - /* Wait until RXNE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); } - - /* Read CRC */ - tmpreg = hspi->Instance->DR; - (void)tmpreg; // suppress compiler warning - - /* Wait until RXNE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + + /* Disable Rx DMA Request */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); + /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + } + + /* Read CRC */ + tmpreg = hspi->Instance->DR; + (void)tmpreg; // suppress compiler warning + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } } - } - - hspi->RxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } } else { @@ -1858,65 +2052,73 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { __IO uint16_t tmpreg; - + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) { - /* Check if CRC is done on going (RXNE flag set) */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) { - /* Wait until RXNE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + /* Check if CRC is done on going (RXNE flag set) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + } + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + (void)tmpreg; // suppress compiler warning + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } } - /* Read CRC */ - tmpreg = hspi->Instance->DR; - (void)tmpreg; // suppress compiler warning - } - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - } - /* Disable Tx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - } - - /* Disable Rx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; - - hspi->State = HAL_SPI_STATE_READY; - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + } + /* Disable Tx DMA Request */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + } + + /* Disable Rx DMA Request */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + + hspi->State = HAL_SPI_STATE_READY; + + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } } else { @@ -1924,9 +2126,49 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } } +/** + * @brief DMA SPI half transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_RxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI Half transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxRxHalfCpltCallback(hspi); +} + /** * @brief DMA SPI communication error callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) @@ -1941,14 +2183,16 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles SPI Communication Timeout. - * @param hspi: SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait until flag is set */ if(Status == RESET) @@ -1957,7 +2201,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -1991,7 +2235,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master diff --git a/stmhal/hal/src/stm32f4xx_hal_sram.c b/stmhal/hal/src/stm32f4xx_hal_sram.c index 59b48d76d..6d9369d3d 100644 --- a/stmhal/hal/src/stm32f4xx_hal_sram.c +++ b/stmhal/hal/src/stm32f4xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sram.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -134,7 +134,8 @@ /** * @brief Performs the SRAM device initialization sequence - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param Timing: Pointer to SRAM control timing structure * @param ExtTiming: Pointer to SRAM extended mode timing structure * @retval HAL status @@ -170,7 +171,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp /** * @brief Performs the SRAM device De-initialization sequence. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) @@ -191,7 +193,8 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) /** * @brief SRAM MSP Init. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @retval None */ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) @@ -203,7 +206,8 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) /** * @brief SRAM MSP DeInit. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @retval None */ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) @@ -215,8 +219,9 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) /** * @brief DMA transfer complete callback. - * @param hsram: pointer to SRAM handle - * @retval none + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None */ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) { @@ -227,8 +232,9 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete error callback. - * @param hsram: pointer to SRAM handle - * @retval none + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None */ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) { @@ -257,7 +263,8 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief Reads 8-bit buffer from SRAM memory. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory @@ -292,7 +299,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress /** * @brief Writes 8-bit buffer to SRAM memory. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory @@ -333,7 +341,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Reads 16-bit buffer from SRAM memory. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory @@ -368,7 +377,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes 16-bit buffer to SRAM memory. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory @@ -409,7 +419,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Reads 32-bit buffer from SRAM memory. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory @@ -442,7 +453,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes 32-bit buffer to SRAM memory. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory @@ -481,7 +493,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Reads a Words data from the SRAM memory using DMA transfer. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory @@ -513,7 +526,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes a Words data buffer to SRAM memory using DMA transfer. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory @@ -570,7 +584,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Enables dynamically SRAM write operation. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) @@ -592,7 +607,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) /** * @brief Disables dynamically SRAM write operation. - * @param hsram: pointer to SRAM handle + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) @@ -636,8 +652,9 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) /** * @brief Returns the SRAM controller state - * @param hsram: pointer to SRAM handle - * @retval SRAM controller state + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL state */ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) { diff --git a/stmhal/hal/src/stm32f4xx_hal_tim.c b/stmhal/hal/src/stm32f4xx_hal_tim.c index 19e7bdcde..fc0255c01 100644 --- a/stmhal/hal/src/stm32f4xx_hal_tim.c +++ b/stmhal/hal/src/stm32f4xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -193,7 +193,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM Base handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) @@ -229,7 +230,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM Base peripheral - * @param htim: TIM Base handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) @@ -256,7 +258,8 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) @@ -268,7 +271,8 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Base MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) @@ -280,7 +284,8 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) @@ -303,7 +308,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) @@ -326,7 +332,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) @@ -346,7 +353,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) @@ -365,7 +373,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param pData: The source Buffer address. * @param Length: The length of data to be transferred from memory to peripheral. * @retval HAL status @@ -411,7 +420,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) @@ -460,7 +470,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM Output Compare handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) @@ -496,7 +507,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: TIM Output Compare handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) @@ -523,7 +535,8 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -535,7 +548,8 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) @@ -547,8 +561,9 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -579,8 +594,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -611,8 +627,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -677,8 +694,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -743,8 +761,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -862,8 +881,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -957,7 +977,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) @@ -993,7 +1014,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) @@ -1020,7 +1042,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) @@ -1032,7 +1055,8 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM PWM MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) @@ -1044,8 +1068,9 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1076,8 +1101,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1111,8 +1137,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1177,8 +1204,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1243,8 +1271,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1362,8 +1391,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1457,7 +1487,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM Input Capture handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) @@ -1493,7 +1524,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: TIM Input Capture handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) @@ -1520,7 +1552,8 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM INput Capture MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) @@ -1532,7 +1565,8 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Input Capture MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) @@ -1544,8 +1578,9 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param hdma : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1570,8 +1605,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1596,8 +1632,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param hdma : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1655,8 +1692,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1715,8 +1753,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1830,8 +1869,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1919,7 +1959,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM OnePulse handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param OnePulseMode: Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. @@ -1966,7 +2007,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitializes the TIM One Pulse - * @param htim: TIM One Pulse handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) @@ -1993,7 +2035,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) @@ -2005,7 +2048,8 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM One Pulse MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) @@ -2017,8 +2061,9 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param OutputChannel : TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2050,8 +2095,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be disable + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param OutputChannel : TIM Channels to be disable. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2083,8 +2129,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param OutputChannel : TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2122,8 +2169,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param OutputChannel : TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2185,7 +2233,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim: TIM Encoder Interface handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sConfig: TIM Encoder Interface configuration structure * @retval HAL status */ @@ -2272,7 +2321,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitializes the TIM Encoder interface - * @param htim: TIM Encoder handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) @@ -2299,7 +2349,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) @@ -2311,7 +2362,8 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) @@ -2323,8 +2375,9 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2364,8 +2417,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2406,8 +2460,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2453,8 +2508,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2503,8 +2559,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2622,8 +2679,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2688,7 +2746,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) @@ -2746,7 +2805,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR2_CC3S) != 0x00) + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2767,7 +2826,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR2_CC4S) != 0x00) + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2844,9 +2903,10 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM Output Compare handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sConfig: TIM Output Compare configuration structure - * @param Channel : TIM Channels to be enabled + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2917,9 +2977,10 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: TIM IC handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sConfig: TIM Input Capture configuration structure - * @param Channel : TIM Channels to be enabled + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3013,9 +3074,10 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sConfig: TIM PWM configuration structure - * @param Channel : TIM Channels to be enabled + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3113,13 +3175,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: TIM One Pulse handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel : TIM Channels to be enabled + * @param OutputChannel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel : TIM Channels to be enabled + * @param InputChannel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3225,8 +3288,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. * This parameters can be on of the following values: * @arg TIM_DMABase_CR1 * @arg TIM_DMABase_CR2 @@ -3247,7 +3311,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABase_CCR4 * @arg TIM_DMABase_BDTR * @arg TIM_DMABase_DCR - * @param BurstRequestSrc: TIM DMA Request sources + * @param BurstRequestSrc: TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3258,7 +3322,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer: The Buffer address. * @param BurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -3388,7 +3452,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param BurstRequestSrc: TIM DMA Request sources to disable * @retval HAL status */ @@ -3406,8 +3471,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. * This parameters can be on of the following values: * @arg TIM_DMABase_CR1 * @arg TIM_DMABase_CR2 @@ -3428,7 +3494,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABase_CCR4 * @arg TIM_DMABase_BDTR * @arg TIM_DMABase_DCR - * @param BurstRequestSrc: TIM DMA Request sources + * @param BurstRequestSrc: TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3439,7 +3505,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer: The Buffer address. * @param BurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -3570,7 +3636,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param BurstRequestSrc: TIM DMA Request sources to disable. * @retval HAL status */ @@ -3588,7 +3655,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param EventSource: specifies the event source. * This parameter can be one of the following values: * @arg TIM_EventSource_Update: Timer update Event source @@ -3630,15 +3698,16 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel + * @param Channel: specifies the TIM Channel. * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) @@ -3738,7 +3807,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp /** * @brief Configures the clock source to be used - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status @@ -3871,7 +3941,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: TIM handle. + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module.. * @param TI1_Selection: Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: @@ -3905,7 +3976,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim: TIM handle. + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module.. * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave @@ -4052,8 +4124,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI /** * @brief Read the captured value from Capture Compare unit - * @param htim: TIM handle. - * @param Channel : TIM Channels to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module.. + * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -4145,7 +4218,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non blocking mode - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) @@ -4157,7 +4231,8 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Output Compare callback in non blocking mode - * @param htim : TIM OC handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) @@ -4168,7 +4243,8 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Input Capture callback in non blocking mode - * @param htim : TIM IC handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) @@ -4180,7 +4256,8 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non blocking mode - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) @@ -4192,7 +4269,8 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non blocking mode - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) @@ -4204,7 +4282,8 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non blocking mode - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) @@ -4226,7 +4305,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) ##### Peripheral State functions ##### ============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -4235,7 +4314,8 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base state - * @param htim: TIM Base handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) @@ -4245,7 +4325,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC state - * @param htim: TIM Ouput Compare handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) @@ -4255,7 +4336,8 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM state - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) @@ -4265,7 +4347,8 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture state - * @param htim: TIM IC handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) @@ -4275,7 +4358,8 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode state - * @param htim: TIM OPM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) @@ -4285,7 +4369,8 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode state - * @param htim: TIM Encoder handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) @@ -4299,7 +4384,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA error callback - * @param hdma : pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) @@ -4313,7 +4399,8 @@ void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) @@ -4326,7 +4413,8 @@ void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) } /** * @brief TIM DMA Capture complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) @@ -4341,7 +4429,8 @@ void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) @@ -4355,7 +4444,8 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma : pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) diff --git a/stmhal/hal/src/stm32f4xx_hal_tim_ex.c b/stmhal/hal/src/stm32f4xx_hal_tim_ex.c index ac74ac533..32cef39d8 100644 --- a/stmhal/hal/src/stm32f4xx_hal_tim_ex.c +++ b/stmhal/hal/src/stm32f4xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -145,7 +145,8 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim: TIM Encoder Interface handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sConfig: TIM Hall Sensor configuration structure * @retval HAL status */ @@ -218,7 +219,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitializes the TIM Hall Sensor interface - * @param htim: TIM Hall Sensor handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) @@ -245,7 +247,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) @@ -257,7 +260,8 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) @@ -269,7 +273,8 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) @@ -290,7 +295,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) @@ -311,7 +317,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM Hall Sensor handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) @@ -335,7 +342,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) @@ -359,7 +367,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM Hall Sensor handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from TIM peripheral to memory. * @retval HAL status @@ -408,7 +417,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) @@ -458,13 +468,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -488,13 +499,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -518,13 +530,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -582,13 +595,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -646,13 +660,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @param pData: The source Buffer address. * @param Length: The length of data to be transferred from memory to TIM peripheral * @retval HAL status @@ -763,13 +778,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -863,13 +879,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -892,13 +909,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -922,13 +940,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -989,13 +1008,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1056,13 +1076,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @param pData: The source Buffer address. * @param Length: The length of data to be transferred from memory to TIM peripheral * @retval HAL status @@ -1173,13 +1194,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * TIM_CHANNEL_1/ + * TIM_CHANNEL_2/ + * TIM_CHANNEL_3/ + * TIM_CHANNEL_4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1262,11 +1284,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complemetary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param OutputChannel: TIM Channel to be enabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * TIM_CHANNEL_1 / + * IM_CHANNEL_2 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -1287,11 +1310,11 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param OutputChannel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * TIM_CHANNEL_1 / TIM_CHANNEL_2 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -1316,11 +1339,11 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param OutputChannel: TIM Channel to be enabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * TIM_CHANNEL_1 / IM_CHANNEL_2 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -1347,11 +1370,11 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param OutputChannel: TIM Channel to be disabled. * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * TIM_CHANNEL_1 / IM_CHANNEL_2 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -1402,21 +1425,22 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t */ /** * @brief Configure the TIM commutation event sequence. - * @note: this function is mandatory to use the commutation event in order to + * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * TIM_TS_ITR0 / + * TIM_TS_ITR1 / + * TIM_TS_ITR2 / + * TIM_TS_ITR3 / + * TIM_TS_NONE + * @param CommutationSource: the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1451,21 +1475,22 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint /** * @brief Configure the TIM commutation event sequence with interrupt. - * @note: this function is mandatory to use the commutation event in order to + * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * TIM_TS_ITR0 / + * TIM_TS_ITR1 / + * TIM_TS_ITR2 / + * TIM_TS_ITR3 / + * TIM_TS_NONE + * @param CommutationSource: the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1503,22 +1528,23 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u /** * @brief Configure the TIM commutation event sequence with DMA. - * @note: this function is mandatory to use the commutation event in order to + * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * TIM_TS_ITR0 / + * TIM_TS_ITR1 / + * TIM_TS_ITR2 / + * TIM_TS_ITR3 / + * TIM_TS_NONE + * @param CommutationSource: the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1562,7 +1588,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim: TIM handle. + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. @@ -1599,7 +1626,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim: TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status @@ -1641,7 +1669,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param htim: TIM handle. + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module.. * @param TIM_Remap: specifies the TIM input remapping source. * This parameter can be one of the following values: * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) @@ -1697,7 +1726,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /** * @brief Hall commutation changed callback in non blocking mode - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) @@ -1709,7 +1739,8 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non blocking mode - * @param htim : TIM handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) @@ -1731,7 +1762,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) ##### Extension Peripheral State functions ##### ============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1740,7 +1771,8 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Hall Sensor interface state - * @param htim: TIM Hall Sensor handle + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) @@ -1754,7 +1786,8 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma : pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) diff --git a/stmhal/hal/src/stm32f4xx_hal_uart.c b/stmhal/hal/src/stm32f4xx_hal_uart.c index a54af3ffa..1ee095143 100644 --- a/stmhal/hal/src/stm32f4xx_hal_uart.c +++ b/stmhal/hal/src/stm32f4xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -21,7 +21,7 @@ (#) Declare a UART_HandleTypeDef handle structure. - (#) Initialize the UART low level resources by implement the HAL_UART_MspInit() API: + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: (##) Enable the USARTx interface clock. (##) UART pins configuration: (+++) Enable the clock for the UART GPIOs. @@ -42,7 +42,7 @@ interrupt on the DMA Tx/Rx Stream. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the huart Init structure. + flow control and Mode(Receiver/Transmitter) in the Init structure. (#) For the UART asynchronous mode, initialize the UART registers by calling the HAL_UART_Init() API. @@ -55,16 +55,19 @@ (#) For the Multi-Processor mode, initialize the UART registers by calling the HAL_MultiProcessor_Init() API. - -@- The specific UART interrupts (Transmission complete interrupt, + [..] + (@) The specific UART interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive process. - -@- These API's(HAL_UART_Init() and HAL_HalfDuplex_Init()) configures also the + [..] + (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed HAL_UART_MspInit() API. - (#) Three mode of operations are available within this driver : + [..] + Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -84,7 +87,7 @@ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback + add his own code by customization of function pointer HAL_UART_RxCpltCallback (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_UART_ErrorCallback @@ -100,7 +103,7 @@ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback + add his own code by customization of function pointer HAL_UART_RxCpltCallback (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_UART_ErrorCallback (+) Pause the DMA Transfer using HAL_UART_DMAPause() @@ -114,10 +117,10 @@ (+) __HAL_UART_ENABLE: Enable the UART peripheral (+) __HAL_UART_DISABLE: Disable the UART peripheral - (+) __HAL_UART_GET_FLAG : Checks whether the specified UART flag is set or not - (+) __HAL_UART_CLEAR_FLAG : Clears the specified UART pending flag - (+) __HAL_UART_ENABLE_IT: Enables the specified UART interrupt - (+) __HAL_UART_DISABLE_IT: Disables the specified UART interrupt + (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not + (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag + (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt + (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt [..] (@) You can refer to the UART HAL driver header file for more useful macros @@ -205,18 +208,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | UART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ + please refer to Reference manual for possible UART frame formats. (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Methode @@ -232,7 +224,8 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, /** * @brief Initializes the UART mode according to the specified parameters in * the UART_InitTypeDef and create the associated handle. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) @@ -259,9 +252,9 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Init the low level hardware */ HAL_UART_MspInit(huart); } - - huart->State = HAL_UART_STATE_BUSY; - + + huart->State = HAL_UART_STATE_BUSY; + /* Disable the peripheral */ __HAL_UART_DISABLE(huart); @@ -287,7 +280,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the half-duplex mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) @@ -303,7 +297,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Init the low level hardware */ HAL_UART_MspInit(huart); } - + + huart->State = HAL_UART_STATE_BUSY; + /* Disable the peripheral */ __HAL_UART_DISABLE(huart); @@ -332,7 +328,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the LIN mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param BreakDetectLength: Specifies the LIN break detection length. * This parameter can be one of the following values: * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection @@ -354,7 +351,9 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Init the low level hardware */ HAL_UART_MspInit(huart); } - + + huart->State = HAL_UART_STATE_BUSY; + /* Disable the peripheral */ __HAL_UART_DISABLE(huart); @@ -387,7 +386,8 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initializes the Multi-Processor mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param Address: USART address * @param WakeUpMethode: specifies the USART wakeup method. * This parameter can be one of the following values: @@ -412,7 +412,9 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Init the low level hardware */ HAL_UART_MspInit(huart); } - + + huart->State = HAL_UART_STATE_BUSY; + /* Disable the peripheral */ __HAL_UART_DISABLE(huart); @@ -446,7 +448,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /** * @brief DeInitializes the UART peripheral. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @@ -476,7 +479,8 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief UART MSP Init. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) @@ -488,7 +492,8 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief UART MSP DeInit. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) @@ -517,7 +522,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) Non-Blocking mode: The communication is performed using Interrupts + (++) Non blocking mode: The communication is performed using Interrupts or DMA, these APIs return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when @@ -527,20 +532,20 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback() user callback will be executed when a communication error is detected. - (#) Blocking mode API's are: + (#) Blocking mode APIs are: (++) HAL_UART_Transmit() (++) HAL_UART_Receive() - (#) Non-Blocking mode API's with Interrupt are: + (#) Non Blocking mode APIs with Interrupt are: (++) HAL_UART_Transmit_IT() (++) HAL_UART_Receive_IT() (++) HAL_UART_IRQHandler() - (#) No-Blocking mode functions with DMA are: + (#) Non Blocking mode functions with DMA are: (++) HAL_UART_Transmit_DMA() (++) HAL_UART_Receive_DMA() - (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non blocking mode: (++) HAL_UART_TxCpltCallback() (++) HAL_UART_RxCpltCallback() (++) HAL_UART_ErrorCallback() @@ -556,7 +561,8 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief Sends an amount of data in blocking mode. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -649,7 +655,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receives an amount of data in blocking mode. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @param Timeout: Timeout duration @@ -748,7 +755,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Sends an amount of data in non blocking mode. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -792,8 +800,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /* Process Unlocked */ __HAL_UNLOCK(huart); - /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + /* Enable the UART Transmit data register empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); return HAL_OK; } @@ -805,7 +813,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receives an amount of data in non blocking mode - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @retval HAL status @@ -862,7 +871,8 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Sends an amount of data in non blocking mode. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -928,7 +938,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receives an amount of data in non blocking mode. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit. @@ -954,7 +965,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData huart->RxXferSize = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit rocess is ongoing or not */ + /* Check if a transmit process is ongoing or not */ if(huart->State == HAL_UART_STATE_BUSY_TX) { huart->State = HAL_UART_STATE_BUSY_TX_RX; @@ -994,8 +1005,9 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Pauses the DMA Transfer. - * @param huart: UART handle - * @retval None + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { @@ -1027,8 +1039,9 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /** * @brief Resumes the DMA Transfer. - * @param huart: UART handle - * @retval None + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { @@ -1042,22 +1055,19 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) } else if(huart->State == HAL_UART_STATE_BUSY_RX) { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); /* Enable the UART DMA Rx request */ huart->Instance->CR3 |= USART_CR3_DMAR; } else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); /* Enable the UART DMA Tx & Rx request */ huart->Instance->CR3 |= USART_CR3_DMAT; huart->Instance->CR3 |= USART_CR3_DMAR; } - - /* If the UART peripheral is still not enabled, enable it */ - if ((huart->Instance->CR1 & USART_CR1_UE) == 0) - { - /* Enable UART peripheral */ - __HAL_UART_ENABLE(huart); - } /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1067,13 +1077,17 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /** * @brief Stops the DMA Transfer. - * @param huart: UART handle - * @retval None + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { - /* Process Locked */ - __HAL_LOCK(huart); + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ /* Disable the UART Tx/Rx DMA requests */ huart->Instance->CR3 &= ~USART_CR3_DMAT; @@ -1089,20 +1103,16 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { HAL_DMA_Abort(huart->hdmarx); } - /* Disable UART peripheral */ - __HAL_UART_DISABLE(huart); huart->State = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } /** * @brief This function handles UART interrupt request. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) @@ -1114,7 +1124,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* UART parity error interrupt occurred ------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_PE); + __HAL_UART_CLEAR_PEFLAG(huart); huart->ErrorCode |= HAL_UART_ERROR_PE; } @@ -1124,7 +1134,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* UART frame error interrupt occurred -------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_FE); + __HAL_UART_CLEAR_FEFLAG(huart); huart->ErrorCode |= HAL_UART_ERROR_FE; } @@ -1134,7 +1144,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* UART noise error interrupt occurred -------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_NE); + __HAL_UART_CLEAR_NEFLAG(huart); huart->ErrorCode |= HAL_UART_ERROR_NE; } @@ -1144,7 +1154,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* UART Over-Run interrupt occurred ----------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_ORE); + __HAL_UART_CLEAR_OREFLAG(huart); huart->ErrorCode |= HAL_UART_ERROR_ORE; } @@ -1155,16 +1165,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) if((tmp1 != RESET) && (tmp2 != RESET)) { UART_Receive_IT(huart); - __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); } - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC); + tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE); + tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE); /* UART in mode Transmitter ------------------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { UART_Transmit_IT(huart); - __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); } if(huart->ErrorCode != HAL_UART_ERROR_NONE) @@ -1178,7 +1186,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Tx Transfer completed callbacks. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) @@ -1190,7 +1199,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callbacks. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1202,7 +1212,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Rx Transfer completed callbacks. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) @@ -1214,7 +1225,8 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callbacks. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1226,7 +1238,8 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief UART error callbacks. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -1259,7 +1272,8 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief Transmits break characters. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) @@ -1285,7 +1299,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /** * @brief Enters the UART in mute mode. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) @@ -1311,7 +1326,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Exits the UART mute mode: wake up software. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) @@ -1337,9 +1353,9 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) /** * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { @@ -1372,7 +1388,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /** * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) @@ -1417,10 +1434,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) ============================================================================== [..] This subsection provides a set of functions allowing to return the State of - UART communication process, return Peripheral Errors occured during communication + UART communication process, return Peripheral Errors occurred during communication process (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. - (+) HAL_UART_GetError() check in run-time errors that could be occured durung communication. + (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. @endverbatim * @{ @@ -1428,7 +1445,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /** * @brief Returns the UART state. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) @@ -1456,41 +1474,51 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) * @param hdma: DMA handle * @retval None */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + /* DMA Normal mode*/ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + huart->TxXferCount = 0; - /* Wait for UART TC Flag */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout Occured */ - huart->State = HAL_UART_STATE_TIMEOUT; - HAL_UART_ErrorCallback(huart); - } - else - { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + /* Wait for UART TC Flag */ + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK) { - huart->State = HAL_UART_STATE_BUSY_RX; + /* Timeout occurred */ + huart->State = HAL_UART_STATE_TIMEOUT; + HAL_UART_ErrorCallback(huart); } else { - huart->State = HAL_UART_STATE_READY; + /* No Timeout */ + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + HAL_UART_TxCpltCallback(huart); } + } + /* DMA Circular mode */ + else + { HAL_UART_TxCpltCallback(huart); } } /** * @brief DMA UART transmit process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1508,27 +1536,32 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; + /* DMA Normal mode*/ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + huart->RxXferCount = 0; - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; + /* Check if a transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } } HAL_UART_RxCpltCallback(huart); } /** * @brief DMA UART receive process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1555,7 +1588,8 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles UART Communication Timeout. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @param Flag: specifies the UART flag to check. * @param Status: The new Flag status (SET or RESET). * @param Timeout: Timeout duration @@ -1563,10 +1597,11 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t timeout = 0; - - timeout = HAL_GetTick() + Timeout; - + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until flag is set */ if(Status == RESET) { @@ -1575,7 +1610,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); @@ -1600,7 +1635,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); @@ -1618,12 +1653,13 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, } } } - return HAL_OK; + return HAL_OK; } /** * @brief Sends an amount of data in non blocking mode. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) @@ -1634,9 +1670,6 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) tmp1 = huart->State; if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX)) { - /* Process Locked */ - __HAL_LOCK(huart); - if(huart->Init.WordLength == UART_WORDLENGTH_9B) { tmp = (uint16_t*) huart->pTxBuffPtr; @@ -1658,8 +1691,8 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) if(--huart->TxXferCount == 0) { /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + /* Check if a receive process is ongoing or not */ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { @@ -1669,34 +1702,35 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + huart->State = HAL_UART_STATE_READY; } - /* Call the Process Unlocked before calling the Tx callback API to give the possibility to - start again the Transmission under the Tx callback API */ - __HAL_UNLOCK(huart); + + /* Wait on TC flag to be able to start a second transfer */ + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } HAL_UART_TxCpltCallback(huart); return HAL_OK; } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } + /** * @brief Receives an amount of data in non blocking mode - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) @@ -1707,9 +1741,6 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) tmp1 = huart->State; if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX)) { - /* Process Locked */ - __HAL_LOCK(huart); - if(huart->Init.WordLength == UART_WORDLENGTH_9B) { tmp = (uint16_t*) huart->pRxBuffPtr; @@ -1735,14 +1766,11 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); } } - + if(--huart->RxXferCount == 0) { - while(HAL_IS_BIT_SET(huart->Instance->SR, UART_FLAG_RXNE)) - { - } __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - + /* Check if a transmit process is ongoing or not */ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { @@ -1752,23 +1780,16 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + huart->State = HAL_UART_STATE_READY; } - /* Call the Process Unlocked before calling the Rx callback API to give the possibility to - start again the reception under the Rx callback API */ - __HAL_UNLOCK(huart); - HAL_UART_RxCpltCallback(huart); - + return HAL_OK; } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1779,7 +1800,8 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) /** * @brief Configures the UART peripheral. - * @param huart: UART handle + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) diff --git a/stmhal/hal/src/stm32f4xx_hal_usart.c b/stmhal/hal/src/stm32f4xx_hal_usart.c index 3c5808b67..0f816f1b8 100644 --- a/stmhal/hal/src/stm32f4xx_hal_usart.c +++ b/stmhal/hal/src/stm32f4xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_usart.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: @@ -18,7 +18,7 @@ The USART HAL driver can be used as follows: (#) Declare a USART_HandleTypeDef handle structure. - (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API: + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API: (##) Enable the USARTx interface clock. (##) USART pins configuration: (+++) Enable the clock for the USART GPIOs. @@ -40,14 +40,14 @@ flow control and Mode(Receiver/Transmitter) in the husart Init structure. (#) Initialize the USART registers by calling the HAL_USART_Init() API: - (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed HAL_USART_MspInit(&husart) API. -@@- The specific USART interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __USART_ENABLE_IT() and __USART_DISABLE_IT() inside the transmit and receive process. - (#) Three mode of operations are available within this driver : + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -97,10 +97,10 @@ (+) __HAL_USART_ENABLE: Enable the USART peripheral (+) __HAL_USART_DISABLE: Disable the USART peripheral - (+) __HAL_USART_GET_FLAG : Checks whether the specified USART flag is set or not - (+) __HAL_USART_CLEAR_FLAG : Clears the specified USART pending flag - (+) __HAL_USART_ENABLE_IT: Enables the specified USART interrupt - (+) __HAL_USART_DISABLE_IT: Disables the specified USART interrupt + (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not + (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag + (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt + (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt [..] (@) You can refer to the USART HAL driver header file for more useful macros @@ -150,7 +150,7 @@ #ifdef HAL_USART_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define DYMMY_DATA 0xFFFF +#define DUMMY_DATA 0xFFFF #define USART_TIMEOUT_VALUE 22000 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -189,18 +189,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ + please refer to Reference manual for possible USART frame formats. (++) USART polarity (++) USART phase (++) USART LastBit @@ -217,7 +206,8 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief Initializes the USART mode according to the specified * parameters in the USART_InitTypeDef and create the associated handle. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) @@ -260,7 +250,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /** * @brief DeInitializes the USART peripheral. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) @@ -290,7 +281,8 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief USART MSP Init. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) @@ -302,7 +294,8 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief USART MSP DeInit. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) @@ -331,7 +324,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) The USART supports master mode only: it cannot receive or send data related to an input clock (SCLK is always an output). - (#) There are two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. @@ -341,28 +334,28 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) dedicated USART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() - user callbacks + user callbacks will be executed respectivelly at the end of the transmit or Receive process - The HAL_USART_ErrorCallback()user callback will be executed when a communication + The HAL_USART_ErrorCallback() user callback will be executed when a communication error is detected - (#) Blocking mode API's are : - (++) HAL_USART_Transmit()in simplex mode + (#) Blocking mode APIs are : + (++) HAL_USART_Transmit() in simplex mode (++) HAL_USART_Receive() in full duplex receive only (++) HAL_USART_TransmitReceive() in full duplex mode - (#) Non-Blocking mode API's with Interrupt are : + (#) Non Blocking mode APIs with Interrupt are : (++) HAL_USART_Transmit_IT()in simplex mode (++) HAL_USART_Receive_IT() in full duplex receive only - (++) HAL_USART_TransmitReceive_IT()in full duplex mode + (++) HAL_USART_TransmitReceive_IT() in full duplex mode (++) HAL_USART_IRQHandler() - (#) No-Blocking mode functions with DMA are : + (#) Non Blocking mode functions with DMA are : (++) HAL_USART_Transmit_DMA()in simplex mode (++) HAL_USART_Receive_DMA() in full duplex receive only (++) HAL_USART_TransmitReceie_DMA() in full duplex mode - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_USART_TxCpltCallback() (++) HAL_USART_RxCpltCallback() (++) HAL_USART_ErrorCallback() @@ -374,9 +367,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief Simplex Send an amount of data in blocking mode. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @param pTxData: Pointer to data buffer * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) @@ -404,7 +399,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if(husart->Init.WordLength == USART_WORDLENGTH_9B) { /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -449,9 +444,11 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Full-Duplex Receive an amount of data in blocking mode. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @param pRxData: Pointer to data buffer * @param Size: Amount of data to be received + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -478,13 +475,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat husart->RxXferCount--; if(husart->Init.WordLength == USART_WORDLENGTH_9B) { - /* Wait until TC flag is set to send dummy byte in order to generate the clock for the slave to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } /* Send dummy byte in order to generate clock */ - husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x01FF); + husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF); /* Wait for RXNE Flag */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -505,14 +502,14 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat } else { - /* Wait until TC flag is set to send dummy byte in order to generate the clock for the slave to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } /* Send Dummy Byte in order to generate clock */ - husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x00FF); + husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF); /* Wait until RXNE flag is set to receive the byte */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -548,9 +545,12 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). - * @param husart: USART handle - * @param pTxData: Pointer to data buffer + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data transmitted buffer + * @param pRxData: Pointer to data received buffer * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -582,7 +582,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t if(husart->Init.WordLength == USART_WORDLENGTH_9B) { /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -617,7 +617,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t else { /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -656,7 +656,8 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @param pTxData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -692,8 +693,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Transmit Complete Interrupt */ - __USART_ENABLE_IT(husart, USART_IT_TC); + /* Enable the USART Transmit Data Register Empty Interrupt */ + __USART_ENABLE_IT(husart, USART_IT_TXE); return HAL_OK; } @@ -705,7 +706,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Simplex Receive an amount of data in non-blocking mode. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @param pRxData: Pointer to data buffer * @param Size: Amount of data to be received * @retval HAL status @@ -741,7 +743,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Send dummy byte in order to generate the clock for the slave to send data */ - husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x01FF); + husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF); return HAL_OK; } @@ -753,8 +755,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param husart: USART handle - * @param pTxData: Pointer to data buffer + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data transmitted buffer + * @param pRxData: Pointer to data received buffer * @param Size: Amount of data to be received * @retval HAL status */ @@ -791,8 +795,8 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Transmit Complete Interrupt */ - __USART_ENABLE_IT(husart, USART_IT_TC); + /* Enable the USART Transmit Data Register Empty Interrupt */ + __USART_ENABLE_IT(husart, USART_IT_TXE); return HAL_OK; } @@ -804,8 +808,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: USART handle - * @param pData: Pointer to data buffer + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status */ @@ -859,7 +864,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /** * @brief Full-Duplex Receive an amount of data in non-blocking mode. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @param pRxData: Pointer to data buffer * @param Size: Amount of data to be received * @retval HAL status @@ -906,6 +912,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR this mode isn't a simplex receive mode but a full-duplex receive one */ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); + /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer + when using the USART in circular mode */ + __HAL_USART_CLEAR_OREFLAG(husart); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAR; @@ -927,8 +937,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. - * @param husart: USART handle - * @param pRxData: Pointer to data buffer + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data transmitted buffer + * @param pRxData: Pointer to data received buffer * @param Size: Amount of data to be received * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status @@ -979,7 +991,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Enable the USART transmit DMA Stream */ tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); - + + /* Clear the Overrun flag: mandatory for the second transfer in circular mode */ + __HAL_USART_CLEAR_OREFLAG(husart); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAR; @@ -1001,92 +1016,57 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /** * @brief Pauses the DMA Transfer. - * @param husart: USART handle - * @retval None + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) { /* Process Locked */ __HAL_LOCK(husart); - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Disable the USART DMA Tx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - } - else if(husart->State == HAL_USART_STATE_BUSY_RX) - { - /* Disable the USART DMA Rx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } - else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) - { - /* Disable the USART DMA Tx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - /* Disable the USART DMA Rx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } - + + /* Disable the USART DMA Tx request */ + husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } /** * @brief Resumes the DMA Transfer. - * @param husart: USART handle - * @retval None + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) { /* Process Locked */ __HAL_LOCK(husart); - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Enable the USART DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAT; - } - else if(husart->State == HAL_USART_STATE_BUSY_RX) - { - /* Enable the USART DMA Rx request */ - husart->Instance->CR3 |= USART_CR3_DMAR; - } - else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) - { - /* Enable the USART DMA Rx request before the DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAR; - /* Enable the USART DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAT; - } - - /* If the USART peripheral is still not enabled, enable it */ - if ((husart->Instance->CR1 & USART_CR1_UE) == 0) - { - /* Enable USART peripheral */ - __USART_ENABLE(husart); - } - + + /* Enable the USART DMA Tx request */ + husart->Instance->CR3 |= USART_CR3_DMAT; + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } /** * @brief Stops the DMA Transfer. - * @param husart: USART handle - * @retval None + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) { - /* Process Locked */ - __HAL_LOCK(husart); - - /* Disable the USART Tx/Rx DMA requests */ - husart->Instance->CR3 &= ~USART_CR3_DMAT; - husart->Instance->CR3 &= ~USART_CR3_DMAR; + /* The Lock is not implemented on this API to allow the user application + to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() + */ /* Abort the USART DMA Tx Stream */ if(husart->hdmatx != NULL) @@ -1098,20 +1078,20 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) { HAL_DMA_Abort(husart->hdmarx); } - /* Disable USART peripheral */ - __USART_DISABLE(husart); - + + /* Disable the USART Tx/Rx DMA requests */ + husart->Instance->CR3 &= ~USART_CR3_DMAT; + husart->Instance->CR3 &= ~USART_CR3_DMAR; + husart->State = HAL_USART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_OK; } /** * @brief This function handles USART interrupt request. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) @@ -1123,7 +1103,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART parity error interrupt occurred -----------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_PE); + __HAL_USART_CLEAR_PEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_PE; } @@ -1132,7 +1112,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART frame error interrupt occurred ------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_FE); + __HAL_USART_CLEAR_FEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_FE; } @@ -1141,7 +1121,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART noise error interrupt occurred ------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_NE); + __HAL_USART_CLEAR_NEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_NE; } @@ -1150,7 +1130,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART Over-Run interrupt occurred ---------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { - __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_ORE); + __HAL_USART_CLEAR_OREFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_ORE; } @@ -1177,8 +1157,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } } - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC); + tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE); + tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE); /* USART in mode Transmitter -----------------------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { @@ -1195,7 +1175,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Tx Transfer completed callbacks. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) @@ -1207,7 +1188,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Tx Half Transfer completed callbacks. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1219,7 +1201,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Rx Transfer completed callbacks. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) @@ -1231,7 +1214,8 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Half Transfer completed callbacks. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1243,7 +1227,8 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) @@ -1255,7 +1240,8 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /** * @brief USART error callbacks. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) @@ -1279,10 +1265,10 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) [..] This subsection provides a set of functions allowing to return the State of USART communication - process, return Peripheral Errors occured during communication process + process, return Peripheral Errors occurred during communication process (+) HAL_USART_GetState() API can be helpful to check in run-time the state of the USART peripheral. - (+) HAL_USART_GetError() check in run-time errors that could be occured durung + (+) HAL_USART_GetError() check in run-time errors that could be occurred during communication. @endverbatim * @{ @@ -1290,7 +1276,8 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Returns the USART state. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval HAL state */ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) @@ -1322,37 +1309,44 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - husart->TxXferCount = 0; - if(husart->State == HAL_USART_STATE_BUSY_TX) + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) { - /* Wait for USART TC Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK) + husart->TxXferCount = 0; + if(husart->State == HAL_USART_STATE_BUSY_TX) { - /* Timeout Occured */ - husart->State = HAL_USART_STATE_TIMEOUT; - HAL_USART_ErrorCallback(husart); - } - else - { - /* No Timeout */ - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - husart->Instance->CR3 &= ~(USART_CR3_DMAT); - husart->State= HAL_USART_STATE_READY; + /* Wait for USART TC Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + husart->State = HAL_USART_STATE_TIMEOUT; + HAL_USART_ErrorCallback(husart); + } + else + { + /* No Timeout */ + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + husart->Instance->CR3 &= ~(USART_CR3_DMAT); + husart->State= HAL_USART_STATE_READY; + HAL_USART_TxCpltCallback(husart); + } } } - /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + /* DMA Circular mode */ else { - husart->State= HAL_USART_STATE_BUSY_RX; - HAL_USART_TxCpltCallback(husart); + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + HAL_USART_TxCpltCallback(husart); + } } } /** * @brief DMA USART transmit process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1367,25 +1361,52 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) * @param hdma: DMA handle * @retval None */ -static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + husart->RxXferCount = 0; + husart->State= HAL_USART_STATE_READY; + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit + in the USART CR3 register */ + husart->Instance->CR3 &= ~(USART_CR3_DMAR); - husart->RxXferCount = 0; + HAL_USART_RxCpltCallback(husart); + } + /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + else + { + /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit + in the USART CR3 register */ + husart->Instance->CR3 &= ~(USART_CR3_DMAR); + husart->Instance->CR3 &= ~(USART_CR3_DMAT); - /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit - in the USART CR3 register */ - husart->Instance->CR3 &= ~(USART_CR3_DMAR); - husart->Instance->CR3 &= ~(USART_CR3_DMAT); - - husart->State= HAL_USART_STATE_READY; - - HAL_USART_RxCpltCallback(husart); + HAL_USART_TxRxCpltCallback(husart); + } + } + /* DMA circular mode */ + else + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + HAL_USART_RxCpltCallback(husart); + } + /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + else + { + HAL_USART_TxRxCpltCallback(husart); + } + } } /** * @brief DMA USART receive process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1400,7 +1421,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) * @param hdma: DMA handle * @retval None */ -static void USART_DMAError(DMA_HandleTypeDef *hdma) +static void USART_DMAError(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; @@ -1414,7 +1435,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles USART Communication Timeout. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @param Flag: specifies the USART flag to check. * @param Status: The new Flag status (SET or RESET). * @param Timeout: Timeout duration @@ -1422,9 +1444,10 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; - timeout = HAL_GetTick() + Timeout; + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait until flag is set */ if(Status == RESET) @@ -1434,7 +1457,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __USART_DISABLE_IT(husart, USART_IT_TXE); @@ -1459,7 +1482,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __USART_DISABLE_IT(husart, USART_IT_TXE); @@ -1483,7 +1506,8 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval HAL status * @note The USART errors are not managed to avoid the overrun error. */ @@ -1493,9 +1517,6 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_BUSY_TX) { - /* Process Locked */ - __HAL_LOCK(husart); - if(husart->Init.WordLength == USART_WORDLENGTH_9B) { tmp = (uint16_t*) husart->pTxBuffPtr; @@ -1516,26 +1537,23 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) if(--husart->TxXferCount == 0) { - /* Disable the USART Transmit Complete Interrupt */ - __USART_DISABLE_IT(husart, USART_IT_TC); + /* Disable the USART Transmit data register empty Interrupt */ + __USART_DISABLE_IT(husart, USART_IT_TXE); /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __USART_DISABLE_IT(husart, USART_IT_ERR); + + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } husart->State = HAL_USART_STATE_READY; - - /* Call the Process Unlocked before calling the Tx callback API to give the possibility to - start again the Transmission under the Tx callback API */ - __HAL_UNLOCK(husart); - + HAL_USART_TxCpltCallback(husart); return HAL_OK; } - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_OK; } else @@ -1546,7 +1564,8 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) /** * @brief Simplex Receive an amount of data in non-blocking mode. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval HAL status */ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) @@ -1554,9 +1573,6 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) uint16_t* tmp; if(husart->State == HAL_USART_STATE_BUSY_RX) { - /* Process Locked */ - __HAL_LOCK(husart); - if(husart->Init.WordLength == USART_WORDLENGTH_9B) { tmp = (uint16_t*) husart->pRxBuffPtr; @@ -1573,7 +1589,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) if(--husart->RxXferCount != 0x00) { /* Send dummy byte in order to generate the clock for the slave to send the next data */ - husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x01FF); + husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF); } } else @@ -1590,7 +1606,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) if(--husart->RxXferCount != 0x00) { /* Send dummy byte in order to generate the clock for the slave to send the next data */ - husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x00FF); + husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF); } } @@ -1606,18 +1622,10 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) __USART_DISABLE_IT(husart, USART_IT_ERR); husart->State = HAL_USART_STATE_READY; - /* Call the Process Unlocked before calling the Rx callback API to give the possibility to - start again the reception under the Rx callback API */ - __HAL_UNLOCK(husart); - HAL_USART_RxCpltCallback(husart); return HAL_OK; } - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_OK; } else @@ -1628,7 +1636,8 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) /** * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval HAL status */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) @@ -1637,8 +1646,6 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { - /* Process Locked */ - __HAL_LOCK(husart); if(husart->TxXferCount != 0x00) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) @@ -1665,7 +1672,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) /* Check the latest data transmitted */ if(husart->TxXferCount == 0) { - __USART_DISABLE_IT(husart, USART_IT_TC); + __USART_DISABLE_IT(husart, USART_IT_TXE); } } } @@ -1713,21 +1720,14 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __USART_DISABLE_IT(husart, USART_IT_ERR); - + husart->State = HAL_USART_STATE_READY; - /* Call the Process Unlocked before calling the Tx\Rx callback API to give the possibility to - start again the Transmission\Reception under the Tx\Rx callback API */ - __HAL_UNLOCK(husart); - HAL_USART_TxRxCpltCallback(husart); return HAL_OK; } - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_OK; } else @@ -1738,7 +1738,8 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) /** * @brief Configures the USART peripheral. - * @param husart: USART handle + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ static void USART_SetConfig(USART_HandleTypeDef *husart) diff --git a/stmhal/hal/src/stm32f4xx_hal_wwdg.c b/stmhal/hal/src/stm32f4xx_hal_wwdg.c index 76884ac55..133ba7c6e 100644 --- a/stmhal/hal/src/stm32f4xx_hal_wwdg.c +++ b/stmhal/hal/src/stm32f4xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -62,9 +62,9 @@ Below the list of most used macros in WWDG HAL driver. (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral - (+) __HAL_IWDG_GET_FLAG: Get the selected WWDG's flag status - (+) __HAL_IWDG_CLEAR_FLAG: Clear the WWDG's pending flags - (+) __HAL_IWDG_RELOAD_COUNTER: Enables the WWDG early wakeup interrupt + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt @endverbatim ****************************************************************************** @@ -144,20 +144,20 @@ /** * @brief Initializes the WWDG according to the specified * parameters in the WWDG_InitTypeDef and creates the associated handle. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) { - uint32_t tmp = 0; - /* Check the WWDG handle allocation */ if(hwwdg == NULL) { return HAL_ERROR; } - + /* Check the parameters */ + assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); @@ -172,31 +172,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) hwwdg->State = HAL_WWDG_STATE_BUSY; /* Set WWDG Prescaler and Window */ - /* Get the CFR register value */ - tmp = hwwdg->Instance->CFR; - - /* Clear WDGTB[1:0] and W[6:0] bits */ - tmp &= ((uint32_t)~(WWDG_CFR_WDGTB | WWDG_CFR_W)); - - /* Prepare the WWDG Prescaler and Window parameters */ - tmp |= hwwdg->Init.Prescaler | hwwdg->Init.Window; - - /* Write to WWDG CFR */ - hwwdg->Instance->CFR = tmp; - + MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window)); /* Set WWDG Counter */ - /* Get the CR register value */ - tmp = hwwdg->Instance->CR; - - /* Clear T[6:0] bits */ - tmp &= ((uint32_t)~(WWDG_CR_T)); - - /* Prepare the WWDG Counter parameter */ - tmp |= (hwwdg->Init.Counter); - - /* Write to WWDG CR */ - hwwdg->Instance->CR = tmp; - + MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter); + /* Change WWDG peripheral state */ hwwdg->State = HAL_WWDG_STATE_READY; @@ -206,11 +185,21 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) /** * @brief DeInitializes the WWDG peripheral. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) -{ +{ + /* Check the WWDG handle allocation */ + if(hwwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + /* Change WWDG peripheral state */ hwwdg->State = HAL_WWDG_STATE_BUSY; @@ -238,7 +227,8 @@ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) /** * @brief Initializes the WWDG MSP. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) @@ -250,7 +240,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) /** * @brief DeInitializes the WWDG MSP. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) @@ -283,7 +274,8 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) /** * @brief Starts the WWDG. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) @@ -309,30 +301,33 @@ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) /** * @brief Starts the WWDG with interrupt enabled. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) -{ +{ /* Process Locked */ __HAL_LOCK(hwwdg); - + /* Change WWDG peripheral state */ hwwdg->State = HAL_WWDG_STATE_BUSY; - + /* Enable the Early Wakeup Interrupt */ __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI); /* Enable the peripheral */ __HAL_WWDG_ENABLE(hwwdg); - + /* Return function status */ return HAL_OK; } /** * @brief Refreshes the WWDG. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @param Counter: value of counter to put in WWDG counter * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) @@ -347,7 +342,7 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) assert_param(IS_WWDG_COUNTER(Counter)); /* Write to WWDG CR the WWDG Counter value to refresh with */ - MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, Counter); + MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter); /* Change WWDG peripheral state */ hwwdg->State = HAL_WWDG_STATE_READY; @@ -368,7 +363,8 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) * generated and the corresponding Interrupt Service Routine (ISR) can * be used to trigger specific actions (such as communications or data * logging), before resetting the device. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) @@ -392,7 +388,8 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) /** * @brief Early Wakeup WWDG callback. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) @@ -423,7 +420,8 @@ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) /** * @brief Returns the WWDG state. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL state */ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg) diff --git a/stmhal/hal/src/stm32f4xx_ll_fmc.c b/stmhal/hal/src/stm32f4xx_ll_fmc.c index d36633b51..9b1d68c90 100644 --- a/stmhal/hal/src/stm32f4xx_ll_fmc.c +++ b/stmhal/hal/src/stm32f4xx_ll_fmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fmc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -685,21 +685,22 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) */ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_NAND_BANK(Bank)); - - timeout = HAL_GetTick() + Timeout; - + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait untill FIFO is empty */ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { return HAL_TIMEOUT; } @@ -1145,7 +1146,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { __IO uint32_t tmpr = 0; - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -1158,12 +1159,13 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com tmpr = (uint32_t)((Command->CommandMode) |\ (Command->CommandTarget) |\ (((Command->AutoRefreshNumber)-1) << 5) |\ - ((Command->ModeRegisterDefinition) << 9) + ((Command->ModeRegisterDefinition) << 9) ); Device->SDCMR = tmpr; - - timeout = HAL_GetTick() + Timeout; + + /* Get tick */ + tickstart = HAL_GetTick(); /* wait until command is send */ while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) @@ -1171,7 +1173,7 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { return HAL_TIMEOUT; } diff --git a/stmhal/hal/src/stm32f4xx_ll_fsmc.c b/stmhal/hal/src/stm32f4xx_ll_fsmc.c index 55b187584..f06bf499c 100644 --- a/stmhal/hal/src/stm32f4xx_ll_fsmc.c +++ b/stmhal/hal/src/stm32f4xx_ll_fsmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fsmc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief FSMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -630,21 +630,22 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank */ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { - uint32_t timeout = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_NAND_BANK(Bank)); - - timeout = HAL_GetTick() + Timeout; - + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait untill FIFO is empty */ while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { return HAL_TIMEOUT; } diff --git a/stmhal/hal/src/stm32f4xx_ll_sdmmc.c b/stmhal/hal/src/stm32f4xx_ll_sdmmc.c index aaedb7062..9e0b60903 100644 --- a/stmhal/hal/src/stm32f4xx_ll_sdmmc.c +++ b/stmhal/hal/src/stm32f4xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -66,8 +66,8 @@ (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO peripheral. - (+) Enable the Power ON State using the HAL_SDIO_PowerState_ON(hsdio) - function and disable it using the function HAL_SDIO_PowerState_OFF(hsdio). + (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx) + function and disable it using the function HAL_SDIO_PowerState_OFF(SDIOx). (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. @@ -81,8 +81,8 @@ __SDIO_DMA_DISABLE(). (+) To control the CPSM (Command Path State Machine) and send - commands to the card use the HAL_SDIO_SendCommand(), - HAL_SDIO_GetCommandResponse() and HAL_SDIO_GetResponse() functions. First, user has + commands to the card use the SDIO_SendCommand(SDIOx), + SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has to fill the command structure (pointer to SDIO_CmdInitTypeDef) according to the selected command to be sent. The parameters that should be filled are: @@ -93,13 +93,13 @@ (++) CPSM Status (Enable or Disable). -@@- To check if the command is well received, read the SDIO_CMDRESP - register using the HAL_SDIO_GetCommandResponse(). + register using the SDIO_GetCommandResponse(). The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - HAL_SDIO_GetResponse() function. + SDIO_GetResponse() function. (+) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the HAL_SDIO_DataConfig(), HAL_SDIO_GetDataCounter(), - HAL_SDIO_ReadFIFO(), HAL_SDIO_WriteFIFO() and HAL_SDIO_GetFIFOCount() functions. + data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), + SDIO_ReadFIFO(), DIO_WriteFIFO() and SDIO_GetFIFOCount() functions. *** Read Operations *** ======================= @@ -135,9 +135,9 @@ (++) DPSM Status (Enable or Disable) (#) Configure the SDIO resources to send the data to the card according to - selected transfer mode (Refer to Step 8, 9 and 10). + selected transfer mode. - (#) Send the selected Write command (refer to step 11). + (#) Send the selected Write command. (#) Use the SDIO flags/interrupts to check the transfer status. @@ -219,7 +219,7 @@ */ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) { - __IO uint32_t tmpreg = 0; + uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); @@ -230,12 +230,6 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); - /* Get the SDIO CLKCR value */ - tmpreg = SDIOx->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - /* Set SDIO configuration parameters */ tmpreg |= (Init.ClockEdge |\ Init.ClockBypass |\ @@ -246,7 +240,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) ); /* Write to SDIO CLKCR */ - SDIOx->CLKCR = tmpreg; + MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); return HAL_OK; } @@ -275,7 +269,6 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) /** * @brief Read data (word) from Rx FIFO in blocking mode (polling) * @param SDIOx: Pointer to SDIO register base - * @param ReadData: Data to read * @retval HAL status */ uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) @@ -325,7 +318,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) { /* Set power state to ON */ - SDIOx->POWER = (uint32_t)0x00000003; + SDIOx->POWER = SDIO_POWER_PWRCTRL; return HAL_OK; } @@ -354,7 +347,7 @@ HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) */ uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) { - return (SDIOx->POWER & (~PWR_PWRCTRL_MASK)); + return (SDIOx->POWER & SDIO_POWER_PWRCTRL); } /** @@ -377,14 +370,7 @@ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDI /* Set the SDIO Argument value */ SDIOx->ARG = SDIO_CmdInitStruct->Argument; - - /* SDIO CMD Configuration */ - /* Get the SDIO CMD value */ - tmpreg = SDIOx->CMD; - - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - + /* Set SDIO command parameters */ tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\ SDIO_CmdInitStruct->Response |\ @@ -392,7 +378,7 @@ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDI SDIO_CmdInitStruct->CPSM); /* Write to SDIO CMD register */ - SDIOx->CMD = tmpreg; + MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); return HAL_OK; } @@ -456,21 +442,14 @@ HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDI /* Set the SDIO DataLength value */ SDIOx->DLEN = SDIO_DataInitStruct->DataLength; -/* SDIO DCTRL Configuration */ - /* Get the SDIO DCTRL value */ - tmpreg = SDIOx->DCTRL; - - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set the SDIO data configuration parameters */ tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\ SDIO_DataInitStruct->TransferDir |\ SDIO_DataInitStruct->TransferMode |\ SDIO_DataInitStruct->DPSM); - + /* Write to SDIO DCTRL */ - SDIOx->DCTRL = tmpreg; + MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); return HAL_OK; @@ -488,7 +467,7 @@ uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) /** * @brief Get the FIFO data - * @param hsdio: SDIO handle + * @param SDIOx: Pointer to SDIO register base * @retval Data received */ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) @@ -515,26 +494,6 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) return HAL_OK; } - -/** - * @} - */ - -/** @defgroup HAL_SDIO_Group3 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permit to get in runtime the status of the SDIO peripheral - and the data flow. - -@endverbatim - * @{ - */ - /** * @} */ diff --git a/stmhal/hal/src/stm32f4xx_ll_usb.c b/stmhal/hal/src/stm32f4xx_ll_usb.c index 257d5c97e..cd3a0bc5b 100644 --- a/stmhal/hal/src/stm32f4xx_ll_usb.c +++ b/stmhal/hal/src/stm32f4xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0 + * @date 19-June-2014 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -1420,8 +1420,6 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, #pragma O0 #elif defined (__GNUC__) /*!< GNU Compiler */ #pragma GCC optimize ("O0") -#elif defined (__TASKING__) /*!< TASKING Compiler */ -#pragma optimize=0 #endif /* __CC_ARM */ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) { @@ -1437,6 +1435,11 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe USB_DoPing(USBx, hc->ch_num); return HAL_OK; } + else if(dma == 1) + { + USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + hc->do_ping = 0; + } } /* Compute the expected number of packets associated to the transfer */ @@ -1463,15 +1466,15 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /* Initialize the HCTSIZn register */ USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ - ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); + ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ + (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); if (dma) { /* xfer_buff MUST be 32-bits aligned */ USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; } - + is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); @@ -1479,7 +1482,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /* Set host channel enable */ USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; USBx_HC(hc->ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - + if (dma == 0) /* Slave mode */ { if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) diff --git a/stmhal/system_stm32f4xx.c b/stmhal/system_stm32f4xx.c index bc9c5dff4..4f8090204 100644 --- a/stmhal/system_stm32f4xx.c +++ b/stmhal/system_stm32f4xx.c @@ -348,9 +348,4 @@ void SystemClock_Config(void) { __fatal_error("HAL_RCC_ClockConfig"); } - - // SysTick_Config (called from HL_RCC_ClockConfig) sets the SysTick_IRQn to - // be the lowest priority, but we want it to be the highest priority, so fix - // things here. - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); }