diff --git a/ports/stm32/eth.c b/ports/stm32/eth.c
index 9633d32b2..756bb6dd6 100644
--- a/ports/stm32/eth.c
+++ b/ports/stm32/eth.c
@@ -153,9 +153,9 @@ void eth_set_trace(eth_t *self, uint32_t value) {
 
 STATIC int eth_mac_init(eth_t *self) {
     // Configure MPU
-    mpu_config_start();
+    uint32_t irq_state = mpu_config_start();
     mpu_config_region(MPU_REGION_ETH, (uint32_t)&eth_dma, MPU_CONFIG_ETH(MPU_REGION_SIZE_16KB));
-    mpu_config_end();
+    mpu_config_end(irq_state);
 
     // Configure GPIO
     mp_hal_pin_config_alt_static(MICROPY_HW_ETH_MDC, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_MDC);
diff --git a/ports/stm32/mpu.h b/ports/stm32/mpu.h
index 1efe93a68..74ba81496 100644
--- a/ports/stm32/mpu.h
+++ b/ports/stm32/mpu.h
@@ -78,8 +78,8 @@ static inline void mpu_init(void) {
     __ISB();
 }
 
-static inline void mpu_config_start(void) {
-    __disable_irq();
+static inline uint32_t mpu_config_start(void) {
+    return disable_irq();
 }
 
 static inline void mpu_config_region(uint32_t region, uint32_t base_addr, uint32_t attr_size) {
@@ -88,11 +88,11 @@ static inline void mpu_config_region(uint32_t region, uint32_t base_addr, uint32
     MPU->RASR = attr_size;
 }
 
-static inline void mpu_config_end(void) {
+static inline void mpu_config_end(uint32_t irq_state) {
     __ISB();
     __DSB();
     __DMB();
-    __enable_irq();
+    enable_irq(irq_state);
 }
 
 #else
diff --git a/ports/stm32/qspi.c b/ports/stm32/qspi.c
index ec744bfb2..30ee2c9ea 100644
--- a/ports/stm32/qspi.c
+++ b/ports/stm32/qspi.c
@@ -55,9 +55,9 @@
 static inline void qspi_mpu_disable_all(void) {
     // Configure MPU to disable access to entire QSPI region, to prevent CPU
     // speculative execution from accessing this region and modifying QSPI registers.
-    mpu_config_start();
+    uint32_t irq_state = mpu_config_start();
     mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x00, MPU_REGION_SIZE_256MB));
-    mpu_config_end();
+    mpu_config_end(irq_state);
 }
 
 static inline void qspi_mpu_enable_mapped(void) {
@@ -67,11 +67,11 @@ static inline void qspi_mpu_enable_mapped(void) {
     // to everything except the valid address space, using holes in the bottom
     // of the regions and nesting them.
     // At the moment this is hard-coded to 2MiB of QSPI address space.
-    mpu_config_start();
+    uint32_t irq_state = mpu_config_start();
     mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB));
     mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0f, MPU_REGION_SIZE_32MB));
     mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_16MB));
-    mpu_config_end();
+    mpu_config_end(irq_state);
 }
 
 void qspi_init(void) {