stm32: Add support for RF coprocessor on WB55 MCUs.
This requires a BLE wireless stack firmware to be already programmed in the secure flash area of the device.pull/1/head
Damien George
parent
40ea1915fc
commit
6a64b280d0
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@ -252,6 +252,7 @@ SRC_C = \
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softtimer.c \
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powerctrl.c \
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powerctrlboot.c \
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rfcore.c \
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pybthread.c \
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factoryreset.c \
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timer.c \
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@ -8,6 +8,7 @@ MEMORY
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* sectors 0-127 */
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FLASH_FS (r) : ORIGIN = 0x08080000, LENGTH = 256K /* sectors 128-191 */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K /* SRAM1 */
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RAM2A (xrw) : ORIGIN = 0x20030020, LENGTH = 8K /* SRAM2A */
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}
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/* produce a link error if there is not this amount of RAM for these sections */
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@ -31,3 +32,13 @@ _heap_end = _sstack;
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_flash_fs_start = ORIGIN(FLASH_FS);
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_flash_fs_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);
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SECTIONS
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{
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.ram2a_bss :
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{
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. = ALIGN(4);
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*rfcore.o(.bss.ipcc_mem_*)
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. = ALIGN(4);
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} >RAM2A
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}
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@ -48,6 +48,7 @@
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#endif
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#include "mpu.h"
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#include "rfcore.h"
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#include "systick.h"
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#include "pendsv.h"
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#include "powerctrl.h"
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@ -466,6 +467,9 @@ void stm32_main(uint32_t reset_mode) {
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#endif
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// basic sub-system init
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#if defined(STM32WB)
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rfcore_init();
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#endif
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#if MICROPY_HW_SDRAM_SIZE
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sdram_init();
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#if MICROPY_HW_SDRAM_STARTUP_TEST
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@ -26,15 +26,54 @@
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "uart.h"
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#include "pendsv.h"
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#include "extmod/nimble/nimble/hci_uart.h"
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#include "drivers/cyw43/cywbt.h"
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#if MICROPY_BLUETOOTH_NIMBLE
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#if defined(STM32WB)
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/******************************************************************************/
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// UART
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// HCI over IPCC
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#include "rfcore.h"
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int nimble_hci_uart_configure(uint32_t port) {
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(void)port;
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return 0;
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}
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int nimble_hci_uart_set_baudrate(uint32_t baudrate) {
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(void)baudrate;
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return 0;
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}
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int nimble_hci_uart_activate(void) {
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rfcore_ble_init();
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return 0;
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}
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void nimble_hci_uart_rx(hal_uart_rx_cb_t rx_cb, void *rx_arg) {
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// Protect in case it's called from ble_npl_sem_pend at thread-level
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MICROPY_PY_LWIP_ENTER
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rfcore_ble_check_msg(rx_cb, rx_arg);
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MICROPY_PY_LWIP_EXIT
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}
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void nimble_hci_uart_tx_strn(const char *str, uint len) {
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MICROPY_PY_LWIP_ENTER
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rfcore_ble_hci_cmd(len, (const uint8_t*)str);
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MICROPY_PY_LWIP_EXIT
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}
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#else
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/******************************************************************************/
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// HCI over UART
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#include "pendsv.h"
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#include "uart.h"
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#include "drivers/cyw43/cywbt.h"
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pyb_uart_obj_t bt_hci_uart_obj;
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static uint8_t hci_uart_rxbuf[512];
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@ -130,4 +169,6 @@ void nimble_hci_uart_tx_strn(const char *str, uint len) {
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uart_tx_strn(&bt_hci_uart_obj, str, len);
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}
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#endif // defined(STM32WB)
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#endif // MICROPY_BLUETOOTH_NIMBLE
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@ -0,0 +1,425 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "rtc.h"
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#include "rfcore.h"
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#if defined(STM32WB)
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// Define to 1 to print traces of HCI packets
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#define HCI_TRACE (0)
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#define IPCC_CH_BLE (0x01) // BLE HCI command and response
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#define IPCC_CH_SYS (0x02) // system HCI command and response
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#define IPCC_CH_MM (0x08) // release buffer
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#define IPCC_CH_HCI_ACL (0x20) // HCI ACL outgoing data
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#define OGF_VENDOR (0x3f)
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#define OCF_WRITE_CONFIG (0x0c)
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#define OCF_SET_TX_POWER (0x0f)
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#define OCF_BLE_INIT (0x66)
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#define HCI_OPCODE(ogf, ocf) ((ogf) << 10 | (ocf))
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typedef struct _tl_list_node_t {
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volatile struct _tl_list_node_t *next;
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volatile struct _tl_list_node_t *prev;
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uint8_t body[0];
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} tl_list_node_t;
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typedef struct _parse_hci_info_t {
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int (*cb_fun)(void*, uint8_t);
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void *cb_env;
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bool was_hci_reset_evt;
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} parse_hci_info_t;
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static volatile uint32_t ipcc_mem_dev_info_tab[8];
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static volatile uint32_t ipcc_mem_ble_tab[4];
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static volatile uint32_t ipcc_mem_sys_tab[2];
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static volatile uint32_t ipcc_mem_memmgr_tab[7];
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static volatile uint32_t ipcc_mem_sys_cmd_buf[272 / 4];
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static volatile tl_list_node_t ipcc_mem_sys_queue;
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static volatile tl_list_node_t ipcc_mem_memmgr_free_buf_queue;
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static volatile uint32_t ipcc_mem_memmgr_ble_spare_evt_buf[272 / 4];
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static volatile uint32_t ipcc_mem_memmgr_sys_spare_evt_buf[272 / 4];
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static volatile uint32_t ipcc_mem_memmgr_evt_pool[6 * 272 / 4];
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static volatile uint32_t ipcc_mem_ble_cmd_buf[272 / 4];
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static volatile uint32_t ipcc_mem_ble_cs_buf[272 / 4];
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static volatile tl_list_node_t ipcc_mem_ble_evt_queue;
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static volatile uint32_t ipcc_mem_ble_hci_acl_data_buf[272 / 4];
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/******************************************************************************/
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// Transport layer linked list
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STATIC void tl_list_init(volatile tl_list_node_t *n) {
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n->next = n;
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n->prev = n;
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}
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STATIC volatile tl_list_node_t *tl_list_unlink(volatile tl_list_node_t *n) {
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volatile tl_list_node_t *next = n->next;
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volatile tl_list_node_t *prev = n->prev;
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prev->next = next;
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next->prev = prev;
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return next;
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}
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STATIC void tl_list_append(volatile tl_list_node_t *head, volatile tl_list_node_t *n) {
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n->next = head;
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n->prev = head->prev;
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head->prev->next = n;
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head->prev = n;
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}
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/******************************************************************************/
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// IPCC interface
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STATIC uint32_t get_ipccdba(void) {
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return *(uint32_t*)(OPTION_BYTE_BASE + 0x68) & 0x3fff;
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}
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STATIC volatile void **get_buffer_table(void) {
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return (volatile void**)(SRAM2A_BASE + get_ipccdba());
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}
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void ipcc_init(uint32_t irq_pri) {
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// Setup buffer table pointers
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volatile void **tab = get_buffer_table();
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tab[0] = &ipcc_mem_dev_info_tab[0];
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tab[1] = &ipcc_mem_ble_tab[0];
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tab[3] = &ipcc_mem_sys_tab[0];
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tab[4] = &ipcc_mem_memmgr_tab[0];
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// Start IPCC peripheral
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__HAL_RCC_IPCC_CLK_ENABLE();
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// Enable wanted IRQs
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IPCC->C1CR = 0;//IPCC_C1CR_RXOIE;
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IPCC->C1MR = 0xffffffff;
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NVIC_SetPriority(IPCC_C1_RX_IRQn, irq_pri);
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HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
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// Device info table will be populated by FUS/WS
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// Populate system table
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tl_list_init(&ipcc_mem_sys_queue);
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ipcc_mem_sys_tab[0] = (uint32_t)&ipcc_mem_sys_cmd_buf[0];
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ipcc_mem_sys_tab[1] = (uint32_t)&ipcc_mem_sys_queue;
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// Populate memory manager table
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tl_list_init(&ipcc_mem_memmgr_free_buf_queue);
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ipcc_mem_memmgr_tab[0] = (uint32_t)&ipcc_mem_memmgr_ble_spare_evt_buf[0];
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ipcc_mem_memmgr_tab[1] = (uint32_t)&ipcc_mem_memmgr_sys_spare_evt_buf[0];
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ipcc_mem_memmgr_tab[2] = (uint32_t)&ipcc_mem_memmgr_evt_pool[0];
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ipcc_mem_memmgr_tab[3] = sizeof(ipcc_mem_memmgr_evt_pool);
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ipcc_mem_memmgr_tab[4] = (uint32_t)&ipcc_mem_memmgr_free_buf_queue;
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ipcc_mem_memmgr_tab[5] = 0;
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ipcc_mem_memmgr_tab[6] = 0;
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// Populate BLE table
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tl_list_init(&ipcc_mem_ble_evt_queue);
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ipcc_mem_ble_tab[0] = (uint32_t)&ipcc_mem_ble_cmd_buf[0];
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ipcc_mem_ble_tab[1] = (uint32_t)&ipcc_mem_ble_cs_buf[0];
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ipcc_mem_ble_tab[2] = (uint32_t)&ipcc_mem_ble_evt_queue;
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ipcc_mem_ble_tab[3] = (uint32_t)&ipcc_mem_ble_hci_acl_data_buf[0];
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}
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STATIC int ipcc_wait_ack(unsigned int ch, uint32_t timeout_ms) {
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uint32_t t0 = mp_hal_ticks_ms();
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while (IPCC->C1TOC2SR & ch) {
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if (mp_hal_ticks_ms() - t0 > timeout_ms) {
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printf("ipcc_wait_ack: timeout\n");
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return -MP_ETIMEDOUT;
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}
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}
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// C2 cleared IPCC flag
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return 0;
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}
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STATIC int ipcc_wait_msg(unsigned int ch, uint32_t timeout_ms) {
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uint32_t t0 = mp_hal_ticks_ms();
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while (!(IPCC->C2TOC1SR & ch)) {
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if (mp_hal_ticks_ms() - t0 > timeout_ms) {
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printf("ipcc_wait_msg: timeout\n");
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return -MP_ETIMEDOUT;
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}
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}
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// C2 set IPCC flag
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return 0;
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}
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/******************************************************************************/
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// Transport layer HCI interface
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STATIC void tl_parse_hci_msg(const uint8_t *buf, parse_hci_info_t *parse) {
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const char *kind;
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size_t len = 3 + buf[2];
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switch (buf[0]) {
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case 0x02: {
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// Standard BT HCI ACL packet
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kind = "HCI_ACL";
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if (parse != NULL) {
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for (size_t i = 0; i < len; ++i) {
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parse->cb_fun(parse->cb_env, buf[i]);
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}
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}
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break;
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}
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case 0x04: {
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// Standard BT HCI event packet
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kind = "HCI_EVT";
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if (parse != NULL) {
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bool fix = false;
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if (buf[1] == 0x0e && len == 7 && buf[3] == 0x01 && buf[4] == 0x63 && buf[5] == 0x0c && buf[6] == 0x01) {
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len -= 1;
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fix = true;
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}
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for (size_t i = 0; i < len; ++i) {
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parse->cb_fun(parse->cb_env, buf[i]);
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}
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if (fix) {
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len += 1;
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parse->cb_fun(parse->cb_env, 0x00); // success
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}
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// Check for successful HCI_Reset event
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parse->was_hci_reset_evt = buf[1] == 0x0e && buf[2] == 0x04 && buf[3] == 0x01
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&& buf[4] == 0x03 && buf[5] == 0x0c && buf[6] == 0x00;
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}
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break;
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}
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case 0x11: {
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// Response packet
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// assert(buf[1] == 0x0e);
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kind = "VEND_RESP";
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//uint16_t cmd = buf[4] | buf[5] << 8;
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//uint8_t status = buf[6];
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break;
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}
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case 0x12: {
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// Event packet
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// assert(buf[1] == 0xff);
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kind = "VEND_EVT";
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//uint16_t evt = buf[3] | buf[4] << 8;
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break;
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}
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default:
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kind = "HCI_UNKNOWN";
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break;
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}
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#if HCI_TRACE
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printf("[% 8d] %s(%02x", mp_hal_ticks_ms(), kind, buf[0]);
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for (int i = 1; i < len; ++i) {
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printf(":%02x", buf[i]);
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}
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printf(")\n");
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#else
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(void)kind;
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#endif
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}
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STATIC void tl_check_msg(volatile tl_list_node_t *head, unsigned int ch, parse_hci_info_t *parse) {
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if (IPCC->C2TOC1SR & ch) {
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// Message available on CH2
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volatile tl_list_node_t *cur = head->next;
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bool free = false;
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while (cur != head) {
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tl_parse_hci_msg((uint8_t*)cur->body, parse);
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volatile tl_list_node_t *next = tl_list_unlink(cur);
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if ((void*)&ipcc_mem_memmgr_evt_pool[0] <= (void*)cur
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&& (void*)cur < (void*)&ipcc_mem_memmgr_evt_pool[MP_ARRAY_SIZE(ipcc_mem_memmgr_evt_pool)]) {
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// Place memory back in free pool
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tl_list_append(&ipcc_mem_memmgr_free_buf_queue, cur);
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free = true;
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}
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cur = next;
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}
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if (free) {
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// Notify change in free pool
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IPCC->C1SCR = IPCC_CH_MM << 16;
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}
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// Clear receive channel
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IPCC->C1SCR = ch;
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}
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}
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STATIC void tl_hci_cmd(uint8_t *cmd, unsigned int ch, uint8_t hdr, uint16_t opcode, size_t len, const uint8_t *buf) {
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tl_list_node_t *n = (tl_list_node_t*)cmd;
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n->next = n;
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n->prev = n;
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cmd[8] = hdr;
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cmd[9] = opcode;
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cmd[10] = opcode >> 8;
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cmd[11] = len;
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memcpy(&cmd[12], buf, len);
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// IPCC indicate
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IPCC->C1SCR = ch << 16;
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}
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STATIC void tl_sys_wait_resp(const uint8_t *buf, unsigned int ch) {
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if (ipcc_wait_ack(ch, 250) == 0) {
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tl_parse_hci_msg(buf, NULL);
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}
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}
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STATIC void tl_sys_hci_cmd_resp(uint16_t opcode, size_t len, const uint8_t *buf) {
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tl_hci_cmd((uint8_t*)&ipcc_mem_sys_cmd_buf, IPCC_CH_SYS, 0x10, opcode, len, buf);
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tl_sys_wait_resp((uint8_t*)&ipcc_mem_sys_cmd_buf, IPCC_CH_SYS);
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}
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STATIC void tl_ble_hci_cmd_resp(uint16_t opcode, size_t len, const uint8_t *buf) {
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tl_hci_cmd((uint8_t*)&ipcc_mem_ble_cmd_buf[0], IPCC_CH_BLE, 0x01, opcode, len, buf);
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ipcc_wait_msg(IPCC_CH_BLE, 250);
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tl_check_msg(&ipcc_mem_ble_evt_queue, IPCC_CH_BLE, NULL);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
// RF core interface
|
||||
|
||||
void rfcore_init(void) {
|
||||
// Ensure LSE is running
|
||||
rtc_init_finalise();
|
||||
|
||||
// Select LSE as RF wakeup source
|
||||
RCC->CSR = (RCC->CSR & ~RCC_CSR_RFWKPSEL) | 1 << RCC_CSR_RFWKPSEL_Pos;
|
||||
|
||||
// Initialise IPCC and shared memory structures
|
||||
ipcc_init(IRQ_PRI_SDIO);
|
||||
|
||||
// Boot the second core
|
||||
__SEV();
|
||||
__WFE();
|
||||
PWR->CR4 |= PWR_CR4_C2BOOT;
|
||||
}
|
||||
|
||||
static const struct {
|
||||
uint8_t* pBleBufferAddress; // unused
|
||||
uint32_t BleBufferSize; // unused
|
||||
uint16_t NumAttrRecord;
|
||||
uint16_t NumAttrServ;
|
||||
uint16_t AttrValueArrSize;
|
||||
uint8_t NumOfLinks;
|
||||
uint8_t ExtendedPacketLengthEnable;
|
||||
uint8_t PrWriteListSize;
|
||||
uint8_t MblockCount;
|
||||
uint16_t AttMtu;
|
||||
uint16_t SlaveSca;
|
||||
uint8_t MasterSca;
|
||||
uint8_t LsSource; // 0=LSE 1=internal RO
|
||||
uint32_t MaxConnEventLength;
|
||||
uint16_t HsStartupTime;
|
||||
uint8_t ViterbiEnable;
|
||||
uint8_t LlOnly; // 0=LL+Host, 1=LL only
|
||||
uint8_t HwVersion;
|
||||
} ble_init_params = {
|
||||
0,
|
||||
0,
|
||||
0, // NumAttrRecord
|
||||
0, // NumAttrServ
|
||||
0, // AttrValueArrSize
|
||||
1, // NumOfLinks
|
||||
1, // ExtendedPacketLengthEnable
|
||||
0, // PrWriteListSize
|
||||
0x79, // MblockCount
|
||||
0, // AttMtu
|
||||
0, // SlaveSca
|
||||
0, // MasterSca
|
||||
1, // LsSource
|
||||
0xffffffff, // MaxConnEventLength
|
||||
0x148, // HsStartupTime
|
||||
0, // ViterbiEnable
|
||||
1, // LlOnly
|
||||
0, // HwVersion
|
||||
};
|
||||
|
||||
void rfcore_ble_init(void) {
|
||||
// Clear any outstanding messages from ipcc_init
|
||||
tl_check_msg(&ipcc_mem_sys_queue, IPCC_CH_SYS, NULL);
|
||||
tl_check_msg(&ipcc_mem_ble_evt_queue, IPCC_CH_BLE, NULL);
|
||||
|
||||
// Configure and reset the BLE controller
|
||||
tl_sys_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_BLE_INIT), sizeof(ble_init_params), (const uint8_t*)&ble_init_params);
|
||||
tl_ble_hci_cmd_resp(HCI_OPCODE(0x03, 0x0003), 0, NULL);
|
||||
}
|
||||
|
||||
void rfcore_ble_hci_cmd(size_t len, const uint8_t *src) {
|
||||
#if HCI_TRACE
|
||||
printf("[% 8d] HCI_CMD(%02x", mp_hal_ticks_ms(), src[0]);
|
||||
for (int i = 1; i < len; ++i) {
|
||||
printf(":%02x", src[i]);
|
||||
}
|
||||
printf(")\n");
|
||||
#endif
|
||||
|
||||
tl_list_node_t *n;
|
||||
uint32_t ch;
|
||||
if (src[0] == 0x01) {
|
||||
n = (tl_list_node_t*)&ipcc_mem_ble_cmd_buf[0];
|
||||
ch = IPCC_CH_BLE;
|
||||
} else if (src[0] == 0x02) {
|
||||
n = (tl_list_node_t*)&ipcc_mem_ble_hci_acl_data_buf[0];
|
||||
ch = IPCC_CH_HCI_ACL;
|
||||
} else {
|
||||
printf("** UNEXPECTED HCI HDR: 0x%02x **\n", src[0]);
|
||||
return;
|
||||
}
|
||||
|
||||
n->next = n;
|
||||
n->prev = n;
|
||||
memcpy(n->body, src, len);
|
||||
|
||||
// IPCC indicate
|
||||
IPCC->C1SCR = ch << 16;
|
||||
}
|
||||
|
||||
void rfcore_ble_check_msg(int (*cb)(void*, uint8_t), void *env) {
|
||||
parse_hci_info_t parse = { cb, env, false };
|
||||
tl_check_msg(&ipcc_mem_ble_evt_queue, IPCC_CH_BLE, &parse);
|
||||
|
||||
// Intercept HCI_Reset events and reconfigure the controller following the reset
|
||||
if (parse.was_hci_reset_evt) {
|
||||
uint8_t buf[8];
|
||||
buf[0] = 0; // config offset
|
||||
buf[1] = 6; // config length
|
||||
mp_hal_get_mac(MP_HAL_MAC_BDADDR, &buf[2]);
|
||||
#define SWAP_UINT8(a, b) { uint8_t temp = a; a = b; b = temp; }
|
||||
SWAP_UINT8(buf[2], buf[7]);
|
||||
SWAP_UINT8(buf[3], buf[6]);
|
||||
SWAP_UINT8(buf[4], buf[5]);
|
||||
tl_ble_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_WRITE_CONFIG), 8, buf); // set BDADDR
|
||||
tl_ble_hci_cmd_resp(HCI_OPCODE(OGF_VENDOR, OCF_SET_TX_POWER), 2, (const uint8_t*)"\x00\x06"); // 0 dBm
|
||||
}
|
||||
}
|
||||
|
||||
#endif // defined(STM32WB)
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Damien P. George
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#ifndef MICROPY_INCLUDED_STM32_RFCORE_H
|
||||
#define MICROPY_INCLUDED_STM32_RFCORE_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void rfcore_init(void);
|
||||
|
||||
void rfcore_ble_init(void);
|
||||
void rfcore_ble_hci_cmd(size_t len, const uint8_t *src);
|
||||
void rfcore_ble_check_msg(int (*cb)(void*, uint8_t), void *env);
|
||||
|
||||
#endif // MICROPY_INCLUDED_STM32_RFCORE_H
|
||||
Loading…
Reference in New Issue