jebbatime
/
micropython
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Add support for SD card (not working).

osx
Damien 2013-10-24 00:22:27 +01:00
parent 6f08f8ce51
commit 7ee80bac8e
11 changed files with 5722 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
stm/Makefile
View File

@ -24,8 +24,8 @@ SRC_C = \
systick.c \
stm32fxxx_it.c \
usb.c \
sdio.c \
lexerstm.c \
# sd.c \
SRC_S = \
startup_stm32f40xx.s \
@ -63,6 +63,7 @@ SRC_STM = \
stm32f4xx_exti.c \
stm32f4xx_gpio.c \
stm32f4xx_tim.c \
stm32f4xx_sdio.c \
stm_misc.c \
usb_core.c \
usb_dcd.c \
@ -79,16 +80,8 @@ SRC_STM = \
usbd_msc_data.c \
usbd_msc_scsi.c \
usbd_storage_msd.c \
# not needed
# usb_otg.c \
# usb_hcd.c \
# usb_hcd_int.c \
# for SD card
# stm32f4xx_sdio.c \
# stm324x7i_eval.c \
# stm324x7i_eval_sdio_sd.c \
stm324x7i_eval.c \
stm324x7i_eval_sdio_sd.c \
OBJ = $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o) $(PY_O) $(SRC_FATFS:.c=.o) $(SRC_STM:.c=.o))

361
stm/lib/stm324x7i_eval.c 100644
View File

@ -0,0 +1,361 @@
/**
******************************************************************************
* @file STM324x7i_eval.c
* @author MCD Application Team
* @version V1.0.0
* @date 11-January-2013
* @brief This file provides
* - set of firmware functions to manage Leds, push-button and COM ports
* - low level initialization functions for SD card (on SDIO) and
* serial EEPROM (sEE)
* available on STM324x7I-EVAL evaluation board(MB786) from
* STMicroelectronics.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_dma.h"
#include "stm32f4xx_exti.h"
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_sdio.h"
//#include "stm32f4xx_syscfg.h"
#include "stm_misc.h"
#include "stm324x7i_eval.h"
//#include "stm32f4xx_i2c.h"
/** @addtogroup Utilities
* @{
*/
/** @addtogroup STM32_EVAL
* @{
*/
/** @addtogroup STM324x7I_EVAL
* @{
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL
* @brief This file provides firmware functions to manage Leds, push-buttons,
* COM ports, SD card on SDIO and serial EEPROM (sEE) available on
* STM324x7I-EVAL evaluation board from STMicroelectronics.
* @{
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Private_Variables
* @{
*/
#if 0
GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
LED4_GPIO_PORT};
const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
LED4_PIN};
const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
LED4_GPIO_CLK};
GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
KEY_BUTTON_GPIO_PORT};
const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
KEY_BUTTON_PIN};
const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
KEY_BUTTON_GPIO_CLK};
const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
TAMPER_BUTTON_EXTI_LINE,
KEY_BUTTON_EXTI_LINE};
const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
TAMPER_BUTTON_EXTI_PORT_SOURCE,
KEY_BUTTON_EXTI_PORT_SOURCE};
const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
TAMPER_BUTTON_EXTI_PIN_SOURCE,
KEY_BUTTON_EXTI_PIN_SOURCE};
const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
KEY_BUTTON_EXTI_IRQn};
GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT};
GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT};
const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK};
const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK};
const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN};
const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN};
const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE};
const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE};
const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF};
const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF};
DMA_InitTypeDef sEEDMA_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
#endif
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Private_Functions
* @{
*/
/**
* @brief DeInitializes the SDIO interface.
* @param None
* @retval None
*/
void SD_LowLevel_DeInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/*!< Disable SDIO Clock */
SDIO_ClockCmd(DISABLE);
/*!< Set Power State to OFF */
SDIO_SetPowerState(SDIO_PowerState_OFF);
/*!< DeInitializes the SDIO peripheral */
SDIO_DeInit();
/* Disable the SDIO APB2 Clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_MCO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_MCO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_MCO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_MCO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_MCO);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_MCO);
/* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PD.02 CMD line */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Configure PC.12 pin: CLK pin */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_Init(GPIOC, &GPIO_InitStructure);
}
/**
* @brief Initializes the SD Card and put it into StandBy State (Ready for
* data transfer).
* @param None
* @retval None
*/
void SD_LowLevel_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* GPIOC and GPIOD Periph clock enable */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_SDIO);
/* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PD.02 CMD line */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Configure PC.12 pin: CLK pin */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
// dpgeorge: switch is normally open, connected to VDD when card inserted
GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
/* Enable the SDIO APB2 Clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE);
/* Enable the DMA2 Clock */
RCC_AHB1PeriphClockCmd(SD_SDIO_DMA_CLK, ENABLE);
}
/**
* @brief Configures the DMA2 Channel4 for SDIO Tx request.
* @param BufferSRC: pointer to the source buffer
* @param BufferSize: buffer size
* @retval None
*/
void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize)
{
DMA_InitTypeDef SDDMA_InitStructure;
DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF);
/* DMA2 Stream3 or Stream6 disable */
DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE);
/* DMA2 Stream3 or Stream6 Config */
DMA_DeInit(SD_SDIO_DMA_STREAM);
SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL;
SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferSRC;
SDDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
SDDMA_InitStructure.DMA_BufferSize = BufferSize;
SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4;
SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4;
DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure);
DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE);
DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral);
/* DMA2 Stream3 or Stream6 enable */
DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE);
}
/**
* @brief Configures the DMA2 Channel4 for SDIO Rx request.
* @param BufferDST: pointer to the destination buffer
* @param BufferSize: buffer size
* @retval None
*/
void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize)
{
DMA_InitTypeDef SDDMA_InitStructure;
DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF);
/* DMA2 Stream3 or Stream6 disable */
DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE);
/* DMA2 Stream3 or Stream6 Config */
DMA_DeInit(SD_SDIO_DMA_STREAM);
SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL;
SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferDST;
SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
SDDMA_InitStructure.DMA_BufferSize = BufferSize;
SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4;
SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4;
DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure);
DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE);
DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral);
/* DMA2 Stream3 or Stream6 enable */
DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

370
stm/lib/stm324x7i_eval.h 100644
View File

@ -0,0 +1,370 @@
/**
******************************************************************************
* @file STM324x7i_eval.h
* @author MCD Application Team
* @version V1.0.0
* @date 11-January-2013
* @brief This file contains definitions for STM324x7I_EVAL's Leds, push-buttons
* and COM ports hardware resources.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM324x7I_EVAL_H
#define __STM324x7I_EVAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup Utilities
* @{
*/
/** @addtogroup STM32_EVAL
* @{
*/
/** @addtogroup STM324x7I_EVAL
* @{
*/
/** @addtogroup STM324x7I_EVAL_LOW_LEVEL
* @{
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Exported_Types
* @{
*/
#if 0
typedef enum
{
LED1 = 0,
LED2 = 1,
LED3 = 2,
LED4 = 3
} Led_TypeDef;
typedef enum
{
BUTTON_WAKEUP = 0,
BUTTON_TAMPER = 1,
BUTTON_KEY = 2,
BUTTON_RIGHT = 3,
BUTTON_LEFT = 4,
BUTTON_UP = 5,
BUTTON_DOWN = 6,
BUTTON_SEL = 7
} Button_TypeDef;
typedef enum
{
BUTTON_MODE_GPIO = 0,
BUTTON_MODE_EXTI = 1
} ButtonMode_TypeDef;
typedef enum
{
JOY_NONE = 0,
JOY_SEL = 1,
JOY_DOWN = 2,
JOY_LEFT = 3,
JOY_RIGHT = 4,
JOY_UP = 5
} JOYState_TypeDef
;
typedef enum
{
COM1 = 0,
COM2 = 1
} COM_TypeDef;
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Exported_Constants
* @{
*/
/**
* @brief Define for STM324x7I_EVAL board
*/
#if !defined (USE_STM324x7I_EVAL)
#define USE_STM324x7I_EVAL
#endif
/** @addtogroup STM324x7I_EVAL_LOW_LEVEL_LED
* @{
*/
#define LEDn 4
#define LED1_PIN GPIO_Pin_6
#define LED1_GPIO_PORT GPIOG
#define LED1_GPIO_CLK RCC_AHB1Periph_GPIOG
#define LED2_PIN GPIO_Pin_8
#define LED2_GPIO_PORT GPIOG
#define LED2_GPIO_CLK RCC_AHB1Periph_GPIOG
#define LED3_PIN GPIO_Pin_9
#define LED3_GPIO_PORT GPIOI
#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOI
#define LED4_PIN GPIO_Pin_7
#define LED4_GPIO_PORT GPIOC
#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOC
/**
* @}
*/
/** @addtogroup STM324x7I_EVAL_LOW_LEVEL_BUTTON
* @{
*/
#define BUTTONn 3 /*!< Joystick pins are connected to
an IO Expander (accessible through
I2C1 interface) */
/**
* @brief Wakeup push-button
*/
#define WAKEUP_BUTTON_PIN GPIO_Pin_0
#define WAKEUP_BUTTON_GPIO_PORT GPIOA
#define WAKEUP_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA
#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define WAKEUP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
#define WAKEUP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
/**
* @brief Tamper push-button
*/
#define TAMPER_BUTTON_PIN GPIO_Pin_13
#define TAMPER_BUTTON_GPIO_PORT GPIOC
#define TAMPER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOC
#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define TAMPER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC
#define TAMPER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13
#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
/**
* @brief Key push-button
*/
#define KEY_BUTTON_PIN GPIO_Pin_15
#define KEY_BUTTON_GPIO_PORT GPIOG
#define KEY_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG
#define KEY_BUTTON_EXTI_LINE EXTI_Line15
#define KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG
#define KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource15
#define KEY_BUTTON_EXTI_IRQn EXTI15_10_IRQn
/**
* @}
*/
/** @addtogroup STM324x7I_EVAL_LOW_LEVEL_COM
* @{
*/
#define COMn 1
/**
* @brief Definition for COM port1, connected to USART3
*/
#define EVAL_COM1 USART3
#define EVAL_COM1_CLK RCC_APB1Periph_USART3
#define EVAL_COM1_TX_PIN GPIO_Pin_10
#define EVAL_COM1_TX_GPIO_PORT GPIOC
#define EVAL_COM1_TX_GPIO_CLK RCC_AHB1Periph_GPIOC
#define EVAL_COM1_TX_SOURCE GPIO_PinSource10
#define EVAL_COM1_TX_AF GPIO_AF_USART3
#define EVAL_COM1_RX_PIN GPIO_Pin_11
#define EVAL_COM1_RX_GPIO_PORT GPIOC
#define EVAL_COM1_RX_GPIO_CLK RCC_AHB1Periph_GPIOC
#define EVAL_COM1_RX_SOURCE GPIO_PinSource11
#define EVAL_COM1_RX_AF GPIO_AF_USART3
#define EVAL_COM1_IRQn USART3_IRQn
#endif
/**
* @}
*/
/** @addtogroup STM324x7I_EVAL_LOW_LEVEL_SD_FLASH
* @{
*/
/**
* @brief SD FLASH SDIO Interface
*/
#define SD_DETECT_PIN GPIO_Pin_13 /* PC.13 */
#define SD_DETECT_GPIO_PORT GPIOC /* GPIOC */
#define SD_DETECT_GPIO_CLK RCC_AHB1Periph_GPIOC
#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
/**
* @brief SDIO Intialization Frequency (400KHz max)
*/
#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
/**
* @brief SDIO Data Transfer Frequency (25MHz max)
*/
#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
#define SD_SDIO_DMA DMA2
#define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2
#define SD_SDIO_DMA_STREAM3 3
//#define SD_SDIO_DMA_STREAM6 6
#ifdef SD_SDIO_DMA_STREAM3
#define SD_SDIO_DMA_STREAM DMA2_Stream3
#define SD_SDIO_DMA_CHANNEL DMA_Channel_4
#define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF3
#define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3
#define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3
#define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3
#define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3
#define SD_SDIO_DMA_IRQn DMA2_Stream3_IRQn
#define SD_SDIO_DMA_IRQHANDLER DMA2_Stream3_IRQHandler
#elif defined SD_SDIO_DMA_STREAM6
#define SD_SDIO_DMA_STREAM DMA2_Stream6
#define SD_SDIO_DMA_CHANNEL DMA_Channel_4
#define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF6
#define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6
#define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF6
#define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF6
#define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6
#define SD_SDIO_DMA_IRQn DMA2_Stream6_IRQn
#define SD_SDIO_DMA_IRQHANDLER DMA2_Stream6_IRQHandler
#endif /* SD_SDIO_DMA_STREAM3 */
/**
* @}
*/
/** @addtogroup STM324x7I_EVAL_LOW_LEVEL_I2C_EE
* @{
*/
/**
* @brief I2C EEPROM Interface pins
*/
#if 0
#define sEE_I2C I2C1
#define sEE_I2C_CLK RCC_APB1Periph_I2C1
#define sEE_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */
#define sEE_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */
#define sEE_I2C_SCL_GPIO_CLK RCC_AHB1Periph_GPIOB
#define sEE_I2C_SCL_SOURCE GPIO_PinSource6
#define sEE_I2C_SCL_AF GPIO_AF_I2C1
#define sEE_I2C_SDA_PIN GPIO_Pin_9 /* PB.09 */
#define sEE_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */
#define sEE_I2C_SDA_GPIO_CLK RCC_AHB1Periph_GPIOB
#define sEE_I2C_SDA_SOURCE GPIO_PinSource9
#define sEE_I2C_SDA_AF GPIO_AF_I2C1
#define sEE_M24C64_32
#define sEE_I2C_DMA DMA1
#define sEE_I2C_DMA_CHANNEL DMA_Channel_1
#define sEE_I2C_DMA_STREAM_TX DMA1_Stream6
#define sEE_I2C_DMA_STREAM_RX DMA1_Stream0
#define sEE_I2C_DMA_CLK RCC_AHB1Periph_DMA1
#define sEE_I2C_DR_Address ((uint32_t)0x40005410)
#define sEE_USE_DMA
#define sEE_I2C_DMA_TX_IRQn DMA1_Stream6_IRQn
#define sEE_I2C_DMA_RX_IRQn DMA1_Stream0_IRQn
#define sEE_I2C_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler
#define sEE_I2C_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define sEE_I2C_DMA_PREPRIO 0
#define sEE_I2C_DMA_SUBPRIO 0
#define sEE_TX_DMA_FLAG_FEIF DMA_FLAG_FEIF6
#define sEE_TX_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6
#define sEE_TX_DMA_FLAG_TEIF DMA_FLAG_TEIF6
#define sEE_TX_DMA_FLAG_HTIF DMA_FLAG_HTIF6
#define sEE_TX_DMA_FLAG_TCIF DMA_FLAG_TCIF6
#define sEE_RX_DMA_FLAG_FEIF DMA_FLAG_FEIF0
#define sEE_RX_DMA_FLAG_DMEIF DMA_FLAG_DMEIF0
#define sEE_RX_DMA_FLAG_TEIF DMA_FLAG_TEIF0
#define sEE_RX_DMA_FLAG_HTIF DMA_FLAG_HTIF0
#define sEE_RX_DMA_FLAG_TCIF DMA_FLAG_TCIF0
#define sEE_DIRECTION_TX 0
#define sEE_DIRECTION_RX 1
/* Time constant for the delay caclulation allowing to have a millisecond
incrementing counter. This value should be equal to (System Clock / 1000).
ie. if system clock = 168MHz then sEE_TIME_CONST should be 168. */
#define sEE_TIME_CONST 168
#endif
/**
* @}
*/
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Exported_Functions
* @{
*/
void SD_LowLevel_DeInit(void);
void SD_LowLevel_Init(void);
void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize);
void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize);
#if 0
void sEE_LowLevel_DeInit(void);
void sEE_LowLevel_Init(void);
void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
#endif
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM324x7I_EVAL_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2949
stm/lib/stm324x7i_eval_sdio_sd.c 100644
View File

File diff suppressed because it is too large Load Diff

408
stm/lib/stm324x7i_eval_sdio_sd.h 100644
View File

@ -0,0 +1,408 @@
/**
******************************************************************************
* @file stm324x7i_eval_sdio_sd.h
* @author MCD Application Team
* @version V1.0.0
* @date 11-January-2013
* @brief This file contains all the functions prototypes for the SD Card
* stm324x7i_eval_sdio_sd driver firmware library.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM324x7I_EVAL_SDIO_SD_H
#define __STM324x7I_EVAL_SDIO_SD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm324x7i_eval.h"
/** @addtogroup Utilities
* @{
*/
/** @addtogroup STM32_EVAL
* @{
*/
/** @addtogroup STM324x7I_EVAL
* @{
*/
/** @addtogroup STM324x7I_EVAL_SDIO_SD
* @{
*/
/** @defgroup STM324x7I_EVAL_SDIO_SD_Exported_Types
* @{
*/
typedef enum
{
/**
* @brief SDIO specific error defines
*/
SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */
SD_DATA_CRC_FAIL = (2), /*!< Data bock sent/received (CRC check Failed) */
SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
SD_DATA_TIMEOUT = (4), /*!< Data time out */
SD_TX_UNDERRUN = (5), /*!< Transmit FIFO under-run */
SD_RX_OVERRUN = (6), /*!< Receive FIFO over-run */
SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in widE bus mode */
SD_CMD_OUT_OF_RANGE = (8), /*!< CMD's argument was out of range.*/
SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs.*/
SD_BAD_ERASE_PARAM = (12), /*!< An Invalid selection for erase groups */
SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */
SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */
SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */
SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */
SD_CC_ERROR = (18), /*!< Internal card controller error */
SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or Unknown error */
SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */
SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */
SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */
SD_WP_ERASE_SKIP = (23), /*!< only partial address space was erased */
SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */
SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */
SD_INVALID_VOLTRANGE = (27),
SD_ADDR_OUT_OF_RANGE = (28),
SD_SWITCH_ERROR = (29),
SD_SDIO_DISABLED = (30),
SD_SDIO_FUNCTION_BUSY = (31),
SD_SDIO_FUNCTION_FAILED = (32),
SD_SDIO_UNKNOWN_FUNCTION = (33),
/**
* @brief Standard error defines
*/
SD_INTERNAL_ERROR,
SD_NOT_CONFIGURED,
SD_REQUEST_PENDING,
SD_REQUEST_NOT_APPLICABLE,
SD_INVALID_PARAMETER,
SD_UNSUPPORTED_FEATURE,
SD_UNSUPPORTED_HW,
SD_ERROR,
SD_OK = 0
} SD_Error;
/**
* @brief SDIO Transfer state
*/
typedef enum
{
SD_TRANSFER_OK = 0,
SD_TRANSFER_BUSY = 1,
SD_TRANSFER_ERROR
} SDTransferState;
/**
* @brief SD Card States
*/
typedef enum
{
SD_CARD_READY = ((uint32_t)0x00000001),
SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002),
SD_CARD_STANDBY = ((uint32_t)0x00000003),
SD_CARD_TRANSFER = ((uint32_t)0x00000004),
SD_CARD_SENDING = ((uint32_t)0x00000005),
SD_CARD_RECEIVING = ((uint32_t)0x00000006),
SD_CARD_PROGRAMMING = ((uint32_t)0x00000007),
SD_CARD_DISCONNECTED = ((uint32_t)0x00000008),
SD_CARD_ERROR = ((uint32_t)0x000000FF)
}SDCardState;
/**
* @brief Card Specific Data: CSD Register
*/
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
__IO uint8_t SysSpecVersion; /*!< System specification version */
__IO uint8_t Reserved1; /*!< Reserved */
__IO uint8_t TAAC; /*!< Data read access-time 1 */
__IO uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
__IO uint16_t CardComdClasses; /*!< Card command classes */
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
__IO uint8_t DSRImpl; /*!< DSR implemented */
__IO uint8_t Reserved2; /*!< Reserved */
__IO uint32_t DeviceSize; /*!< Device Size */
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
__IO uint8_t EraseGrSize; /*!< Erase group size */
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserded */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGrouop; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
__IO uint8_t FileFormat; /*!< File Format */
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< always 1*/
} SD_CSD;
/**
* @brief Card Identification Data: CID Register
*/
typedef struct
{
__IO uint8_t ManufacturerID; /*!< ManufacturerID */
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
__IO uint32_t ProdName1; /*!< Product Name part1 */
__IO uint8_t ProdName2; /*!< Product Name part2*/
__IO uint8_t ProdRev; /*!< Product Revision */
__IO uint32_t ProdSN; /*!< Product Serial Number */
__IO uint8_t Reserved1; /*!< Reserved1 */
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< always 1 */
} SD_CID;
/**
* @brief SD Card Status
*/
typedef struct
{
__IO uint8_t DAT_BUS_WIDTH;
__IO uint8_t SECURED_MODE;
__IO uint16_t SD_CARD_TYPE;
__IO uint32_t SIZE_OF_PROTECTED_AREA;
__IO uint8_t SPEED_CLASS;
__IO uint8_t PERFORMANCE_MOVE;
__IO uint8_t AU_SIZE;
__IO uint16_t ERASE_SIZE;
__IO uint8_t ERASE_TIMEOUT;
__IO uint8_t ERASE_OFFSET;
} SD_CardStatus;
/**
* @brief SD Card information
*/
typedef struct
{
SD_CSD SD_csd;
SD_CID SD_cid;
uint64_t CardCapacity; /*!< Card Capacity */
uint32_t CardBlockSize; /*!< Card Block Size */
uint16_t RCA;
uint8_t CardType;
} SD_CardInfo;
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_SDIO_SD_Exported_Constants
* @{
*/
/**
* @brief SDIO Commands Index
*/
#define SD_CMD_GO_IDLE_STATE ((uint8_t)0)
#define SD_CMD_SEND_OP_COND ((uint8_t)1)
#define SD_CMD_ALL_SEND_CID ((uint8_t)2)
#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */
#define SD_CMD_SET_DSR ((uint8_t)4)
#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5)
#define SD_CMD_HS_SWITCH ((uint8_t)6)
#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7)
#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8)
#define SD_CMD_SEND_CSD ((uint8_t)9)
#define SD_CMD_SEND_CID ((uint8_t)10)
#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */
#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12)
#define SD_CMD_SEND_STATUS ((uint8_t)13)
#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15)
#define SD_CMD_SET_BLOCKLEN ((uint8_t)16)
#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)
#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18)
#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19)
#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */
#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */
#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)
#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)
#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */
#define SD_CMD_PROG_CSD ((uint8_t)27)
#define SD_CMD_SET_WRITE_PROT ((uint8_t)28)
#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29)
#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30)
#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write
block to be erased. (For SD card only) */
#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the
continuous range to be erased. (For SD card only) */
#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased.
(For MMC card only spec 3.31) */
#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the
continuous range to be erased. (For MMC card only spec 3.31) */
#define SD_CMD_ERASE ((uint8_t)38)
#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */
#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */
#define SD_CMD_LOCK_UNLOCK ((uint8_t)42)
#define SD_CMD_APP_CMD ((uint8_t)55)
#define SD_CMD_GEN_CMD ((uint8_t)56)
#define SD_CMD_NO_CMD ((uint8_t)64)
/**
* @brief Following commands are SD Card Specific commands.
* SDIO_APP_CMD should be sent before sending these commands.
*/
#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */
#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */
#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */
#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */
#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */
#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */
#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */
/**
* @brief Following commands are SD Card Specific security commands.
* SDIO_APP_CMD should be sent before sending these commands.
*/
#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */
#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */
#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */
#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */
#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */
#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */
#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */
#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */
#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */
#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */
#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */
/* Uncomment the following line to select the SDIO Data transfer mode */
#if !defined (SD_DMA_MODE) && !defined (SD_POLLING_MODE)
/*#define SD_DMA_MODE ((uint32_t)0x00000000)*/
#define SD_POLLING_MODE ((uint32_t)0x00000002)
#endif
/**
* @brief SD detection on its memory slot
*/
#define SD_PRESENT ((uint8_t)0x01)
#define SD_NOT_PRESENT ((uint8_t)0x00)
/**
* @brief Supported SD Memory Cards
*/
#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003)
#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_SDIO_SD_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup STM324x7I_EVAL_SDIO_SD_Exported_Functions
* @{
*/
void SD_DeInit(void);
SD_Error SD_Init(void);
SDTransferState SD_GetStatus(void);
SDCardState SD_GetState(void);
uint8_t SD_Detect(void);
SD_Error SD_PowerON(void);
SD_Error SD_PowerOFF(void);
SD_Error SD_InitializeCards(void);
SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus);
SD_Error SD_EnableWideBusOperation(uint32_t WideMode);
SD_Error SD_SelectDeselect(uint64_t addr);
SD_Error SD_ReadBlock(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize);
SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
SD_Error SD_WriteBlock(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize);
SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
SDTransferState SD_GetTransferState(void);
SD_Error SD_StopTransfer(void);
SD_Error SD_Erase(uint64_t startaddr, uint64_t endaddr);
SD_Error SD_SendStatus(uint32_t *pcardstatus);
SD_Error SD_SendSDStatus(uint32_t *psdstatus);
SD_Error SD_ProcessIRQSrc(void);
void SD_ProcessDMAIRQ(void);
SD_Error SD_WaitReadOperation(void);
SD_Error SD_WaitWriteOperation(void);
SD_Error SD_HighSpeed(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM324x7I_EVAL_SDIO_SD_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1012
stm/lib/stm32f4xx_sdio.c 100644
View File

File diff suppressed because it is too large Load Diff

536
stm/lib/stm32f4xx_sdio.h 100644
View File

@ -0,0 +1,536 @@
/**
******************************************************************************
* @file stm32f4xx_sdio.h
* @author MCD Application Team
* @version V1.1.0
* @date 11-January-2013
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_SDIO_H
#define __STM32F4xx_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
{
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SDIO_Clock_Edge */
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
enabled or disabled.
This parameter can be a value of @ref SDIO_Clock_Bypass */
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
disabled when the bus is idle.
This parameter can be a value of @ref SDIO_Clock_Power_Save */
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
This parameter can be a value of @ref SDIO_Bus_Wide */
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
This parameter can be a value between 0x00 and 0xFF. */
} SDIO_InitTypeDef;
typedef struct
{
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register */
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_CPSM_State */
} SDIO_CmdInitTypeDef;
typedef struct
{
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
This parameter can be a value of @ref SDIO_Data_Block_Size */
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDIO_Transfer_Direction */
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDIO_Transfer_Type */
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_DPSM_State */
} SDIO_DataInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIO_Exported_Constants
* @{
*/
/** @defgroup SDIO_Clock_Edge
* @{
*/
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
((EDGE) == SDIO_ClockEdge_Falling))
/**
* @}
*/
/** @defgroup SDIO_Clock_Bypass
* @{
*/
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
((BYPASS) == SDIO_ClockBypass_Enable))
/**
* @}
*/
/** @defgroup SDIO_Clock_Power_Save
* @{
*/
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
((SAVE) == SDIO_ClockPowerSave_Enable))
/**
* @}
*/
/** @defgroup SDIO_Bus_Wide
* @{
*/
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
((WIDE) == SDIO_BusWide_8b))
/**
* @}
*/
/** @defgroup SDIO_Hardware_Flow_Control
* @{
*/
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
((CONTROL) == SDIO_HardwareFlowControl_Enable))
/**
* @}
*/
/** @defgroup SDIO_Power_State
* @{
*/
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
/**
* @}
*/
/** @defgroup SDIO_Interrupt_sources
* @{
*/
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Command_Index
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
/**
* @}
*/
/** @defgroup SDIO_Response_Type
* @{
*/
#define SDIO_Response_No ((uint32_t)0x00000000)
#define SDIO_Response_Short ((uint32_t)0x00000040)
#define SDIO_Response_Long ((uint32_t)0x000000C0)
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
((RESPONSE) == SDIO_Response_Short) || \
((RESPONSE) == SDIO_Response_Long))
/**
* @}
*/
/** @defgroup SDIO_Wait_Interrupt_State
* @{
*/
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
((WAIT) == SDIO_Wait_Pend))
/**
* @}
*/
/** @defgroup SDIO_CPSM_State
* @{
*/
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
/**
* @}
*/
/** @defgroup SDIO_Response_Registers
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
#define SDIO_RESP2 ((uint32_t)0x00000004)
#define SDIO_RESP3 ((uint32_t)0x00000008)
#define SDIO_RESP4 ((uint32_t)0x0000000C)
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
/**
* @}
*/
/** @defgroup SDIO_Data_Length
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
/**
* @}
*/
/** @defgroup SDIO_Data_Block_Size
* @{
*/
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
((SIZE) == SDIO_DataBlockSize_2b) || \
((SIZE) == SDIO_DataBlockSize_4b) || \
((SIZE) == SDIO_DataBlockSize_8b) || \
((SIZE) == SDIO_DataBlockSize_16b) || \
((SIZE) == SDIO_DataBlockSize_32b) || \
((SIZE) == SDIO_DataBlockSize_64b) || \
((SIZE) == SDIO_DataBlockSize_128b) || \
((SIZE) == SDIO_DataBlockSize_256b) || \
((SIZE) == SDIO_DataBlockSize_512b) || \
((SIZE) == SDIO_DataBlockSize_1024b) || \
((SIZE) == SDIO_DataBlockSize_2048b) || \
((SIZE) == SDIO_DataBlockSize_4096b) || \
((SIZE) == SDIO_DataBlockSize_8192b) || \
((SIZE) == SDIO_DataBlockSize_16384b))
/**
* @}
*/
/** @defgroup SDIO_Transfer_Direction
* @{
*/
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
((DIR) == SDIO_TransferDir_ToSDIO))
/**
* @}
*/
/** @defgroup SDIO_Transfer_Type
* @{
*/
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
((MODE) == SDIO_TransferMode_Block))
/**
* @}
*/
/** @defgroup SDIO_DPSM_State
* @{
*/
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
/**
* @}
*/
/** @defgroup SDIO_Flags
* @{
*/
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
((FLAG) == SDIO_FLAG_TXUNDERR) || \
((FLAG) == SDIO_FLAG_RXOVERR) || \
((FLAG) == SDIO_FLAG_CMDREND) || \
((FLAG) == SDIO_FLAG_CMDSENT) || \
((FLAG) == SDIO_FLAG_DATAEND) || \
((FLAG) == SDIO_FLAG_STBITERR) || \
((FLAG) == SDIO_FLAG_DBCKEND) || \
((FLAG) == SDIO_FLAG_CMDACT) || \
((FLAG) == SDIO_FLAG_TXACT) || \
((FLAG) == SDIO_FLAG_RXACT) || \
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
((FLAG) == SDIO_FLAG_TXFIFOF) || \
((FLAG) == SDIO_FLAG_RXFIFOF) || \
((FLAG) == SDIO_FLAG_TXFIFOE) || \
((FLAG) == SDIO_FLAG_RXFIFOE) || \
((FLAG) == SDIO_FLAG_TXDAVL) || \
((FLAG) == SDIO_FLAG_RXDAVL) || \
((FLAG) == SDIO_FLAG_SDIOIT) || \
((FLAG) == SDIO_FLAG_CEATAEND))
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
((IT) == SDIO_IT_DCRCFAIL) || \
((IT) == SDIO_IT_CTIMEOUT) || \
((IT) == SDIO_IT_DTIMEOUT) || \
((IT) == SDIO_IT_TXUNDERR) || \
((IT) == SDIO_IT_RXOVERR) || \
((IT) == SDIO_IT_CMDREND) || \
((IT) == SDIO_IT_CMDSENT) || \
((IT) == SDIO_IT_DATAEND) || \
((IT) == SDIO_IT_STBITERR) || \
((IT) == SDIO_IT_DBCKEND) || \
((IT) == SDIO_IT_CMDACT) || \
((IT) == SDIO_IT_TXACT) || \
((IT) == SDIO_IT_RXACT) || \
((IT) == SDIO_IT_TXFIFOHE) || \
((IT) == SDIO_IT_RXFIFOHF) || \
((IT) == SDIO_IT_TXFIFOF) || \
((IT) == SDIO_IT_RXFIFOF) || \
((IT) == SDIO_IT_TXFIFOE) || \
((IT) == SDIO_IT_RXFIFOE) || \
((IT) == SDIO_IT_TXDAVL) || \
((IT) == SDIO_IT_RXDAVL) || \
((IT) == SDIO_IT_SDIOIT) || \
((IT) == SDIO_IT_CEATAEND))
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Read_Wait_Mode
* @{
*/
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the SDIO configuration to the default reset state ****/
void SDIO_DeInit(void);
/* Initialization and Configuration functions *********************************/
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_ClockCmd(FunctionalState NewState);
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
uint32_t SDIO_GetPowerState(void);
/* Command path state machine (CPSM) management functions *********************/
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
uint8_t SDIO_GetCommandResponse(void);
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
/* Data path state machine (DPSM) management functions ************************/
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
uint32_t SDIO_GetDataCounter(void);
uint32_t SDIO_ReadData(void);
void SDIO_WriteData(uint32_t Data);
uint32_t SDIO_GetFIFOCount(void);
/* SDIO IO Cards mode management functions ************************************/
void SDIO_StartSDIOReadWait(FunctionalState NewState);
void SDIO_StopSDIOReadWait(FunctionalState NewState);
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(FunctionalState NewState);
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
/* CE-ATA mode management functions *******************************************/
void SDIO_CommandCompletionCmd(FunctionalState NewState);
void SDIO_CEATAITCmd(FunctionalState NewState);
void SDIO_SendCEATACmd(FunctionalState NewState);
/* DMA transfers management functions *****************************************/
void SDIO_DMACmd(FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_SDIO_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

20
stm/main.c
View File

@ -460,6 +460,21 @@ int main(void) {
// enable the CCM RAM and the GPIO's
RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN | RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN;
// configure SDIO pins to be high to start with (doesn't seem to fix problem...)
{
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOC, &GPIO_InitStructure);
// Configure PD.02 CMD line
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_Init(GPIOD, &GPIO_InitStructure);
}
// basic sub-system init
sys_tick_init();
led_init();
@ -813,8 +828,9 @@ soft_reset:
}
// SD card testing
if (0) {
//sdio_init();
if (1) {
extern void sdio_init(void);
sdio_init();
}
printf("PYB: sync filesystems\n");

1
stm/mma.c
View File

@ -61,6 +61,7 @@ void mma_init(void) {
I2C1->CR1 |= I2C_CR1_PE;
// wait 20ms, then turn on AVDD, then wait 20ms again; this seems to work, but maybe can decrease delays
// doesn't work for soft reboot; 50ms doesn't work either...
sys_tick_delay_ms(20);
GPIOB->BSRRL = GPIO_Pin_5;
sys_tick_delay_ms(20);

60
stm/sdio.c 100644
View File

@ -0,0 +1,60 @@
// TODO
// make it work with DMA
#include <stdio.h>
//#include "stm32f4xx_sdio.h"
#include "stm324x7i_eval_sdio_sd.h"
#include "misc.h"
#include "systick.h"
#define BLOCK_SIZE 512 /* Block Size in Bytes */
uint8_t aBuffer_Block_Rx[BLOCK_SIZE];
void sdio_init(void) {
SD_Error error = SD_Init();
printf("Init: %x\n", error);
uint8_t det = SD_Detect();
printf("Detc: %x\n", det);
if (!det) {
printf("no card detected\n");
SD_PowerOFF();
SD_DeInit();
return;
}
// read a block!
error = SD_ReadBlock(aBuffer_Block_Rx, 512, BLOCK_SIZE);
printf("ReadBlock: %d\n", error);
/*
// Check if the Transfer is finished
error = SD_WaitReadOperation();
printf("WaitReadOp: %d\n", error);
*/
uint32_t stc = sys_tick_counter;
while (SD_GetStatus() != SD_TRANSFER_OK) {
if (sys_tick_has_passed(stc, 2000)) {
printf("timeout waiting for read to finish\n");
break;
}
}
printf("done!!\n");
printf("%.16s", aBuffer_Block_Rx);
/*
snprintf((char*)aBuffer_Block_Rx, BLOCK_SIZE, "Here is some data back for you!\nBLOCK_SIZE=%d\n", BLOCK_SIZE);
error = SD_WriteBlock(aBuffer_Block_Rx, 512, BLOCK_SIZE);
printf("WriteBlock: %d\n", error);
while (SD_GetStatus() != SD_TRANSFER_OK) {
}
printf("done writing!\n");
*/
SD_PowerOFF();
SD_DeInit();
}

4
stm/stm32fxxx_it.c
View File

@ -230,7 +230,9 @@ void OTG_HS_EP1_OUT_IRQHandler(void)
void SDIO_IRQHandler(void)
{
/* Process All SDIO Interrupt Sources */
//SD_ProcessIRQSrc();
// dpgeorge: i don't think this is used at the moment...
extern void SD_ProcessIRQSrc(void);
SD_ProcessIRQSrc();
}
/******************************************************************************/