stm32/sdram: Integrate SDRAM driver into rest of code.
If SDRAM is configured and enabled for a board then it is used for the MicroPython GC heap.pull/1/head
Andrew Leech
Damien George
parent
7ae053abfd
commit
a1db1506a2
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@ -253,6 +253,7 @@ SRC_C = \
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spibdev.c \
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storage.c \
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sdcard.c \
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sdram.c \
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fatfs_port.c \
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lcd.c \
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accel.c \
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@ -305,10 +306,17 @@ ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 h7 l4))
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SRC_HAL += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_,\
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hal_sd.c \
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ll_sdmmc.c \
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ll_fmc.c \
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ll_usb.c \
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)
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endif
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ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 h7))
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SRC_HAL += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_,\
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hal_sdram.c \
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)
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endif
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ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),STM32H743xx))
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SRC_HAL += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_, hal_fdcan.c)
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else
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@ -55,6 +55,7 @@
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#include "rtc.h"
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#include "storage.h"
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#include "sdcard.h"
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#include "sdram.h"
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#include "rng.h"
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#include "accel.h"
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#include "servo.h"
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@ -555,7 +556,16 @@ soft_reset:
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mp_stack_set_limit((char*)&_estack - (char*)&_heap_end - 1024);
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// GC init
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#if MICROPY_HW_SDRAM_SIZE
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sdram_init();
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#if MICROPY_HW_SDRAM_STARTUP_TEST
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sdram_test(true);
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#endif
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gc_init(sdram_start(), sdram_end());
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#else
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gc_init(&_heap_start, &_heap_end);
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#endif
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#if MICROPY_ENABLE_PYSTACK
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static mp_obj_t pystack[384];
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@ -8,14 +8,15 @@
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*/
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#include <stdio.h>
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#include <stdbool.h>
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#include <stm32f4xx_hal.h>
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#include "mdefs.h"
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#include "pincfg.h"
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#include <string.h>
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "pin.h"
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#include "pin_static_af.h"
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#include "systick.h"
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#include "sdram.h"
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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#define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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@ -28,43 +29,109 @@
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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static SDRAM_HandleTypeDef hsdram;
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static FMC_SDRAM_TimingTypeDef SDRAM_Timing;
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static FMC_SDRAM_CommandTypeDef command;
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#if defined(MICROPY_HW_FMC_SDCKE0) && defined(MICROPY_HW_FMC_SDNE0)
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#define FMC_SDRAM_BANK FMC_SDRAM_BANK1
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#define FMC_SDRAM_CMD_TARGET_BANK FMC_SDRAM_CMD_TARGET_BANK1
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#define SDRAM_START_ADDRESS 0xC0000000
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#elif defined(MICROPY_HW_FMC_SDCKE1) && defined(MICROPY_HW_FMC_SDNE1)
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#define FMC_SDRAM_BANK FMC_SDRAM_BANK2
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#define FMC_SDRAM_CMD_TARGET_BANK FMC_SDRAM_CMD_TARGET_BANK2
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#define SDRAM_START_ADDRESS 0xD0000000
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#endif
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#ifdef FMC_SDRAM_BANK
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static void sdram_init_seq(SDRAM_HandleTypeDef
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*hsdram, FMC_SDRAM_CommandTypeDef *command);
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extern void __fatal_error(const char *msg);
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bool sdram_init()
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{
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bool sdram_init(void) {
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SDRAM_HandleTypeDef hsdram;
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FMC_SDRAM_TimingTypeDef SDRAM_Timing;
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FMC_SDRAM_CommandTypeDef command;
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__HAL_RCC_FMC_CLK_ENABLE();
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#if defined(MICROPY_HW_FMC_SDCKE0)
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDCKE0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDCKE0);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNE0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNE0);
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#elif defined(MICROPY_HW_FMC_SDCKE1)
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDCKE1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDCKE1);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNE1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNE1);
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#endif
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDCLK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDCLK);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNCAS, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNCAS);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNRAS, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNRAS);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_SDNWE, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_SDNWE);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_BA0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_BA0);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_BA1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_BA1);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_NBL0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_NBL0);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_NBL1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_NBL1);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A0);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A1);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A2);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A3);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A4, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A4);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A5, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A5);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A6, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A6);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A7, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A7);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A8, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A8);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A9, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A9);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A10, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A10);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A11, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A11);
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#ifdef MICROPY_HW_FMC_A12
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_A12, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_A12);
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#endif
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D0);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D1);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D2);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D3);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D4, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D4);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D5, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D5);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D6, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D6);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D7, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D7);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D8, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D8);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D9, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D9);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D10, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D10);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D11, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D11);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D12, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D12);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D13, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D13);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D14, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D14);
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mp_hal_pin_config_alt_static(MICROPY_HW_FMC_D15, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_FMC_D15);
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/* SDRAM device configuration */
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hsdram.Instance = FMC_SDRAM_DEVICE;
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/* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
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/* TMRD: 2 Clock cycles */
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SDRAM_Timing.LoadToActiveDelay = 2;
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SDRAM_Timing.LoadToActiveDelay = MICROPY_HW_SDRAM_TIMING_TMRD;
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/* TXSR: min=70ns (6x11.90ns) */
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SDRAM_Timing.ExitSelfRefreshDelay = 7;
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/* TRAS: min=45ns (4x11.90ns) max=120k (ns) */
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SDRAM_Timing.SelfRefreshTime = 7;
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/* TRC: min=67ns (6x11.90ns) */
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SDRAM_Timing.RowCycleDelay = 10;
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/* TWR: 2 Clock cycles */
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SDRAM_Timing.WriteRecoveryTime = 2;
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/* TRP: 20ns => 2x11.90ns */
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SDRAM_Timing.RPDelay = 3;
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/* TRCD: 20ns => 2x11.90ns */
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SDRAM_Timing.RCDDelay = 3;
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SDRAM_Timing.ExitSelfRefreshDelay = MICROPY_HW_SDRAM_TIMING_TXSR;
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/* TRAS */
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SDRAM_Timing.SelfRefreshTime = MICROPY_HW_SDRAM_TIMING_TRAS;
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/* TRC */
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SDRAM_Timing.RowCycleDelay = MICROPY_HW_SDRAM_TIMING_TRC;
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/* TWR */
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SDRAM_Timing.WriteRecoveryTime = MICROPY_HW_SDRAM_TIMING_TWR;
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/* TRP */
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SDRAM_Timing.RPDelay = MICROPY_HW_SDRAM_TIMING_TRP;
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/* TRCD */
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SDRAM_Timing.RCDDelay = MICROPY_HW_SDRAM_TIMING_TRCD;
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hsdram.Init.SDBank = FMC_SDRAM_BANK1;
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hsdram.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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hsdram.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_10;
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hsdram.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_8;
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hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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hsdram.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
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hsdram.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3;
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hsdram.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
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hsdram.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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#define _FMC_INIT(x, n) x ## _ ## n
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#define FMC_INIT(x, n) _FMC_INIT(x, n)
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hsdram.Init.SDBank = FMC_SDRAM_BANK;
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hsdram.Init.ColumnBitsNumber = FMC_INIT(FMC_SDRAM_COLUMN_BITS_NUM, MICROPY_HW_SDRAM_COLUMN_BITS_NUM);
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hsdram.Init.RowBitsNumber = FMC_INIT(FMC_SDRAM_ROW_BITS_NUM, MICROPY_HW_SDRAM_ROW_BITS_NUM);
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hsdram.Init.MemoryDataWidth = FMC_INIT(FMC_SDRAM_MEM_BUS_WIDTH, MICROPY_HW_SDRAM_MEM_BUS_WIDTH);
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hsdram.Init.InternalBankNumber = FMC_INIT(FMC_SDRAM_INTERN_BANKS_NUM, MICROPY_HW_SDRAM_INTERN_BANKS_NUM);
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hsdram.Init.CASLatency = FMC_INIT(FMC_SDRAM_CAS_LATENCY, MICROPY_HW_SDRAM_CAS_LATENCY);
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hsdram.Init.SDClockPeriod = FMC_INIT(FMC_SDRAM_CLOCK_PERIOD, MICROPY_HW_SDRAM_CLOCK_PERIOD);
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hsdram.Init.ReadPipeDelay = FMC_INIT(FMC_SDRAM_RPIPE_DELAY, MICROPY_HW_SDRAM_RPIPE_DELAY);
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hsdram.Init.ReadBurst = (MICROPY_HW_SDRAM_RBURST) ? FMC_SDRAM_RBURST_ENABLE : FMC_SDRAM_RBURST_DISABLE;
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hsdram.Init.WriteProtection = (MICROPY_HW_SDRAM_WRITE_PROTECTION) ? FMC_SDRAM_WRITE_PROTECTION_ENABLE : FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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/* Initialize the SDRAM controller */
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if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK) {
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@ -75,6 +142,14 @@ bool sdram_init()
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return true;
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}
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void *sdram_start(void) {
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return (void*)SDRAM_START_ADDRESS;
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}
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void *sdram_end(void) {
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return (void*)(SDRAM_START_ADDRESS + MICROPY_HW_SDRAM_SIZE);
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}
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static void sdram_init_seq(SDRAM_HandleTypeDef
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*hsdram, FMC_SDRAM_CommandTypeDef *command)
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{
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@ -83,7 +158,7 @@ static void sdram_init_seq(SDRAM_HandleTypeDef
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/* Step 3: Configure a clock configuration enable command */
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command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = 0;
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@ -95,7 +170,7 @@ static void sdram_init_seq(SDRAM_HandleTypeDef
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/* Step 5: Configure a PALL (precharge all) command */
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command->CommandMode = FMC_SDRAM_CMD_PALL;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = 0;
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@ -104,7 +179,7 @@ static void sdram_init_seq(SDRAM_HandleTypeDef
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/* Step 6 : Configure a Auto-Refresh command */
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command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK;
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command->AutoRefreshNumber = 4;
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command->ModeRegisterDefinition = 0;
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@ -114,70 +189,77 @@ static void sdram_init_seq(SDRAM_HandleTypeDef
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/* Step 7: Program the external memory mode register */
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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FMC_INIT(SDRAM_MODEREG_CAS_LATENCY, MICROPY_HW_SDRAM_CAS_LATENCY) |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 8: Set the refresh rate counter */
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/* (15.62 us x Freq) - 20 */
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/* Set the device refresh counter */
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/* Step 8: Set the refresh rate counter
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RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc
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RefreshCycles = 7.8125 us * 90 MHz = 703
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According to the formula on p.1665 of the reference manual,
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we also need to subtract 20 from the value, so the target
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refresh rate is 703 - 20 = 683.
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*/
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||||
#define REFRESH_COUNT (MICROPY_HW_SDRAM_REFRESH_RATE * 90000 / 8192 - 20)
|
||||
HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
|
||||
}
|
||||
|
||||
bool __attribute__((optimize("O0"))) sdram_test(bool fast) {
|
||||
uint8_t const pattern = 0xaa;
|
||||
uint8_t const antipattern = 0x55;
|
||||
uint8_t *const mem_base = (uint8_t*)sdram_start();
|
||||
|
||||
bool DISABLE_OPT sdram_test()
|
||||
{
|
||||
uint8_t pattern = 0xAA;
|
||||
uint8_t antipattern = 0x55;
|
||||
uint32_t mem_size = (16*1024*1024);
|
||||
uint8_t * const mem_base = (uint8_t*)0xC0000000;
|
||||
|
||||
printf("sdram test...\n");
|
||||
/* test data bus */
|
||||
for (uint8_t i=1; i; i<<=1) {
|
||||
for (uint8_t i = 1; i; i <<= 1) {
|
||||
*mem_base = i;
|
||||
if (*mem_base != i) {
|
||||
printf("data bus lines test failed! data (%d)\n", i);
|
||||
BREAK();
|
||||
__asm__ volatile ("BKPT");
|
||||
}
|
||||
}
|
||||
|
||||
/* test address bus */
|
||||
/* Check individual address lines */
|
||||
for (uint32_t i=1; i<mem_size; i<<=1) {
|
||||
for (uint32_t i = 1; i < MICROPY_HW_SDRAM_SIZE; i <<= 1) {
|
||||
mem_base[i] = pattern;
|
||||
if (mem_base[i] != pattern) {
|
||||
printf("address bus lines test failed! address (%p)\n", &mem_base[i]);
|
||||
BREAK();
|
||||
__asm__ volatile ("BKPT");
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for aliasing (overlaping addresses) */
|
||||
mem_base[0] = antipattern;
|
||||
for (uint32_t i=1; i<mem_size; i<<=1) {
|
||||
for (uint32_t i = 1; i < MICROPY_HW_SDRAM_SIZE; i <<= 1) {
|
||||
if (mem_base[i] != pattern) {
|
||||
printf("address bus overlap %p\n", &mem_base[i]);
|
||||
BREAK();
|
||||
__asm__ volatile ("BKPT");
|
||||
}
|
||||
}
|
||||
|
||||
/* test all ram cells */
|
||||
for (uint32_t i=0; i<mem_size; i++) {
|
||||
mem_base[i] = pattern;
|
||||
if (mem_base[i] != pattern) {
|
||||
printf("address bus test failed! address (%p)\n", &mem_base[i]);
|
||||
BREAK();
|
||||
if (!fast) {
|
||||
for (uint32_t i = 0; i < MICROPY_HW_SDRAM_SIZE; ++i) {
|
||||
mem_base[i] = pattern;
|
||||
if (mem_base[i] != pattern) {
|
||||
printf("address bus test failed! address (%p)\n", &mem_base[i]);
|
||||
__asm__ volatile ("BKPT");
|
||||
}
|
||||
}
|
||||
} else {
|
||||
memset(mem_base, pattern, MICROPY_HW_SDRAM_SIZE);
|
||||
}
|
||||
|
||||
printf("sdram test passed\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
#endif // FMC_SDRAM_BANK
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@
|
|||
*/
|
||||
#ifndef __SDRAM_H__
|
||||
#define __SDRAM_H__
|
||||
bool sdram_init();
|
||||
bool sdram_test();
|
||||
bool sdram_init(void);
|
||||
void *sdram_start(void);
|
||||
void *sdram_end(void);
|
||||
bool sdram_test(bool fast);
|
||||
#endif // __SDRAM_H__
|
||||
|
|
|
|||
Loading…
Reference in New Issue