2005-04-16 16:20:36 -06:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1998, 1999, 2000 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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2013-03-25 12:40:49 -06:00
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* Copyright (C) 2007 by Maciej W. Rozycki
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* Copyright (C) 2011, 2012 MIPS Technologies, Inc.
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2005-04-16 16:20:36 -06:00
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*/
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#include <asm/asm.h>
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2005-09-09 14:32:31 -06:00
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#include <asm/asm-offsets.h>
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2016-11-07 04:14:15 -07:00
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#include <asm/export.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/regdef.h>
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2006-12-17 08:07:40 -07:00
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#if LONGSIZE == 4
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#define LONG_S_L swl
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#define LONG_S_R swr
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#else
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#define LONG_S_L sdl
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#define LONG_S_R sdr
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#endif
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2013-03-25 12:40:49 -06:00
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#ifdef CONFIG_CPU_MICROMIPS
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#define STORSIZE (LONGSIZE * 2)
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#define STORMASK (STORSIZE - 1)
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#define FILL64RG t8
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#define FILLPTRG t7
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#undef LONG_S
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#define LONG_S LONG_SP
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#else
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#define STORSIZE LONGSIZE
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#define STORMASK LONGMASK
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#define FILL64RG a1
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#define FILLPTRG t0
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#endif
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2014-01-03 02:23:16 -07:00
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#define LEGACY_MODE 1
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#define EVA_MODE 2
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2014-01-03 03:11:45 -07:00
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/*
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* No need to protect it with EVA #ifdefery. The generated block of code
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* will never be assembled if EVA is not enabled.
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*/
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#define __EVAFY(insn, reg, addr) __BUILD_EVA_INSN(insn##e, reg, addr)
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#define ___BUILD_EVA_INSN(insn, reg, addr) __EVAFY(insn, reg, addr)
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2005-04-16 16:20:36 -06:00
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#define EX(insn,reg,addr,handler) \
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2014-01-03 03:11:45 -07:00
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.if \mode == LEGACY_MODE; \
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9: insn reg, addr; \
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.else; \
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9: ___BUILD_EVA_INSN(insn, reg, addr); \
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.endif; \
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2013-01-22 04:59:30 -07:00
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.section __ex_table,"a"; \
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PTR 9b, handler; \
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2005-04-16 16:20:36 -06:00
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.previous
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2014-01-03 03:11:45 -07:00
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.macro f_fill64 dst, offset, val, fixup, mode
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2013-03-25 12:40:49 -06:00
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EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup)
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#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS))
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EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup)
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#endif
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#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
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EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
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2006-12-17 08:07:40 -07:00
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#endif
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2005-04-16 16:20:36 -06:00
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.endm
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.align 5
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2014-01-03 02:23:16 -07:00
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/*
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* Macro to generate the __bzero{,_user} symbol
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* Arguments:
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* mode: LEGACY_MODE or EVA_MODE
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*/
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.macro __BUILD_BZERO mode
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/* Initialize __memset if this is the first time we call this macro */
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.ifnotdef __memset
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.set __memset, 1
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.hidden __memset /* Make sure it does not leak */
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.endif
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2005-04-16 16:20:36 -06:00
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2013-03-25 12:40:49 -06:00
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sltiu t0, a2, STORSIZE /* very small region? */
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2018-10-02 05:50:16 -06:00
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.set noreorder
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2014-01-03 02:23:16 -07:00
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bnez t0, .Lsmall_memset\@
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2018-04-17 09:40:02 -06:00
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andi t0, a0, STORMASK /* aligned? */
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2018-10-02 05:50:16 -06:00
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.set reorder
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2005-04-16 16:20:36 -06:00
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2013-03-25 12:40:49 -06:00
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#ifdef CONFIG_CPU_MICROMIPS
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move t8, a1 /* used by 'swp' instruction */
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move t9, a1
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#endif
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2018-10-02 05:50:16 -06:00
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.set noreorder
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2007-10-23 05:43:25 -06:00
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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2005-04-16 16:20:36 -06:00
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beqz t0, 1f
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2018-04-17 09:40:02 -06:00
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PTR_SUBU t0, STORSIZE /* alignment in bytes */
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2007-10-23 05:43:25 -06:00
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#else
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.set noat
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2013-03-25 12:40:49 -06:00
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li AT, STORSIZE
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2007-10-23 05:43:25 -06:00
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beqz t0, 1f
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2018-04-17 09:40:02 -06:00
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PTR_SUBU t0, AT /* alignment in bytes */
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2007-10-23 05:43:25 -06:00
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.set at
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#endif
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2018-10-02 05:50:16 -06:00
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.set reorder
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2005-04-16 16:20:36 -06:00
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MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
CONFIG_CPU_HAS_LOAD_STORE_LR.
This variable indicates that the CPU supports these instructions.
Then, the patch does the following:
- Carefully selects this option on all CPUs except MIPSR6.
- Switches all the special cases to test for the new variable,
and inverts the logic:
'#ifndef CONFIG_CPU_MIPSR6' turns into
'#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
and vice-versa.
Also, when this variable is NOT selected (e.g. MIPSR6),
CONFIG_GENERIC_CSUM will default to 'y', to compile generic
C checksum code (instead of special assembly code that uses the
unsupported instructions).
This commit should not affect any existing CPU, and is required
for future Lexra CPU support, that misses these instructions too.
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20808/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
2018-09-26 05:16:15 -06:00
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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2007-11-25 03:47:56 -07:00
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R10KCBARRIER(0(ra))
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2005-04-16 16:20:36 -06:00
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#ifdef __MIPSEB__
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2014-01-03 02:23:16 -07:00
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EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
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2014-11-19 01:58:10 -07:00
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#else
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2014-01-03 02:23:16 -07:00
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EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
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2005-04-16 16:20:36 -06:00
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#endif
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PTR_SUBU a0, t0 /* long align ptr */
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PTR_ADDU a2, t0 /* correct size */
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MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
CONFIG_CPU_HAS_LOAD_STORE_LR.
This variable indicates that the CPU supports these instructions.
Then, the patch does the following:
- Carefully selects this option on all CPUs except MIPSR6.
- Switches all the special cases to test for the new variable,
and inverts the logic:
'#ifndef CONFIG_CPU_MIPSR6' turns into
'#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
and vice-versa.
Also, when this variable is NOT selected (e.g. MIPSR6),
CONFIG_GENERIC_CSUM will default to 'y', to compile generic
C checksum code (instead of special assembly code that uses the
unsupported instructions).
This commit should not affect any existing CPU, and is required
for future Lexra CPU support, that misses these instructions too.
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20808/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
2018-09-26 05:16:15 -06:00
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#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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2014-11-18 02:04:34 -07:00
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#define STORE_BYTE(N) \
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EX(sb, a1, N(a0), .Lbyte_fixup\@); \
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2018-10-02 05:50:16 -06:00
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.set noreorder; \
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2014-11-18 02:04:34 -07:00
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beqz t0, 0f; \
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2018-10-02 05:50:16 -06:00
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PTR_ADDU t0, 1; \
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.set reorder;
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2014-11-18 02:04:34 -07:00
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PTR_ADDU a2, t0 /* correct size */
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PTR_ADDU t0, 1
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STORE_BYTE(0)
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STORE_BYTE(1)
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#if LONGSIZE == 4
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EX(sb, a1, 2(a0), .Lbyte_fixup\@)
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#else
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STORE_BYTE(2)
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STORE_BYTE(3)
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STORE_BYTE(4)
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STORE_BYTE(5)
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EX(sb, a1, 6(a0), .Lbyte_fixup\@)
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#endif
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0:
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ori a0, STORMASK
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xori a0, STORMASK
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PTR_ADDIU a0, STORSIZE
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MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
CONFIG_CPU_HAS_LOAD_STORE_LR.
This variable indicates that the CPU supports these instructions.
Then, the patch does the following:
- Carefully selects this option on all CPUs except MIPSR6.
- Switches all the special cases to test for the new variable,
and inverts the logic:
'#ifndef CONFIG_CPU_MIPSR6' turns into
'#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
and vice-versa.
Also, when this variable is NOT selected (e.g. MIPSR6),
CONFIG_GENERIC_CSUM will default to 'y', to compile generic
C checksum code (instead of special assembly code that uses the
unsupported instructions).
This commit should not affect any existing CPU, and is required
for future Lexra CPU support, that misses these instructions too.
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20808/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
2018-09-26 05:16:15 -06:00
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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2005-04-16 16:20:36 -06:00
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1: ori t1, a2, 0x3f /* # of full blocks */
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xori t1, 0x3f
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2018-10-02 05:50:16 -06:00
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andi t0, a2, 0x40-STORSIZE
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2014-01-03 02:23:16 -07:00
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beqz t1, .Lmemset_partial\@ /* no block to fill */
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2005-04-16 16:20:36 -06:00
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PTR_ADDU t1, a0 /* end address */
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1: PTR_ADDIU a0, 64
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2007-11-25 03:47:56 -07:00
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R10KCBARRIER(0(ra))
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2014-01-03 03:11:45 -07:00
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f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
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2005-04-16 16:20:36 -06:00
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bne t1, a0, 1b
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2014-01-03 02:23:16 -07:00
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.Lmemset_partial\@:
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2007-11-25 03:47:56 -07:00
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R10KCBARRIER(0(ra))
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2005-04-16 16:20:36 -06:00
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PTR_LA t1, 2f /* where to start */
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2013-03-25 12:40:49 -06:00
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#ifdef CONFIG_CPU_MICROMIPS
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LONG_SRL t7, t0, 1
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#endif
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2006-12-17 08:07:40 -07:00
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#if LONGSIZE == 4
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2013-03-25 12:40:49 -06:00
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PTR_SUBU t1, FILLPTRG
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2006-12-17 08:07:40 -07:00
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#else
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.set noat
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2013-03-25 12:40:49 -06:00
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LONG_SRL AT, FILLPTRG, 1
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2006-12-17 08:07:40 -07:00
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PTR_SUBU t1, AT
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2007-10-23 05:43:25 -06:00
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.set at
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2006-12-17 08:07:40 -07:00
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#endif
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2018-10-02 05:50:16 -06:00
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PTR_ADDU a0, t0 /* dest ptr */
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2005-04-16 16:20:36 -06:00
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jr t1
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2014-01-03 02:23:16 -07:00
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/* ... but first do longs ... */
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2014-01-03 03:11:45 -07:00
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f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
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2018-10-02 05:50:16 -06:00
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2: andi a2, STORMASK /* At most one long to go */
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2005-04-16 16:20:36 -06:00
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2018-10-02 05:50:16 -06:00
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.set noreorder
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2005-04-16 16:20:36 -06:00
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beqz a2, 1f
|
MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
CONFIG_CPU_HAS_LOAD_STORE_LR.
This variable indicates that the CPU supports these instructions.
Then, the patch does the following:
- Carefully selects this option on all CPUs except MIPSR6.
- Switches all the special cases to test for the new variable,
and inverts the logic:
'#ifndef CONFIG_CPU_MIPSR6' turns into
'#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
and vice-versa.
Also, when this variable is NOT selected (e.g. MIPSR6),
CONFIG_GENERIC_CSUM will default to 'y', to compile generic
C checksum code (instead of special assembly code that uses the
unsupported instructions).
This commit should not affect any existing CPU, and is required
for future Lexra CPU support, that misses these instructions too.
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20808/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
2018-09-26 05:16:15 -06:00
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|
#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
|
2018-04-17 09:40:02 -06:00
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PTR_ADDU a0, a2 /* What's left */
|
2018-10-02 05:50:16 -06:00
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.set reorder
|
2007-11-25 03:47:56 -07:00
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R10KCBARRIER(0(ra))
|
2005-04-16 16:20:36 -06:00
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#ifdef __MIPSEB__
|
2014-01-03 02:23:16 -07:00
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|
|
EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
|
2014-11-19 01:58:10 -07:00
|
|
|
#else
|
2014-01-03 02:23:16 -07:00
|
|
|
EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
|
2005-04-16 16:20:36 -06:00
|
|
|
#endif
|
2014-11-18 02:04:34 -07:00
|
|
|
#else
|
2018-04-17 09:40:02 -06:00
|
|
|
PTR_SUBU t0, $0, a2
|
2018-10-02 05:50:16 -06:00
|
|
|
.set reorder
|
MIPS: memset.S: Fix byte_fixup for MIPSr6
The __clear_user function is defined to return the number of bytes that
could not be cleared. From the underlying memset / bzero implementation
this means setting register a2 to that number on return. Currently if a
page fault is triggered within the MIPSr6 version of setting of initial
unaligned bytes, the value loaded into a2 on return is meaningless.
During the MIPSr6 version of the initial unaligned bytes block, register
a2 contains the number of bytes to be set beyond the initial unaligned
bytes. The t0 register is initally set to the number of unaligned bytes
- STORSIZE, effectively a negative version of the number of unaligned
bytes. This is then incremented before each byte is saved.
The label .Lbyte_fixup\@ is jumped to on page fault. Currently the value
in a2 is incorrectly replaced by 0 - t0 + 1, effectively the number of
unaligned bytes remaining. This leads to the failures being reported by
the following test code:
static int __init test_clear_user(void)
{
int j, k;
pr_info("\n\n\nTesting clear_user\n");
for (j = 0; j < 512; j++) {
if ((k = clear_user(NULL+3, j)) != j) {
pr_err("clear_user (NULL %d) returned %d\n", j, k);
}
}
return 0;
}
late_initcall(test_clear_user);
Which reports:
[ 3.965439] Testing clear_user
[ 3.973169] clear_user (NULL 8) returned 6
[ 3.976782] clear_user (NULL 9) returned 6
[ 3.980390] clear_user (NULL 10) returned 6
[ 3.984052] clear_user (NULL 11) returned 6
[ 3.987524] clear_user (NULL 12) returned 6
Fix this by subtracting t0 from a2 (rather than $0), effectivey giving:
unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1
a2 = a2 - t0 + 1
This fixes the value returned from __clear user when the number of bytes
to set is > LONGSIZE and the address is invalid and unaligned.
Unfortunately, this breaks the fixup handling for unaligned bytes after
the final long, where register a2 still contains the number of bytes
remaining to be set and the t0 register is to 0 - the number of
unaligned bytes remaining.
Because t0 is now is now subtracted from a2 rather than 0, the number of
bytes unset is reported incorrectly:
static int __init test_clear_user(void)
{
char *test;
int j, k;
pr_info("\n\n\nTesting clear_user\n");
test = vmalloc(PAGE_SIZE);
for (j = 256; j < 512; j++) {
if ((k = clear_user(test + PAGE_SIZE - 254, j)) != j - 254) {
pr_err("clear_user (%px %d) returned %d\n",
test + PAGE_SIZE - 254, j, k);
}
}
return 0;
}
late_initcall(test_clear_user);
[ 3.976775] clear_user (c00000000000df02 256) returned 4
[ 3.981957] clear_user (c00000000000df02 257) returned 6
[ 3.986425] clear_user (c00000000000df02 258) returned 8
[ 3.990850] clear_user (c00000000000df02 259) returned 10
[ 3.995332] clear_user (c00000000000df02 260) returned 12
[ 3.999815] clear_user (c00000000000df02 261) returned 14
Fix this by ensuring that a2 is set to 0 during the set of final
unaligned bytes.
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support")
Patchwork: https://patchwork.linux-mips.org/patch/19338/
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org # v4.0+
2018-05-23 07:39:58 -06:00
|
|
|
move a2, zero /* No remaining longs */
|
2014-11-18 02:04:34 -07:00
|
|
|
PTR_ADDIU t0, 1
|
|
|
|
|
STORE_BYTE(0)
|
|
|
|
|
STORE_BYTE(1)
|
|
|
|
|
#if LONGSIZE == 4
|
|
|
|
|
EX(sb, a1, 2(a0), .Lbyte_fixup\@)
|
|
|
|
|
#else
|
|
|
|
|
STORE_BYTE(2)
|
|
|
|
|
STORE_BYTE(3)
|
|
|
|
|
STORE_BYTE(4)
|
|
|
|
|
STORE_BYTE(5)
|
|
|
|
|
EX(sb, a1, 6(a0), .Lbyte_fixup\@)
|
|
|
|
|
#endif
|
|
|
|
|
0:
|
|
|
|
|
#endif
|
2018-10-02 05:50:16 -06:00
|
|
|
1: move a2, zero
|
|
|
|
|
jr ra
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2014-01-03 02:23:16 -07:00
|
|
|
.Lsmall_memset\@:
|
2018-10-02 05:50:16 -06:00
|
|
|
PTR_ADDU t1, a0, a2
|
2005-04-16 16:20:36 -06:00
|
|
|
beqz a2, 2f
|
|
|
|
|
|
|
|
|
|
1: PTR_ADDIU a0, 1 /* fill bytewise */
|
2007-11-25 03:47:56 -07:00
|
|
|
R10KCBARRIER(0(ra))
|
2018-10-02 05:50:16 -06:00
|
|
|
.set noreorder
|
2005-04-16 16:20:36 -06:00
|
|
|
bne t1, a0, 1b
|
2018-03-29 03:28:23 -06:00
|
|
|
EX(sb, a1, -1(a0), .Lsmall_fixup\@)
|
2018-10-02 05:50:16 -06:00
|
|
|
.set reorder
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2018-10-02 05:50:16 -06:00
|
|
|
2: move a2, zero
|
|
|
|
|
jr ra /* done */
|
2014-01-03 02:23:16 -07:00
|
|
|
.if __memset == 1
|
2005-04-16 16:20:36 -06:00
|
|
|
END(memset)
|
2014-01-03 02:23:16 -07:00
|
|
|
.set __memset, 0
|
|
|
|
|
.hidden __memset
|
|
|
|
|
.endif
|
2005-04-16 16:20:36 -06:00
|
|
|
|
MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
CONFIG_CPU_HAS_LOAD_STORE_LR.
This variable indicates that the CPU supports these instructions.
Then, the patch does the following:
- Carefully selects this option on all CPUs except MIPSR6.
- Switches all the special cases to test for the new variable,
and inverts the logic:
'#ifndef CONFIG_CPU_MIPSR6' turns into
'#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
and vice-versa.
Also, when this variable is NOT selected (e.g. MIPSR6),
CONFIG_GENERIC_CSUM will default to 'y', to compile generic
C checksum code (instead of special assembly code that uses the
unsupported instructions).
This commit should not affect any existing CPU, and is required
for future Lexra CPU support, that misses these instructions too.
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20808/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
2018-09-26 05:16:15 -06:00
|
|
|
#ifndef CONFIG_CPU_HAS_LOAD_STORE_LR
|
2014-11-18 02:04:34 -07:00
|
|
|
.Lbyte_fixup\@:
|
2018-05-23 07:39:59 -06:00
|
|
|
/*
|
|
|
|
|
* unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1
|
|
|
|
|
* a2 = a2 - t0 + 1
|
|
|
|
|
*/
|
MIPS: memset.S: Fix byte_fixup for MIPSr6
The __clear_user function is defined to return the number of bytes that
could not be cleared. From the underlying memset / bzero implementation
this means setting register a2 to that number on return. Currently if a
page fault is triggered within the MIPSr6 version of setting of initial
unaligned bytes, the value loaded into a2 on return is meaningless.
During the MIPSr6 version of the initial unaligned bytes block, register
a2 contains the number of bytes to be set beyond the initial unaligned
bytes. The t0 register is initally set to the number of unaligned bytes
- STORSIZE, effectively a negative version of the number of unaligned
bytes. This is then incremented before each byte is saved.
The label .Lbyte_fixup\@ is jumped to on page fault. Currently the value
in a2 is incorrectly replaced by 0 - t0 + 1, effectively the number of
unaligned bytes remaining. This leads to the failures being reported by
the following test code:
static int __init test_clear_user(void)
{
int j, k;
pr_info("\n\n\nTesting clear_user\n");
for (j = 0; j < 512; j++) {
if ((k = clear_user(NULL+3, j)) != j) {
pr_err("clear_user (NULL %d) returned %d\n", j, k);
}
}
return 0;
}
late_initcall(test_clear_user);
Which reports:
[ 3.965439] Testing clear_user
[ 3.973169] clear_user (NULL 8) returned 6
[ 3.976782] clear_user (NULL 9) returned 6
[ 3.980390] clear_user (NULL 10) returned 6
[ 3.984052] clear_user (NULL 11) returned 6
[ 3.987524] clear_user (NULL 12) returned 6
Fix this by subtracting t0 from a2 (rather than $0), effectivey giving:
unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1
a2 = a2 - t0 + 1
This fixes the value returned from __clear user when the number of bytes
to set is > LONGSIZE and the address is invalid and unaligned.
Unfortunately, this breaks the fixup handling for unaligned bytes after
the final long, where register a2 still contains the number of bytes
remaining to be set and the t0 register is to 0 - the number of
unaligned bytes remaining.
Because t0 is now is now subtracted from a2 rather than 0, the number of
bytes unset is reported incorrectly:
static int __init test_clear_user(void)
{
char *test;
int j, k;
pr_info("\n\n\nTesting clear_user\n");
test = vmalloc(PAGE_SIZE);
for (j = 256; j < 512; j++) {
if ((k = clear_user(test + PAGE_SIZE - 254, j)) != j - 254) {
pr_err("clear_user (%px %d) returned %d\n",
test + PAGE_SIZE - 254, j, k);
}
}
return 0;
}
late_initcall(test_clear_user);
[ 3.976775] clear_user (c00000000000df02 256) returned 4
[ 3.981957] clear_user (c00000000000df02 257) returned 6
[ 3.986425] clear_user (c00000000000df02 258) returned 8
[ 3.990850] clear_user (c00000000000df02 259) returned 10
[ 3.995332] clear_user (c00000000000df02 260) returned 12
[ 3.999815] clear_user (c00000000000df02 261) returned 14
Fix this by ensuring that a2 is set to 0 during the set of final
unaligned bytes.
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support")
Patchwork: https://patchwork.linux-mips.org/patch/19338/
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org # v4.0+
2018-05-23 07:39:58 -06:00
|
|
|
PTR_SUBU a2, t0
|
2018-10-02 05:50:16 -06:00
|
|
|
PTR_ADDIU a2, 1
|
2014-11-18 02:04:34 -07:00
|
|
|
jr ra
|
MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
CONFIG_CPU_HAS_LOAD_STORE_LR.
This variable indicates that the CPU supports these instructions.
Then, the patch does the following:
- Carefully selects this option on all CPUs except MIPSR6.
- Switches all the special cases to test for the new variable,
and inverts the logic:
'#ifndef CONFIG_CPU_MIPSR6' turns into
'#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
and vice-versa.
Also, when this variable is NOT selected (e.g. MIPSR6),
CONFIG_GENERIC_CSUM will default to 'y', to compile generic
C checksum code (instead of special assembly code that uses the
unsupported instructions).
This commit should not affect any existing CPU, and is required
for future Lexra CPU support, that misses these instructions too.
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20808/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
2018-09-26 05:16:15 -06:00
|
|
|
#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
|
2014-11-18 02:04:34 -07:00
|
|
|
|
2014-01-03 02:23:16 -07:00
|
|
|
.Lfirst_fixup\@:
|
2018-05-23 07:39:59 -06:00
|
|
|
/* unset_bytes already in a2 */
|
2005-04-16 16:20:36 -06:00
|
|
|
jr ra
|
|
|
|
|
|
2014-01-03 02:23:16 -07:00
|
|
|
.Lfwd_fixup\@:
|
2018-05-23 07:39:59 -06:00
|
|
|
/*
|
|
|
|
|
* unset_bytes = partial_start_addr + #bytes - fault_addr
|
|
|
|
|
* a2 = t1 + (a2 & 3f) - $28->task->BUADDR
|
|
|
|
|
*/
|
2005-04-16 16:20:36 -06:00
|
|
|
PTR_L t0, TI_TASK($28)
|
|
|
|
|
andi a2, 0x3f
|
2010-11-10 06:48:15 -07:00
|
|
|
LONG_L t0, THREAD_BUADDR(t0)
|
2005-04-16 16:20:36 -06:00
|
|
|
LONG_ADDU a2, t1
|
2018-10-02 05:50:16 -06:00
|
|
|
LONG_SUBU a2, t0
|
2005-04-16 16:20:36 -06:00
|
|
|
jr ra
|
|
|
|
|
|
2014-01-03 02:23:16 -07:00
|
|
|
.Lpartial_fixup\@:
|
2018-05-23 07:39:59 -06:00
|
|
|
/*
|
|
|
|
|
* unset_bytes = partial_end_addr + #bytes - fault_addr
|
|
|
|
|
* a2 = a0 + (a2 & STORMASK) - $28->task->BUADDR
|
|
|
|
|
*/
|
2005-04-16 16:20:36 -06:00
|
|
|
PTR_L t0, TI_TASK($28)
|
2013-03-25 12:40:49 -06:00
|
|
|
andi a2, STORMASK
|
2010-11-10 06:48:15 -07:00
|
|
|
LONG_L t0, THREAD_BUADDR(t0)
|
MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup
The __clear_user function is defined to return the number of bytes that
could not be cleared. From the underlying memset / bzero implementation
this means setting register a2 to that number on return. Currently if a
page fault is triggered within the memset_partial block, the value
loaded into a2 on return is meaningless.
The label .Lpartial_fixup\@ is jumped to on page fault. In order to work
out how many bytes failed to copy, the exception handler should find how
many bytes left in the partial block (andi a2, STORMASK), add that to
the partial block end address (a2), and subtract the faulting address to
get the remainder. Currently it incorrectly subtracts the partial block
start address (t1), which has additionally been clobbered to generate a
jump target in memset_partial. Fix this by adding the block end address
instead.
This issue was found with the following test code:
int j, k;
for (j = 0; j < 512; j++) {
if ((k = clear_user(NULL, j)) != j) {
pr_err("clear_user (NULL %d) returned %d\n", j, k);
}
}
Which now passes on Creator Ci40 (MIPS32) and Cavium Octeon II (MIPS64).
Suggested-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/19108/
Signed-off-by: James Hogan <jhogan@kernel.org>
2018-04-17 08:52:21 -06:00
|
|
|
LONG_ADDU a2, a0
|
2018-10-02 05:50:16 -06:00
|
|
|
LONG_SUBU a2, t0
|
2005-04-16 16:20:36 -06:00
|
|
|
jr ra
|
|
|
|
|
|
2014-01-03 02:23:16 -07:00
|
|
|
.Llast_fixup\@:
|
2018-05-23 07:39:59 -06:00
|
|
|
/* unset_bytes already in a2 */
|
2005-04-16 16:20:36 -06:00
|
|
|
jr ra
|
2014-01-03 02:23:16 -07:00
|
|
|
|
2018-03-29 03:28:23 -06:00
|
|
|
.Lsmall_fixup\@:
|
2018-05-23 07:39:59 -06:00
|
|
|
/*
|
|
|
|
|
* unset_bytes = end_addr - current_addr + 1
|
|
|
|
|
* a2 = t1 - a0 + 1
|
|
|
|
|
*/
|
2018-03-29 03:28:23 -06:00
|
|
|
PTR_SUBU a2, t1, a0
|
MIPS: memset: Fix CPU_DADDI_WORKAROUNDS `small_fixup' regression
Fix a commit 8a8158c85e1e ("MIPS: memset.S: EVA & fault support for
small_memset") regression and remove assembly warnings:
arch/mips/lib/memset.S: Assembler messages:
arch/mips/lib/memset.S:243: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
triggering with the CPU_DADDI_WORKAROUNDS option set and this code:
PTR_SUBU a2, t1, a0
jr ra
PTR_ADDIU a2, 1
This is because with that option in place the DADDIU instruction, which
the PTR_ADDIU CPP macro expands to, becomes a GAS macro, which in turn
expands to an LI/DADDU (or actually ADDIU/DADDU) sequence:
13c: 01a4302f dsubu a2,t1,a0
140: 03e00008 jr ra
144: 24010001 li at,1
148: 00c1302d daddu a2,a2,at
...
Correct this by switching off the `noreorder' assembly mode and letting
GAS schedule this jump's delay slot, as there is nothing special about
it that would require manual scheduling. With this change in place
correct code is produced:
13c: 01a4302f dsubu a2,t1,a0
140: 24010001 li at,1
144: 03e00008 jr ra
148: 00c1302d daddu a2,a2,at
...
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: 8a8158c85e1e ("MIPS: memset.S: EVA & fault support for small_memset")
Patchwork: https://patchwork.linux-mips.org/patch/20833/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: stable@vger.kernel.org # 4.17+
2018-10-02 05:50:11 -06:00
|
|
|
PTR_ADDIU a2, 1
|
2018-03-29 03:28:23 -06:00
|
|
|
jr ra
|
|
|
|
|
|
2014-01-03 02:23:16 -07:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* memset(void *s, int c, size_t n)
|
|
|
|
|
*
|
|
|
|
|
* a0: start of area to clear
|
|
|
|
|
* a1: char to fill with
|
|
|
|
|
* a2: size of area to clear
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
LEAF(memset)
|
2016-11-07 04:14:15 -07:00
|
|
|
EXPORT_SYMBOL(memset)
|
2018-10-02 05:50:16 -06:00
|
|
|
move v0, a0 /* result */
|
2014-01-03 02:23:16 -07:00
|
|
|
beqz a1, 1f
|
|
|
|
|
|
|
|
|
|
andi a1, 0xff /* spread fillword */
|
|
|
|
|
LONG_SLL t1, a1, 8
|
|
|
|
|
or a1, t1
|
|
|
|
|
LONG_SLL t1, a1, 16
|
|
|
|
|
#if LONGSIZE == 8
|
|
|
|
|
or a1, t1
|
|
|
|
|
LONG_SLL t1, a1, 32
|
|
|
|
|
#endif
|
|
|
|
|
or a1, t1
|
|
|
|
|
1:
|
2014-01-03 03:11:45 -07:00
|
|
|
#ifndef CONFIG_EVA
|
2014-01-03 02:23:16 -07:00
|
|
|
FEXPORT(__bzero)
|
2016-11-07 04:14:15 -07:00
|
|
|
EXPORT_SYMBOL(__bzero)
|
2015-08-05 09:41:39 -06:00
|
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#else
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FEXPORT(__bzero_kernel)
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2016-11-07 04:14:15 -07:00
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EXPORT_SYMBOL(__bzero_kernel)
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2014-01-03 03:11:45 -07:00
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#endif
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2014-01-03 02:23:16 -07:00
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__BUILD_BZERO LEGACY_MODE
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2014-01-03 03:11:45 -07:00
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#ifdef CONFIG_EVA
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LEAF(__bzero)
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2016-11-07 04:14:15 -07:00
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EXPORT_SYMBOL(__bzero)
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2014-01-03 03:11:45 -07:00
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__BUILD_BZERO EVA_MODE
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END(__bzero)
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#endif
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