enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/* Copyright 2017-2019 NXP */
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2020-07-19 16:03:35 -06:00
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#include <linux/mdio.h>
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
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#include <linux/module.h>
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2020-01-05 18:34:13 -07:00
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#include <linux/fsl/enetc_mdio.h>
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include "enetc_pf.h"
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#define ENETC_DRV_NAME_STR "ENETC PF driver"
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static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
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{
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u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
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u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
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*(u32 *)addr = upper;
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*(u16 *)(addr + 4) = lower;
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}
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static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
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const u8 *addr)
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{
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u32 upper = *(const u32 *)addr;
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u16 lower = *(const u16 *)(addr + 4);
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__raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
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__raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
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}
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static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
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{
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struct enetc_ndev_priv *priv = netdev_priv(ndev);
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struct sockaddr *saddr = addr;
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if (!is_valid_ether_addr(saddr->sa_data))
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return -EADDRNOTAVAIL;
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memcpy(ndev->dev_addr, saddr->sa_data, ndev->addr_len);
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enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
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return 0;
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}
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static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
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{
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u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
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val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
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enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
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}
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static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
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{
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pf->vlan_promisc_simap |= BIT(si_idx);
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enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
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}
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static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
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{
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pf->vlan_promisc_simap &= ~BIT(si_idx);
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enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
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}
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static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
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{
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u32 val = 0;
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if (vlan)
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val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
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enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
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}
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static int enetc_mac_addr_hash_idx(const u8 *addr)
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{
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u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
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u64 mask = 0;
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int res = 0;
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int i;
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for (i = 0; i < 8; i++)
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mask |= BIT_ULL(i * 6);
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for (i = 0; i < 6; i++)
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res |= (hweight64(fold & (mask << i)) & 0x1) << i;
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return res;
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}
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static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
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{
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filter->mac_addr_cnt = 0;
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bitmap_zero(filter->mac_hash_table,
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ENETC_MADDR_HASH_TBL_SZ);
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}
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static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
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const unsigned char *addr)
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{
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/* add exact match addr */
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ether_addr_copy(filter->mac_addr, addr);
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filter->mac_addr_cnt++;
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}
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static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
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const unsigned char *addr)
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{
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int idx = enetc_mac_addr_hash_idx(addr);
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/* add hash table entry */
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__set_bit(idx, filter->mac_hash_table);
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filter->mac_addr_cnt++;
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}
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static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
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{
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bool err = si->errata & ENETC_ERR_UCMCSWP;
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if (type == UC) {
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enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
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enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
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} else { /* MC */
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enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
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enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
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}
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}
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static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
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u32 *hash)
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{
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bool err = si->errata & ENETC_ERR_UCMCSWP;
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if (type == UC) {
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enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), *hash);
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enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), *(hash + 1));
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} else { /* MC */
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enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), *hash);
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enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), *(hash + 1));
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}
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}
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static void enetc_sync_mac_filters(struct enetc_pf *pf)
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{
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struct enetc_mac_filter *f = pf->mac_filter;
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struct enetc_si *si = pf->si;
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int i, pos;
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pos = EMETC_MAC_ADDR_FILT_RES;
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for (i = 0; i < MADDR_TYPE; i++, f++) {
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bool em = (f->mac_addr_cnt == 1) && (i == UC);
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bool clear = !f->mac_addr_cnt;
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if (clear) {
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if (i == UC)
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enetc_clear_mac_flt_entry(si, pos);
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enetc_clear_mac_ht_flt(si, 0, i);
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continue;
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}
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/* exact match filter */
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if (em) {
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int err;
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enetc_clear_mac_ht_flt(si, 0, UC);
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err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
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BIT(0));
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if (!err)
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continue;
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/* fallback to HT filtering */
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dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
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err);
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}
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/* hash table filter, clear EM filter for UC entries */
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if (i == UC)
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enetc_clear_mac_flt_entry(si, pos);
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enetc_set_mac_ht_flt(si, 0, i, (u32 *)f->mac_hash_table);
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}
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}
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static void enetc_pf_set_rx_mode(struct net_device *ndev)
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{
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struct enetc_ndev_priv *priv = netdev_priv(ndev);
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struct enetc_pf *pf = enetc_si_priv(priv->si);
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struct enetc_hw *hw = &priv->si->hw;
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bool uprom = false, mprom = false;
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struct enetc_mac_filter *filter;
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struct netdev_hw_addr *ha;
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u32 psipmr = 0;
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bool em;
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if (ndev->flags & IFF_PROMISC) {
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/* enable promisc mode for SI0 (PF) */
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psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
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uprom = true;
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mprom = true;
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} else if (ndev->flags & IFF_ALLMULTI) {
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/* enable multi cast promisc mode for SI0 (PF) */
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psipmr = ENETC_PSIPMR_SET_MP(0);
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mprom = true;
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}
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/* first 2 filter entries belong to PF */
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if (!uprom) {
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/* Update unicast filters */
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filter = &pf->mac_filter[UC];
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enetc_reset_mac_addr_filter(filter);
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em = (netdev_uc_count(ndev) == 1);
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netdev_for_each_uc_addr(ha, ndev) {
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if (em) {
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enetc_add_mac_addr_em_filter(filter, ha->addr);
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break;
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}
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enetc_add_mac_addr_ht_filter(filter, ha->addr);
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}
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}
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if (!mprom) {
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/* Update multicast filters */
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filter = &pf->mac_filter[MC];
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enetc_reset_mac_addr_filter(filter);
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netdev_for_each_mc_addr(ha, ndev) {
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if (!is_multicast_ether_addr(ha->addr))
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continue;
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enetc_add_mac_addr_ht_filter(filter, ha->addr);
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}
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}
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if (!uprom || !mprom)
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/* update PF entries */
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enetc_sync_mac_filters(pf);
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psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
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~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
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enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
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}
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static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
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u32 *hash)
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{
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enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), *hash);
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enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), *(hash + 1));
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}
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static int enetc_vid_hash_idx(unsigned int vid)
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{
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int res = 0;
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int i;
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for (i = 0; i < 6; i++)
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res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
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return res;
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}
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static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
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{
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int i;
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if (rehash) {
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bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
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for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
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int hidx = enetc_vid_hash_idx(i);
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__set_bit(hidx, pf->vlan_ht_filter);
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}
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}
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enetc_set_vlan_ht_filter(&pf->si->hw, 0, (u32 *)pf->vlan_ht_filter);
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}
|
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|
static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
|
|
|
|
{
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
int idx;
|
|
|
|
|
|
|
|
__set_bit(vid, pf->active_vlans);
|
|
|
|
|
|
|
|
idx = enetc_vid_hash_idx(vid);
|
|
|
|
if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
|
|
|
|
enetc_sync_vlan_ht_filter(pf, false);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
|
|
|
|
{
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
|
|
|
|
__clear_bit(vid, pf->active_vlans);
|
|
|
|
enetc_sync_vlan_ht_filter(pf, true);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_set_loopback(struct net_device *ndev, bool en)
|
|
|
|
{
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
struct enetc_hw *hw = &priv->si->hw;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
|
2021-03-01 04:18:16 -07:00
|
|
|
if (reg & ENETC_PM0_IFM_RG) {
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
/* RGMII mode */
|
|
|
|
reg = (reg & ~ENETC_PM0_IFM_RLP) |
|
|
|
|
(en ? ENETC_PM0_IFM_RLP : 0);
|
|
|
|
enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
|
|
|
|
} else {
|
|
|
|
/* assume SGMII mode */
|
|
|
|
reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
|
|
|
|
reg = (reg & ~ENETC_PM0_CMD_XGLP) |
|
|
|
|
(en ? ENETC_PM0_CMD_XGLP : 0);
|
|
|
|
reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
|
|
|
|
(en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
|
|
|
|
enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
|
|
|
|
enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
|
|
|
|
{
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
2019-01-22 06:29:56 -07:00
|
|
|
struct enetc_vf_state *vf_state;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
|
|
|
|
if (vf >= pf->total_vfs)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (!is_valid_ether_addr(mac))
|
|
|
|
return -EADDRNOTAVAIL;
|
|
|
|
|
2019-01-22 06:29:56 -07:00
|
|
|
vf_state = &pf->vf_state[vf];
|
|
|
|
vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
|
|
|
|
u8 qos, __be16 proto)
|
|
|
|
{
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
|
|
|
|
if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
if (vf >= pf->total_vfs)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (proto != htons(ETH_P_8021Q))
|
|
|
|
/* only C-tags supported for now */
|
|
|
|
return -EPROTONOSUPPORT;
|
|
|
|
|
|
|
|
enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
|
|
|
|
{
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
u32 cfgr;
|
|
|
|
|
|
|
|
if (vf >= pf->total_vfs)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
|
|
|
|
cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
|
|
|
|
enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_port_setup_primary_mac_address(struct enetc_si *si)
|
|
|
|
{
|
|
|
|
unsigned char mac_addr[MAX_ADDR_LEN];
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* check MAC addresses for PF and all VFs, if any is 0 set it ro rand */
|
|
|
|
for (i = 0; i < pf->total_vfs + 1; i++) {
|
|
|
|
enetc_pf_get_primary_mac_addr(hw, i, mac_addr);
|
|
|
|
if (!is_zero_ether_addr(mac_addr))
|
|
|
|
continue;
|
|
|
|
eth_random_addr(mac_addr);
|
|
|
|
dev_info(&si->pdev->dev, "no MAC address specified for SI%d, using %pM\n",
|
|
|
|
i, mac_addr);
|
|
|
|
enetc_pf_set_primary_mac_addr(hw, i, mac_addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-01-22 06:29:57 -07:00
|
|
|
static void enetc_port_assign_rfs_entries(struct enetc_si *si)
|
|
|
|
{
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
int num_entries, vf_entries, i;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* split RFS entries between functions */
|
|
|
|
val = enetc_port_rd(hw, ENETC_PRFSCAPR);
|
|
|
|
num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
|
|
|
|
vf_entries = num_entries / (pf->total_vfs + 1);
|
|
|
|
|
|
|
|
for (i = 0; i < pf->total_vfs; i++)
|
|
|
|
enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
|
|
|
|
enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
|
|
|
|
num_entries - vf_entries * pf->total_vfs);
|
|
|
|
|
|
|
|
/* enable RFS on port */
|
|
|
|
enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
|
|
|
|
}
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
static void enetc_port_si_configure(struct enetc_si *si)
|
|
|
|
{
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
int num_rings, i;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = enetc_port_rd(hw, ENETC_PCAPR0);
|
|
|
|
num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
|
|
|
|
|
|
|
|
val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
|
|
|
|
val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
|
|
|
|
|
|
|
|
if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
|
|
|
|
val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
|
|
|
|
val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
|
|
|
|
|
|
|
|
dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
|
|
|
|
num_rings, ENETC_PF_NUM_RINGS);
|
|
|
|
|
|
|
|
num_rings = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Add default one-time settings for SI0 (PF) */
|
|
|
|
val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
|
|
|
|
|
|
|
|
if (num_rings)
|
|
|
|
num_rings -= ENETC_PF_NUM_RINGS;
|
|
|
|
|
|
|
|
/* Configure the SIs for each available VF */
|
|
|
|
val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
|
|
|
|
val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
|
|
|
|
|
|
|
|
if (num_rings) {
|
|
|
|
num_rings /= pf->total_vfs;
|
|
|
|
val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
|
|
|
|
val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < pf->total_vfs; i++)
|
|
|
|
enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
|
|
|
|
|
|
|
|
/* Port level VLAN settings */
|
|
|
|
val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
|
|
|
|
enetc_port_wr(hw, ENETC_PVCLCTR, val);
|
|
|
|
/* use outer tag for VLAN filtering */
|
|
|
|
enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:20 -06:00
|
|
|
static void enetc_configure_port_mac(struct enetc_hw *hw)
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
{
|
|
|
|
enetc_port_wr(hw, ENETC_PM0_MAXFRM,
|
|
|
|
ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
|
|
|
|
enetc_port_wr(hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE);
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
|
2020-10-07 03:48:20 -06:00
|
|
|
ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
|
2020-10-07 03:48:20 -06:00
|
|
|
ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
|
2021-03-07 06:23:38 -07:00
|
|
|
|
|
|
|
/* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
|
|
|
|
* and may lead to RX lock-up under traffic. Set it to 1 instead,
|
|
|
|
* as recommended by the hardware team.
|
|
|
|
*/
|
|
|
|
enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
|
2020-10-07 03:48:20 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
|
|
|
|
{
|
2021-03-01 04:18:16 -07:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (phy_interface_mode_is_rgmii(phy_mode)) {
|
|
|
|
val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
|
|
|
|
val &= ~ENETC_PM0_IFM_EN_AUTO;
|
|
|
|
val &= ENETC_PM0_IFM_IFMODE_MASK;
|
|
|
|
val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
|
|
|
|
enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
|
|
|
|
}
|
2020-07-19 16:03:36 -06:00
|
|
|
|
2021-03-01 04:18:16 -07:00
|
|
|
if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
|
|
|
|
val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
|
|
|
|
enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
|
|
|
|
}
|
2020-10-07 03:48:23 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_mac_enable(struct enetc_hw *hw, bool en)
|
|
|
|
{
|
|
|
|
u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
|
2020-10-07 03:48:20 -06:00
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
|
|
|
|
val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
|
2020-10-07 03:48:20 -06:00
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
|
|
|
|
enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_configure_port_pmac(struct enetc_hw *hw)
|
|
|
|
{
|
|
|
|
u32 temp;
|
|
|
|
|
|
|
|
/* Set pMAC step lock */
|
|
|
|
temp = enetc_port_rd(hw, ENETC_PFPMR);
|
|
|
|
enetc_port_wr(hw, ENETC_PFPMR,
|
|
|
|
temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
|
|
|
|
|
|
|
|
temp = enetc_port_rd(hw, ENETC_MMCSR);
|
|
|
|
enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_configure_port(struct enetc_pf *pf)
|
|
|
|
{
|
2019-01-22 06:29:57 -07:00
|
|
|
u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
struct enetc_hw *hw = &pf->si->hw;
|
|
|
|
|
|
|
|
enetc_configure_port_pmac(hw);
|
|
|
|
|
2020-10-07 03:48:20 -06:00
|
|
|
enetc_configure_port_mac(hw);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
|
|
|
|
enetc_port_si_configure(pf->si);
|
|
|
|
|
2019-01-22 06:29:57 -07:00
|
|
|
/* set up hash key */
|
|
|
|
get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
|
|
|
|
enetc_set_rss_key(hw, hash_key);
|
|
|
|
|
|
|
|
/* split up RFS entries */
|
|
|
|
enetc_port_assign_rfs_entries(pf->si);
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
/* fix-up primary MAC addresses, if not set already */
|
|
|
|
enetc_port_setup_primary_mac_address(pf->si);
|
|
|
|
|
|
|
|
/* enforce VLAN promisc mode for all SIs */
|
|
|
|
pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
|
|
|
|
enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSIPMR, 0);
|
|
|
|
|
|
|
|
/* enable port */
|
|
|
|
enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
|
|
|
|
}
|
|
|
|
|
2019-01-22 06:29:56 -07:00
|
|
|
/* Messaging */
|
|
|
|
static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
|
|
|
|
int vf_id)
|
|
|
|
{
|
|
|
|
struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
|
|
|
|
struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
|
|
|
|
struct enetc_msg_cmd_set_primary_mac *cmd;
|
|
|
|
struct device *dev = &pf->si->pdev->dev;
|
|
|
|
u16 cmd_id;
|
|
|
|
char *addr;
|
|
|
|
|
|
|
|
cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
|
|
|
|
cmd_id = cmd->header.id;
|
|
|
|
if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
|
|
|
|
return ENETC_MSG_CMD_STATUS_FAIL;
|
|
|
|
|
|
|
|
addr = cmd->mac.sa_data;
|
|
|
|
if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
|
|
|
|
dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
|
|
|
|
vf_id);
|
|
|
|
else
|
|
|
|
enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
|
|
|
|
|
|
|
|
return ENETC_MSG_CMD_STATUS_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
|
|
|
|
{
|
|
|
|
struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
|
|
|
|
struct device *dev = &pf->si->pdev->dev;
|
|
|
|
struct enetc_msg_cmd_header *cmd_hdr;
|
|
|
|
u16 cmd_type;
|
|
|
|
|
|
|
|
*status = ENETC_MSG_CMD_STATUS_OK;
|
|
|
|
cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
|
|
|
|
cmd_type = cmd_hdr->type;
|
|
|
|
|
|
|
|
switch (cmd_type) {
|
|
|
|
case ENETC_MSG_CMD_MNG_MAC:
|
|
|
|
*status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
|
|
|
|
cmd_type);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
|
|
|
|
{
|
|
|
|
struct enetc_si *si = pci_get_drvdata(pdev);
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (!num_vfs) {
|
2019-01-22 06:29:56 -07:00
|
|
|
enetc_msg_psi_free(pf);
|
|
|
|
kfree(pf->vf_state);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
pf->num_vfs = 0;
|
|
|
|
pci_disable_sriov(pdev);
|
|
|
|
} else {
|
|
|
|
pf->num_vfs = num_vfs;
|
|
|
|
|
2019-01-22 06:29:56 -07:00
|
|
|
pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!pf->vf_state) {
|
|
|
|
pf->num_vfs = 0;
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = enetc_msg_psi_init(pf);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
|
|
|
|
goto err_msg_psi;
|
|
|
|
}
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
err = pci_enable_sriov(pdev, num_vfs);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
|
|
|
|
goto err_en_sriov;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return num_vfs;
|
|
|
|
|
|
|
|
err_en_sriov:
|
2019-01-22 06:29:56 -07:00
|
|
|
enetc_msg_psi_free(pf);
|
|
|
|
err_msg_psi:
|
|
|
|
kfree(pf->vf_state);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
pf->num_vfs = 0;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define enetc_sriov_configure(pdev, num_vfs) (void)0
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int enetc_pf_set_features(struct net_device *ndev,
|
|
|
|
netdev_features_t features)
|
|
|
|
{
|
|
|
|
netdev_features_t changed = ndev->features ^ features;
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
|
enetc: permit configuration of rx-vlan-filter with ethtool
Each ENETC station interface (SI) has a VLAN filter list and a port
flag (PSIPVMR) by which it can be put in "VLAN promiscuous" mode, which
enables the reception of VLAN-tagged traffic even if it is not in the
VLAN filtering list.
Currently the handling of this setting works like this: the port starts
off as VLAN promiscuous, then it switches to enabling VLAN filtering as
soon as the first VLAN is installed in its filter via
.ndo_vlan_rx_add_vid. In practice that does not work out very well,
because more often than not, the first VLAN to be installed is out of
the control of the user: the 8021q module, if loaded, adds its rule for
802.1p (VID 0) traffic upon bringing the interface up.
What the user is currently seeing in ethtool is this:
ethtool -k eno2
rx-vlan-filter: on [fixed]
which doesn't match the intention of the code, but the practical reality
of having the 8021q module install its VID which has the side-effect of
turning on VLAN filtering in this driver. All in all, a slightly
confusing experience.
So instead of letting this driver switch the VLAN filtering state by
itself, just wire it up with the rx-vlan-filter feature from ethtool,
and let it be user-configurable just through that knob, except for one
case, see below.
In promiscuous mode, it is more intuitive that all traffic is received,
including VLAN tagged traffic. It appears that it is necessary to set
the flag in PSIPVMR for that to be the case, so VLAN promiscuous mode is
also temporarily enabled. On exit from promiscuous mode, the setting
made by ethtool is restored.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-17 13:07:55 -06:00
|
|
|
if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
|
|
|
|
if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
|
|
|
|
enetc_disable_si_vlan_promisc(pf, 0);
|
|
|
|
else
|
|
|
|
enetc_enable_si_vlan_promisc(pf, 0);
|
|
|
|
}
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
if (changed & NETIF_F_LOOPBACK)
|
|
|
|
enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
|
|
|
|
|
2019-01-22 06:29:57 -07:00
|
|
|
return enetc_set_features(ndev, features);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct net_device_ops enetc_ndev_ops = {
|
|
|
|
.ndo_open = enetc_open,
|
|
|
|
.ndo_stop = enetc_close,
|
|
|
|
.ndo_start_xmit = enetc_xmit,
|
|
|
|
.ndo_get_stats = enetc_get_stats,
|
|
|
|
.ndo_set_mac_address = enetc_pf_set_mac_addr,
|
|
|
|
.ndo_set_rx_mode = enetc_pf_set_rx_mode,
|
|
|
|
.ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
|
|
|
|
.ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
|
|
|
|
.ndo_set_vf_mac = enetc_pf_set_vf_mac,
|
|
|
|
.ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
|
|
|
|
.ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
|
|
|
|
.ndo_set_features = enetc_pf_set_features,
|
2019-05-22 20:33:29 -06:00
|
|
|
.ndo_do_ioctl = enetc_ioctl,
|
2019-05-27 09:21:31 -06:00
|
|
|
.ndo_setup_tc = enetc_setup_tc,
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
|
|
|
|
const struct net_device_ops *ndev_ops)
|
|
|
|
{
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
|
|
|
|
SET_NETDEV_DEV(ndev, &si->pdev->dev);
|
|
|
|
priv->ndev = ndev;
|
|
|
|
priv->si = si;
|
|
|
|
priv->dev = &si->pdev->dev;
|
|
|
|
si->ndev = ndev;
|
|
|
|
|
|
|
|
priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
|
|
|
|
ndev->netdev_ops = ndev_ops;
|
|
|
|
enetc_set_ethtool_ops(ndev);
|
|
|
|
ndev->watchdog_timeo = 5 * HZ;
|
|
|
|
ndev->max_mtu = ENETC_MAX_MTU;
|
|
|
|
|
2020-11-03 07:02:13 -07:00
|
|
|
ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
|
enetc: permit configuration of rx-vlan-filter with ethtool
Each ENETC station interface (SI) has a VLAN filter list and a port
flag (PSIPVMR) by which it can be put in "VLAN promiscuous" mode, which
enables the reception of VLAN-tagged traffic even if it is not in the
VLAN filtering list.
Currently the handling of this setting works like this: the port starts
off as VLAN promiscuous, then it switches to enabling VLAN filtering as
soon as the first VLAN is installed in its filter via
.ndo_vlan_rx_add_vid. In practice that does not work out very well,
because more often than not, the first VLAN to be installed is out of
the control of the user: the 8021q module, if loaded, adds its rule for
802.1p (VID 0) traffic upon bringing the interface up.
What the user is currently seeing in ethtool is this:
ethtool -k eno2
rx-vlan-filter: on [fixed]
which doesn't match the intention of the code, but the practical reality
of having the 8021q module install its VID which has the side-effect of
turning on VLAN filtering in this driver. All in all, a slightly
confusing experience.
So instead of letting this driver switch the VLAN filtering state by
itself, just wire it up with the rx-vlan-filter feature from ethtool,
and let it be user-configurable just through that knob, except for one
case, see below.
In promiscuous mode, it is more intuitive that all traffic is received,
including VLAN tagged traffic. It appears that it is necessary to set
the flag in PSIPVMR for that to be the case, so VLAN promiscuous mode is
also temporarily enabled. On exit from promiscuous mode, the setting
made by ethtool is restored.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-17 13:07:55 -06:00
|
|
|
NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK;
|
2020-11-03 07:02:13 -07:00
|
|
|
ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
NETIF_F_HW_VLAN_CTAG_TX |
|
enetc: permit configuration of rx-vlan-filter with ethtool
Each ENETC station interface (SI) has a VLAN filter list and a port
flag (PSIPVMR) by which it can be put in "VLAN promiscuous" mode, which
enables the reception of VLAN-tagged traffic even if it is not in the
VLAN filtering list.
Currently the handling of this setting works like this: the port starts
off as VLAN promiscuous, then it switches to enabling VLAN filtering as
soon as the first VLAN is installed in its filter via
.ndo_vlan_rx_add_vid. In practice that does not work out very well,
because more often than not, the first VLAN to be installed is out of
the control of the user: the 8021q module, if loaded, adds its rule for
802.1p (VID 0) traffic upon bringing the interface up.
What the user is currently seeing in ethtool is this:
ethtool -k eno2
rx-vlan-filter: on [fixed]
which doesn't match the intention of the code, but the practical reality
of having the 8021q module install its VID which has the side-effect of
turning on VLAN filtering in this driver. All in all, a slightly
confusing experience.
So instead of letting this driver switch the VLAN filtering state by
itself, just wire it up with the rx-vlan-filter feature from ethtool,
and let it be user-configurable just through that knob, except for one
case, see below.
In promiscuous mode, it is more intuitive that all traffic is received,
including VLAN tagged traffic. It appears that it is necessary to set
the flag in PSIPVMR for that to be the case, so VLAN promiscuous mode is
also temporarily enabled. On exit from promiscuous mode, the setting
made by ethtool is restored.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-17 13:07:55 -06:00
|
|
|
NETIF_F_HW_VLAN_CTAG_RX;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
|
2019-01-22 06:29:57 -07:00
|
|
|
if (si->num_rss)
|
|
|
|
ndev->hw_features |= NETIF_F_RXHASH;
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
ndev->priv_flags |= IFF_UNICAST_FLT;
|
|
|
|
|
2019-11-14 20:33:41 -07:00
|
|
|
if (si->hw_features & ENETC_SI_F_QBV)
|
|
|
|
priv->active_offloads |= ENETC_F_QBV;
|
|
|
|
|
2020-04-30 18:53:18 -06:00
|
|
|
if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
|
2020-04-30 18:53:17 -06:00
|
|
|
priv->active_offloads |= ENETC_F_QCI;
|
|
|
|
ndev->features |= NETIF_F_HW_TC;
|
|
|
|
ndev->hw_features |= NETIF_F_HW_TC;
|
|
|
|
}
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
/* pick up primary MAC address from SI */
|
|
|
|
enetc_get_primary_mac_addr(&si->hw, ndev->dev_addr);
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:20 -06:00
|
|
|
static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
|
2020-01-05 18:34:13 -07:00
|
|
|
{
|
|
|
|
struct device *dev = &pf->si->pdev->dev;
|
|
|
|
struct enetc_mdio_priv *mdio_priv;
|
|
|
|
struct mii_bus *bus;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
|
|
|
|
if (!bus)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
bus->name = "Freescale ENETC MDIO Bus";
|
|
|
|
bus->read = enetc_mdio_read;
|
|
|
|
bus->write = enetc_mdio_write;
|
|
|
|
bus->parent = dev;
|
|
|
|
mdio_priv = bus->priv;
|
|
|
|
mdio_priv->hw = &pf->si->hw;
|
|
|
|
mdio_priv->mdio_base = ENETC_EMDIO_BASE;
|
|
|
|
snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
|
|
|
|
|
|
|
|
err = of_mdiobus_register(bus, np);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "cannot register MDIO bus\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
pf->mdio = bus;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:21 -06:00
|
|
|
static void enetc_mdio_remove(struct enetc_pf *pf)
|
2020-01-05 18:34:13 -07:00
|
|
|
{
|
|
|
|
if (pf->mdio)
|
|
|
|
mdiobus_unregister(pf->mdio);
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:21 -06:00
|
|
|
static int enetc_imdio_create(struct enetc_pf *pf)
|
2020-07-19 16:03:35 -06:00
|
|
|
{
|
|
|
|
struct device *dev = &pf->si->pdev->dev;
|
|
|
|
struct enetc_mdio_priv *mdio_priv;
|
2020-10-07 03:48:23 -06:00
|
|
|
struct lynx_pcs *pcs_lynx;
|
|
|
|
struct mdio_device *pcs;
|
2020-07-19 16:03:35 -06:00
|
|
|
struct mii_bus *bus;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
bus = mdiobus_alloc_size(sizeof(*mdio_priv));
|
|
|
|
if (!bus)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
bus->name = "Freescale ENETC internal MDIO Bus";
|
|
|
|
bus->read = enetc_mdio_read;
|
|
|
|
bus->write = enetc_mdio_write;
|
|
|
|
bus->parent = dev;
|
|
|
|
bus->phy_mask = ~0;
|
|
|
|
mdio_priv = bus->priv;
|
|
|
|
mdio_priv->hw = &pf->si->hw;
|
|
|
|
mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
|
|
|
|
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
|
|
|
|
|
|
|
|
err = mdiobus_register(bus);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
|
|
|
|
goto free_mdio_bus;
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
pcs = mdio_device_create(bus, 0);
|
2020-07-19 16:03:35 -06:00
|
|
|
if (IS_ERR(pcs)) {
|
|
|
|
err = PTR_ERR(pcs);
|
2020-10-07 03:48:23 -06:00
|
|
|
dev_err(dev, "cannot create pcs (%d)\n", err);
|
|
|
|
goto unregister_mdiobus;
|
|
|
|
}
|
|
|
|
|
|
|
|
pcs_lynx = lynx_pcs_create(pcs);
|
|
|
|
if (!pcs_lynx) {
|
|
|
|
mdio_device_free(pcs);
|
|
|
|
err = -ENOMEM;
|
|
|
|
dev_err(dev, "cannot create lynx pcs (%d)\n", err);
|
2020-07-19 16:03:35 -06:00
|
|
|
goto unregister_mdiobus;
|
|
|
|
}
|
|
|
|
|
|
|
|
pf->imdio = bus;
|
2020-10-07 03:48:23 -06:00
|
|
|
pf->pcs = pcs_lynx;
|
2020-07-19 16:03:35 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
unregister_mdiobus:
|
|
|
|
mdiobus_unregister(bus);
|
|
|
|
free_mdio_bus:
|
|
|
|
mdiobus_free(bus);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_imdio_remove(struct enetc_pf *pf)
|
|
|
|
{
|
2020-10-07 03:48:23 -06:00
|
|
|
if (pf->pcs) {
|
|
|
|
mdio_device_free(pf->pcs->mdio);
|
|
|
|
lynx_pcs_destroy(pf->pcs);
|
|
|
|
}
|
2020-07-19 16:03:35 -06:00
|
|
|
if (pf->imdio) {
|
|
|
|
mdiobus_unregister(pf->imdio);
|
|
|
|
mdiobus_free(pf->imdio);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:21 -06:00
|
|
|
static bool enetc_port_has_pcs(struct enetc_pf *pf)
|
|
|
|
{
|
|
|
|
return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
|
|
|
|
pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
|
|
|
|
pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
|
|
|
|
}
|
|
|
|
|
2020-12-04 05:08:00 -07:00
|
|
|
static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
|
2020-10-07 03:48:21 -06:00
|
|
|
{
|
|
|
|
struct device_node *mdio_np;
|
|
|
|
int err;
|
|
|
|
|
2020-12-04 05:08:00 -07:00
|
|
|
mdio_np = of_get_child_by_name(node, "mdio");
|
2020-10-07 03:48:21 -06:00
|
|
|
if (mdio_np) {
|
|
|
|
err = enetc_mdio_probe(pf, mdio_np);
|
|
|
|
|
|
|
|
of_node_put(mdio_np);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (enetc_port_has_pcs(pf)) {
|
|
|
|
err = enetc_imdio_create(pf);
|
|
|
|
if (err) {
|
|
|
|
enetc_mdio_remove(pf);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_mdiobus_destroy(struct enetc_pf *pf)
|
|
|
|
{
|
|
|
|
enetc_mdio_remove(pf);
|
|
|
|
enetc_imdio_remove(pf);
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
static void enetc_pl_mac_validate(struct phylink_config *config,
|
|
|
|
unsigned long *supported,
|
|
|
|
struct phylink_link_state *state)
|
2020-07-19 16:03:35 -06:00
|
|
|
{
|
2020-10-07 03:48:23 -06:00
|
|
|
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
|
|
|
|
|
|
|
|
if (state->interface != PHY_INTERFACE_MODE_NA &&
|
|
|
|
state->interface != PHY_INTERFACE_MODE_INTERNAL &&
|
|
|
|
state->interface != PHY_INTERFACE_MODE_SGMII &&
|
|
|
|
state->interface != PHY_INTERFACE_MODE_2500BASEX &&
|
|
|
|
state->interface != PHY_INTERFACE_MODE_USXGMII &&
|
|
|
|
!phy_interface_mode_is_rgmii(state->interface)) {
|
|
|
|
bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
|
|
return;
|
|
|
|
}
|
2020-07-19 16:03:35 -06:00
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
phylink_set_port_modes(mask);
|
|
|
|
phylink_set(mask, Autoneg);
|
|
|
|
phylink_set(mask, Pause);
|
|
|
|
phylink_set(mask, Asym_Pause);
|
|
|
|
phylink_set(mask, 10baseT_Half);
|
|
|
|
phylink_set(mask, 10baseT_Full);
|
|
|
|
phylink_set(mask, 100baseT_Half);
|
|
|
|
phylink_set(mask, 100baseT_Full);
|
|
|
|
phylink_set(mask, 100baseT_Half);
|
|
|
|
phylink_set(mask, 1000baseT_Half);
|
|
|
|
phylink_set(mask, 1000baseT_Full);
|
|
|
|
|
|
|
|
if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
|
|
|
|
state->interface == PHY_INTERFACE_MODE_2500BASEX ||
|
|
|
|
state->interface == PHY_INTERFACE_MODE_USXGMII) {
|
|
|
|
phylink_set(mask, 2500baseT_Full);
|
|
|
|
phylink_set(mask, 2500baseX_Full);
|
|
|
|
}
|
|
|
|
|
|
|
|
bitmap_and(supported, supported, mask,
|
|
|
|
__ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
|
|
bitmap_and(state->advertising, state->advertising, mask,
|
|
|
|
__ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
|
|
}
|
2020-07-19 16:03:35 -06:00
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
static void enetc_pl_mac_config(struct phylink_config *config,
|
|
|
|
unsigned int mode,
|
|
|
|
const struct phylink_link_state *state)
|
|
|
|
{
|
|
|
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
|
|
|
struct enetc_ndev_priv *priv;
|
2020-07-19 16:03:35 -06:00
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
enetc_mac_config(&pf->si->hw, state->interface);
|
|
|
|
|
|
|
|
priv = netdev_priv(pf->si->ndev);
|
|
|
|
if (pf->pcs)
|
|
|
|
phylink_set_pcs(priv->phylink, &pf->pcs->pcs);
|
2020-07-19 16:03:35 -06:00
|
|
|
}
|
|
|
|
|
2021-03-01 04:18:16 -07:00
|
|
|
static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
|
|
|
|
{
|
|
|
|
u32 old_val, val;
|
|
|
|
|
|
|
|
old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
|
|
|
|
|
|
|
|
if (speed == SPEED_1000) {
|
|
|
|
val &= ~ENETC_PM0_IFM_SSP_MASK;
|
|
|
|
val |= ENETC_PM0_IFM_SSP_1000;
|
|
|
|
} else if (speed == SPEED_100) {
|
|
|
|
val &= ~ENETC_PM0_IFM_SSP_MASK;
|
|
|
|
val |= ENETC_PM0_IFM_SSP_100;
|
|
|
|
} else if (speed == SPEED_10) {
|
|
|
|
val &= ~ENETC_PM0_IFM_SSP_MASK;
|
|
|
|
val |= ENETC_PM0_IFM_SSP_10;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (duplex == DUPLEX_FULL)
|
|
|
|
val |= ENETC_PM0_IFM_FULL_DPX;
|
|
|
|
else
|
|
|
|
val &= ~ENETC_PM0_IFM_FULL_DPX;
|
|
|
|
|
|
|
|
if (val == old_val)
|
|
|
|
return;
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
static void enetc_pl_mac_link_up(struct phylink_config *config,
|
|
|
|
struct phy_device *phy, unsigned int mode,
|
|
|
|
phy_interface_t interface, int speed,
|
|
|
|
int duplex, bool tx_pause, bool rx_pause)
|
2020-07-19 16:03:35 -06:00
|
|
|
{
|
2020-10-07 03:48:23 -06:00
|
|
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
|
|
|
struct enetc_ndev_priv *priv;
|
|
|
|
|
|
|
|
priv = netdev_priv(pf->si->ndev);
|
|
|
|
if (priv->active_offloads & ENETC_F_QBV)
|
|
|
|
enetc_sched_speed_set(priv, speed);
|
2020-07-19 16:03:35 -06:00
|
|
|
|
2021-03-01 04:18:16 -07:00
|
|
|
if (!phylink_autoneg_inband(mode) &&
|
|
|
|
phy_interface_mode_is_rgmii(interface))
|
|
|
|
enetc_force_rgmii_mac(&pf->si->hw, speed, duplex);
|
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
enetc_mac_enable(&pf->si->hw, true);
|
2020-07-19 16:03:35 -06:00
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
static void enetc_pl_mac_link_down(struct phylink_config *config,
|
|
|
|
unsigned int mode,
|
|
|
|
phy_interface_t interface)
|
2020-07-19 16:03:35 -06:00
|
|
|
{
|
2020-10-07 03:48:23 -06:00
|
|
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
|
|
|
|
|
|
|
enetc_mac_enable(&pf->si->hw, false);
|
2020-07-19 16:03:35 -06:00
|
|
|
}
|
|
|
|
|
2020-10-07 03:48:23 -06:00
|
|
|
static const struct phylink_mac_ops enetc_mac_phylink_ops = {
|
|
|
|
.validate = enetc_pl_mac_validate,
|
|
|
|
.mac_config = enetc_pl_mac_config,
|
|
|
|
.mac_link_up = enetc_pl_mac_link_up,
|
|
|
|
.mac_link_down = enetc_pl_mac_link_down,
|
|
|
|
};
|
|
|
|
|
2020-12-04 05:08:00 -07:00
|
|
|
static int enetc_phylink_create(struct enetc_ndev_priv *priv,
|
|
|
|
struct device_node *node)
|
2020-07-19 16:03:35 -06:00
|
|
|
{
|
2020-10-07 03:48:23 -06:00
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
struct phylink *phylink;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
pf->phylink_config.dev = &priv->ndev->dev;
|
|
|
|
pf->phylink_config.type = PHYLINK_NETDEV;
|
|
|
|
|
2020-12-04 05:08:00 -07:00
|
|
|
phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
|
2020-10-07 03:48:23 -06:00
|
|
|
pf->if_mode, &enetc_mac_phylink_ops);
|
|
|
|
if (IS_ERR(phylink)) {
|
|
|
|
err = PTR_ERR(phylink);
|
|
|
|
return err;
|
2020-07-19 16:03:35 -06:00
|
|
|
}
|
2020-10-07 03:48:23 -06:00
|
|
|
|
|
|
|
priv->phylink = phylink;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
|
|
|
|
{
|
|
|
|
if (priv->phylink)
|
|
|
|
phylink_destroy(priv->phylink);
|
2020-07-22 06:38:48 -06:00
|
|
|
}
|
|
|
|
|
net: enetc: initialize the RFS and RSS memories
Michael tried to enable Advanced Error Reporting through the ENETC's
Root Complex Event Collector, and the system started spitting out single
bit correctable ECC errors coming from the ENETC interfaces:
pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
fsl_enetc 0000:00:00.0: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.0: device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.0: [14] CorrIntErr
fsl_enetc 0000:00:00.1: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.1: device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.1: [14] CorrIntErr
Further investigating the port correctable memory error detect register
(PCMEDR) shows that these AER errors have an associated SOURCE_ID of 6
(RFS/RSS):
$ devmem 0x1f8010e10 32
0xC0000006
$ devmem 0x1f8050e10 32
0xC0000006
Discussion with the hardware design engineers reveals that on LS1028A,
the hardware does not do initialization of that RFS/RSS memory, and that
software should clear/initialize the entire table before starting to
operate. That comes as a bit of a surprise, since the driver does not do
initialization of the RFS memory. Also, the initialization of the
Receive Side Scaling is done only partially.
Even though the entire ENETC IP has a single shared flow steering
memory, the flow steering service should returns matches only for TCAM
entries that are within the range of the Station Interface that is doing
the search. Therefore, it should be sufficient for a Station Interface
to initialize all of its own entries in order to avoid any ECC errors,
and only the Station Interfaces in use should need initialization.
There are Physical Station Interfaces associated with PCIe PFs and
Virtual Station Interfaces associated with PCIe VFs. We let the PF
driver initialize the entire port's memory, which includes the RFS
entries which are going to be used by the VF.
Reported-by: Michael Walle <michael@walle.cc>
Fixes: d4fd0404c1c9 ("enetc: Introduce basic PF and VF ENETC ethernet drivers")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Link: https://lore.kernel.org/r/20210204134511.2640309-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-02-04 06:45:11 -07:00
|
|
|
/* Initialize the entire shared memory for the flow steering entries
|
|
|
|
* of this port (PF + VFs)
|
|
|
|
*/
|
|
|
|
static int enetc_init_port_rfs_memory(struct enetc_si *si)
|
|
|
|
{
|
|
|
|
struct enetc_cmd_rfse rfse = {0};
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
int num_rfs, i, err = 0;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = enetc_port_rd(hw, ENETC_PRFSCAPR);
|
|
|
|
num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
|
|
|
|
|
|
|
|
for (i = 0; i < num_rfs; i++) {
|
|
|
|
err = enetc_set_fs_entry(si, &rfse, i);
|
|
|
|
if (err)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int enetc_init_port_rss_memory(struct enetc_si *si)
|
|
|
|
{
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
int num_rss, err;
|
|
|
|
int *rss_table;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = enetc_port_rd(hw, ENETC_PRSSCAPR);
|
|
|
|
num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
|
|
|
|
if (!num_rss)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
|
|
|
|
if (!rss_table)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
err = enetc_set_rss_table(si, rss_table, num_rss);
|
|
|
|
|
|
|
|
kfree(rss_table);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
net: enetc: initialize RFS/RSS memories for unused ports too
Michael reports that since linux-next-20210211, the AER messages for ECC
errors have started reappearing, and this time they can be reliably
reproduced with the first ping on one of his LS1028A boards.
$ ping 1[ 33.258069] pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
72.16.0.1
PING [ 33.267050] pcieport 0000:00:1f.0: AER: can't find device of ID0000
172.16.0.1 (172.16.0.1): 56 data bytes
64 bytes from 172.16.0.1: seq=0 ttl=64 time=17.124 ms
64 bytes from 172.16.0.1: seq=1 ttl=64 time=0.273 ms
$ devmem 0x1f8010e10 32
0xC0000006
It isn't clear why this is necessary, but it seems that for the errors
to go away, we must clear the entire RFS and RSS memory, not just for
the ports in use.
Sadly the code is structured in such a way that we can't have unified
logic for the used and unused ports. For the minimal initialization of
an unused port, we need just to enable and ioremap the PF memory space,
and a control buffer descriptor ring. Unused ports must then free the
CBDR because the driver will exit, but used ports can not pick up from
where that code path left, since the CBDR API does not reinitialize a
ring when setting it up, so its producer and consumer indices are out of
sync between the software and hardware state. So a separate
enetc_init_unused_port function was created, and it gets called right
after the PF memory space is enabled.
Fixes: 07bf34a50e32 ("net: enetc: initialize the RFS and RSS memories")
Reported-by: Michael Walle <michael@walle.cc>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-01 04:18:12 -07:00
|
|
|
static void enetc_init_unused_port(struct enetc_si *si)
|
|
|
|
{
|
|
|
|
struct device *dev = &si->pdev->dev;
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
si->cbd_ring.bd_count = ENETC_CBDR_DEFAULT_SIZE;
|
|
|
|
err = enetc_alloc_cbdr(dev, &si->cbd_ring);
|
|
|
|
if (err)
|
|
|
|
return;
|
|
|
|
|
|
|
|
enetc_setup_cbdr(hw, &si->cbd_ring);
|
|
|
|
|
|
|
|
enetc_init_port_rfs_memory(si);
|
|
|
|
enetc_init_port_rss_memory(si);
|
|
|
|
|
|
|
|
enetc_clear_cbdr(hw);
|
|
|
|
enetc_free_cbdr(dev, &si->cbd_ring);
|
|
|
|
}
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
static int enetc_pf_probe(struct pci_dev *pdev,
|
|
|
|
const struct pci_device_id *ent)
|
|
|
|
{
|
2020-12-04 05:08:00 -07:00
|
|
|
struct device_node *node = pdev->dev.of_node;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
struct enetc_ndev_priv *priv;
|
|
|
|
struct net_device *ndev;
|
|
|
|
struct enetc_si *si;
|
|
|
|
struct enetc_pf *pf;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "PCI probing failed\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
si = pci_get_drvdata(pdev);
|
|
|
|
if (!si->hw.port || !si->hw.global) {
|
|
|
|
err = -ENODEV;
|
|
|
|
dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
|
|
|
|
goto err_map_pf_space;
|
|
|
|
}
|
|
|
|
|
net: enetc: initialize RFS/RSS memories for unused ports too
Michael reports that since linux-next-20210211, the AER messages for ECC
errors have started reappearing, and this time they can be reliably
reproduced with the first ping on one of his LS1028A boards.
$ ping 1[ 33.258069] pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
72.16.0.1
PING [ 33.267050] pcieport 0000:00:1f.0: AER: can't find device of ID0000
172.16.0.1 (172.16.0.1): 56 data bytes
64 bytes from 172.16.0.1: seq=0 ttl=64 time=17.124 ms
64 bytes from 172.16.0.1: seq=1 ttl=64 time=0.273 ms
$ devmem 0x1f8010e10 32
0xC0000006
It isn't clear why this is necessary, but it seems that for the errors
to go away, we must clear the entire RFS and RSS memory, not just for
the ports in use.
Sadly the code is structured in such a way that we can't have unified
logic for the used and unused ports. For the minimal initialization of
an unused port, we need just to enable and ioremap the PF memory space,
and a control buffer descriptor ring. Unused ports must then free the
CBDR because the driver will exit, but used ports can not pick up from
where that code path left, since the CBDR API does not reinitialize a
ring when setting it up, so its producer and consumer indices are out of
sync between the software and hardware state. So a separate
enetc_init_unused_port function was created, and it gets called right
after the PF memory space is enabled.
Fixes: 07bf34a50e32 ("net: enetc: initialize the RFS and RSS memories")
Reported-by: Michael Walle <michael@walle.cc>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-01 04:18:12 -07:00
|
|
|
if (node && !of_device_is_available(node)) {
|
|
|
|
enetc_init_unused_port(si);
|
|
|
|
dev_info(&pdev->dev, "device is disabled, skipping\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto err_device_disabled;
|
|
|
|
}
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
pf = enetc_si_priv(si);
|
|
|
|
pf->si = si;
|
|
|
|
pf->total_vfs = pci_sriov_get_totalvfs(pdev);
|
|
|
|
|
|
|
|
enetc_configure_port(pf);
|
|
|
|
|
|
|
|
enetc_get_si_caps(si);
|
|
|
|
|
|
|
|
ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
|
|
|
|
if (!ndev) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
dev_err(&pdev->dev, "netdev creation failed\n");
|
|
|
|
goto err_alloc_netdev;
|
|
|
|
}
|
|
|
|
|
|
|
|
enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
|
|
|
|
|
|
|
|
priv = netdev_priv(ndev);
|
|
|
|
|
|
|
|
enetc_init_si_rings_params(priv);
|
|
|
|
|
|
|
|
err = enetc_alloc_si_resources(priv);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "SI resource alloc failed\n");
|
|
|
|
goto err_alloc_si_res;
|
|
|
|
}
|
|
|
|
|
net: enetc: initialize the RFS and RSS memories
Michael tried to enable Advanced Error Reporting through the ENETC's
Root Complex Event Collector, and the system started spitting out single
bit correctable ECC errors coming from the ENETC interfaces:
pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
fsl_enetc 0000:00:00.0: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.0: device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.0: [14] CorrIntErr
fsl_enetc 0000:00:00.1: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.1: device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.1: [14] CorrIntErr
Further investigating the port correctable memory error detect register
(PCMEDR) shows that these AER errors have an associated SOURCE_ID of 6
(RFS/RSS):
$ devmem 0x1f8010e10 32
0xC0000006
$ devmem 0x1f8050e10 32
0xC0000006
Discussion with the hardware design engineers reveals that on LS1028A,
the hardware does not do initialization of that RFS/RSS memory, and that
software should clear/initialize the entire table before starting to
operate. That comes as a bit of a surprise, since the driver does not do
initialization of the RFS memory. Also, the initialization of the
Receive Side Scaling is done only partially.
Even though the entire ENETC IP has a single shared flow steering
memory, the flow steering service should returns matches only for TCAM
entries that are within the range of the Station Interface that is doing
the search. Therefore, it should be sufficient for a Station Interface
to initialize all of its own entries in order to avoid any ECC errors,
and only the Station Interfaces in use should need initialization.
There are Physical Station Interfaces associated with PCIe PFs and
Virtual Station Interfaces associated with PCIe VFs. We let the PF
driver initialize the entire port's memory, which includes the RFS
entries which are going to be used by the VF.
Reported-by: Michael Walle <michael@walle.cc>
Fixes: d4fd0404c1c9 ("enetc: Introduce basic PF and VF ENETC ethernet drivers")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Link: https://lore.kernel.org/r/20210204134511.2640309-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-02-04 06:45:11 -07:00
|
|
|
err = enetc_init_port_rfs_memory(si);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
|
|
|
|
goto err_init_port_rfs;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = enetc_init_port_rss_memory(si);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
|
|
|
|
goto err_init_port_rss;
|
|
|
|
}
|
|
|
|
|
2021-03-01 04:18:11 -07:00
|
|
|
err = enetc_configure_si(priv);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to configure SI\n");
|
|
|
|
goto err_config_si;
|
|
|
|
}
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
err = enetc_alloc_msix(priv);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "MSIX alloc failed\n");
|
|
|
|
goto err_alloc_msix;
|
|
|
|
}
|
|
|
|
|
2020-12-04 05:08:00 -07:00
|
|
|
if (!of_get_phy_mode(node, &pf->if_mode)) {
|
|
|
|
err = enetc_mdiobus_create(pf, node);
|
2020-10-07 03:48:20 -06:00
|
|
|
if (err)
|
|
|
|
goto err_mdiobus_create;
|
|
|
|
|
2020-12-04 05:08:00 -07:00
|
|
|
err = enetc_phylink_create(priv, node);
|
2020-10-07 03:48:23 -06:00
|
|
|
if (err)
|
|
|
|
goto err_phylink_create;
|
2020-10-07 03:48:20 -06:00
|
|
|
}
|
2020-07-19 16:03:35 -06:00
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
err = register_netdev(ndev);
|
|
|
|
if (err)
|
|
|
|
goto err_reg_netdev;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_reg_netdev:
|
2020-10-07 03:48:23 -06:00
|
|
|
enetc_phylink_destroy(priv);
|
|
|
|
err_phylink_create:
|
2020-10-07 03:48:20 -06:00
|
|
|
enetc_mdiobus_destroy(pf);
|
|
|
|
err_mdiobus_create:
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
enetc_free_msix(priv);
|
2021-03-01 04:18:11 -07:00
|
|
|
err_config_si:
|
net: enetc: initialize the RFS and RSS memories
Michael tried to enable Advanced Error Reporting through the ENETC's
Root Complex Event Collector, and the system started spitting out single
bit correctable ECC errors coming from the ENETC interfaces:
pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
fsl_enetc 0000:00:00.0: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.0: device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.0: [14] CorrIntErr
fsl_enetc 0000:00:00.1: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.1: device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.1: [14] CorrIntErr
Further investigating the port correctable memory error detect register
(PCMEDR) shows that these AER errors have an associated SOURCE_ID of 6
(RFS/RSS):
$ devmem 0x1f8010e10 32
0xC0000006
$ devmem 0x1f8050e10 32
0xC0000006
Discussion with the hardware design engineers reveals that on LS1028A,
the hardware does not do initialization of that RFS/RSS memory, and that
software should clear/initialize the entire table before starting to
operate. That comes as a bit of a surprise, since the driver does not do
initialization of the RFS memory. Also, the initialization of the
Receive Side Scaling is done only partially.
Even though the entire ENETC IP has a single shared flow steering
memory, the flow steering service should returns matches only for TCAM
entries that are within the range of the Station Interface that is doing
the search. Therefore, it should be sufficient for a Station Interface
to initialize all of its own entries in order to avoid any ECC errors,
and only the Station Interfaces in use should need initialization.
There are Physical Station Interfaces associated with PCIe PFs and
Virtual Station Interfaces associated with PCIe VFs. We let the PF
driver initialize the entire port's memory, which includes the RFS
entries which are going to be used by the VF.
Reported-by: Michael Walle <michael@walle.cc>
Fixes: d4fd0404c1c9 ("enetc: Introduce basic PF and VF ENETC ethernet drivers")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Link: https://lore.kernel.org/r/20210204134511.2640309-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-02-04 06:45:11 -07:00
|
|
|
err_init_port_rss:
|
|
|
|
err_init_port_rfs:
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
err_alloc_msix:
|
|
|
|
enetc_free_si_resources(priv);
|
|
|
|
err_alloc_si_res:
|
|
|
|
si->ndev = NULL;
|
|
|
|
free_netdev(ndev);
|
|
|
|
err_alloc_netdev:
|
net: enetc: initialize RFS/RSS memories for unused ports too
Michael reports that since linux-next-20210211, the AER messages for ECC
errors have started reappearing, and this time they can be reliably
reproduced with the first ping on one of his LS1028A boards.
$ ping 1[ 33.258069] pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
72.16.0.1
PING [ 33.267050] pcieport 0000:00:1f.0: AER: can't find device of ID0000
172.16.0.1 (172.16.0.1): 56 data bytes
64 bytes from 172.16.0.1: seq=0 ttl=64 time=17.124 ms
64 bytes from 172.16.0.1: seq=1 ttl=64 time=0.273 ms
$ devmem 0x1f8010e10 32
0xC0000006
It isn't clear why this is necessary, but it seems that for the errors
to go away, we must clear the entire RFS and RSS memory, not just for
the ports in use.
Sadly the code is structured in such a way that we can't have unified
logic for the used and unused ports. For the minimal initialization of
an unused port, we need just to enable and ioremap the PF memory space,
and a control buffer descriptor ring. Unused ports must then free the
CBDR because the driver will exit, but used ports can not pick up from
where that code path left, since the CBDR API does not reinitialize a
ring when setting it up, so its producer and consumer indices are out of
sync between the software and hardware state. So a separate
enetc_init_unused_port function was created, and it gets called right
after the PF memory space is enabled.
Fixes: 07bf34a50e32 ("net: enetc: initialize the RFS and RSS memories")
Reported-by: Michael Walle <michael@walle.cc>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-01 04:18:12 -07:00
|
|
|
err_device_disabled:
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
err_map_pf_space:
|
|
|
|
enetc_pci_remove(pdev);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enetc_pf_remove(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct enetc_si *si = pci_get_drvdata(pdev);
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
struct enetc_ndev_priv *priv;
|
|
|
|
|
2020-10-07 03:48:20 -06:00
|
|
|
priv = netdev_priv(si->ndev);
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
if (pf->num_vfs)
|
|
|
|
enetc_sriov_configure(pdev, 0);
|
|
|
|
|
|
|
|
unregister_netdev(si->ndev);
|
|
|
|
|
2021-02-16 03:16:28 -07:00
|
|
|
enetc_phylink_destroy(priv);
|
|
|
|
enetc_mdiobus_destroy(pf);
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 06:29:54 -07:00
|
|
|
enetc_free_msix(priv);
|
|
|
|
|
|
|
|
enetc_free_si_resources(priv);
|
|
|
|
|
|
|
|
free_netdev(si->ndev);
|
|
|
|
|
|
|
|
enetc_pci_remove(pdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pci_device_id enetc_pf_id_table[] = {
|
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
|
|
|
|
{ 0, } /* End of table. */
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
|
|
|
|
|
|
|
|
static struct pci_driver enetc_pf_driver = {
|
|
|
|
.name = KBUILD_MODNAME,
|
|
|
|
.id_table = enetc_pf_id_table,
|
|
|
|
.probe = enetc_pf_probe,
|
|
|
|
.remove = enetc_pf_remove,
|
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
.sriov_configure = enetc_sriov_configure,
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
module_pci_driver(enetc_pf_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|