2019-06-01 02:08:37 -06:00
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// SPDX-License-Identifier: GPL-2.0-only
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2016-04-01 03:37:28 -06:00
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/*
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* This contains the functions to handle the descriptors for DesignWare databook
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* 4.xx.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#include <linux/stmmac.h>
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#include "common.h"
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2020-01-13 09:24:12 -07:00
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#include "dwmac4.h"
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2016-04-01 03:37:28 -06:00
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#include "dwmac4_descs.h"
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static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p,
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void __iomem *ioaddr)
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{
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struct net_device_stats *stats = (struct net_device_stats *)data;
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unsigned int tdes3;
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int ret = tx_done;
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2016-11-14 10:58:05 -07:00
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tdes3 = le32_to_cpu(p->des3);
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2016-04-01 03:37:28 -06:00
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/* Get tx owner first */
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if (unlikely(tdes3 & TDES3_OWN))
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return tx_dma_own;
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/* Verify tx error by looking at the last segment. */
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if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
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return tx_not_ls;
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if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
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if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
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x->tx_jabber++;
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if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
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x->tx_frame_flushed++;
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if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
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x->tx_losscarrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
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x->tx_carrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
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(tdes3 & TDES3_EXCESSIVE_COLLISION)))
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stats->collisions +=
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(tdes3 & TDES3_COLLISION_COUNT_MASK)
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>> TDES3_COLLISION_COUNT_SHIFT;
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if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
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x->tx_deferred++;
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if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
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x->tx_underflow++;
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if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
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x->tx_ip_header_error++;
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if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
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x->tx_payload_error++;
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ret = tx_err;
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}
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if (unlikely(tdes3 & TDES3_DEFERRED))
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x->tx_deferred++;
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return ret;
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}
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static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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struct net_device_stats *stats = (struct net_device_stats *)data;
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2016-11-14 10:58:05 -07:00
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unsigned int rdes1 = le32_to_cpu(p->des1);
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unsigned int rdes2 = le32_to_cpu(p->des2);
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unsigned int rdes3 = le32_to_cpu(p->des3);
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2016-04-01 03:37:28 -06:00
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int message_type;
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int ret = good_frame;
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if (unlikely(rdes3 & RDES3_OWN))
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return dma_own;
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2019-11-11 07:42:35 -07:00
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if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
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2016-04-01 03:37:28 -06:00
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return discard_frame;
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2019-11-11 07:42:35 -07:00
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if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
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return rx_not_ls;
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2016-04-01 03:37:28 -06:00
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if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
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if (unlikely(rdes3 & RDES3_GIANT_PACKET))
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stats->rx_length_errors++;
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if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
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x->rx_gmac_overflow++;
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if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
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x->rx_watchdog++;
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if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
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x->rx_mii++;
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if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
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2017-02-08 01:31:17 -07:00
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x->rx_crc_errors++;
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2016-04-01 03:37:28 -06:00
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stats->rx_crc_errors++;
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}
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if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
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x->dribbling_bit++;
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ret = discard_frame;
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}
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message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
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if (rdes1 & RDES1_IP_HDR_ERROR)
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x->ip_hdr_err++;
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if (rdes1 & RDES1_IP_CSUM_BYPASSED)
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x->ip_csum_bypassed++;
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if (rdes1 & RDES1_IPV4_HEADER)
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x->ipv4_pkt_rcvd++;
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if (rdes1 & RDES1_IPV6_HEADER)
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x->ipv6_pkt_rcvd++;
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2016-11-14 01:27:30 -07:00
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if (message_type == RDES_EXT_NO_PTP)
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x->no_ptp_rx_msg_type_ext++;
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else if (message_type == RDES_EXT_SYNC)
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x->ptp_rx_msg_type_sync++;
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2016-04-01 03:37:28 -06:00
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else if (message_type == RDES_EXT_FOLLOW_UP)
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2016-11-14 01:27:30 -07:00
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x->ptp_rx_msg_type_follow_up++;
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2016-04-01 03:37:28 -06:00
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else if (message_type == RDES_EXT_DELAY_REQ)
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2016-11-14 01:27:30 -07:00
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x->ptp_rx_msg_type_delay_req++;
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2016-04-01 03:37:28 -06:00
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else if (message_type == RDES_EXT_DELAY_RESP)
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2016-11-14 01:27:30 -07:00
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x->ptp_rx_msg_type_delay_resp++;
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2016-04-01 03:37:28 -06:00
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else if (message_type == RDES_EXT_PDELAY_REQ)
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2016-11-14 01:27:30 -07:00
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x->ptp_rx_msg_type_pdelay_req++;
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2016-04-01 03:37:28 -06:00
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else if (message_type == RDES_EXT_PDELAY_RESP)
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2016-11-14 01:27:30 -07:00
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x->ptp_rx_msg_type_pdelay_resp++;
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2016-04-01 03:37:28 -06:00
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else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
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2016-11-14 01:27:30 -07:00
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x->ptp_rx_msg_type_pdelay_follow_up++;
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else if (message_type == RDES_PTP_ANNOUNCE)
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x->ptp_rx_msg_type_announce++;
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else if (message_type == RDES_PTP_MANAGEMENT)
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x->ptp_rx_msg_type_management++;
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else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
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x->ptp_rx_msg_pkt_reserved_type++;
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2016-04-01 03:37:28 -06:00
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if (rdes1 & RDES1_PTP_PACKET_TYPE)
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x->ptp_frame_type++;
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if (rdes1 & RDES1_PTP_VER)
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x->ptp_ver++;
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if (rdes1 & RDES1_TIMESTAMP_DROPPED)
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x->timestamp_dropped++;
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if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
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x->sa_rx_filter_fail++;
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ret = discard_frame;
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}
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if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
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x->da_rx_filter_fail++;
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ret = discard_frame;
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}
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if (rdes2 & RDES2_L3_FILTER_MATCH)
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x->l3_filter_match++;
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if (rdes2 & RDES2_L4_FILTER_MATCH)
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x->l4_filter_match++;
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if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
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>> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
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x->l3_l4_filter_no_match++;
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return ret;
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}
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static int dwmac4_rd_get_tx_len(struct dma_desc *p)
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{
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2016-11-14 10:58:05 -07:00
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return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
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2016-04-01 03:37:28 -06:00
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}
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static int dwmac4_get_tx_owner(struct dma_desc *p)
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{
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2016-11-14 10:58:05 -07:00
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return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
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2016-04-01 03:37:28 -06:00
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}
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static void dwmac4_set_tx_owner(struct dma_desc *p)
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{
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2016-11-14 10:58:05 -07:00
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p->des3 |= cpu_to_le32(TDES3_OWN);
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2016-04-01 03:37:28 -06:00
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}
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2018-05-18 07:56:07 -06:00
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static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
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2016-04-01 03:37:28 -06:00
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{
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2019-11-11 07:42:35 -07:00
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p->des3 |= cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
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2018-05-18 07:56:07 -06:00
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if (!disable_rx_ic)
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p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
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2016-04-01 03:37:28 -06:00
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}
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static int dwmac4_get_tx_ls(struct dma_desc *p)
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{
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2016-11-14 10:58:05 -07:00
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return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
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>> TDES3_LAST_DESCRIPTOR_SHIFT;
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2016-04-01 03:37:28 -06:00
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}
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static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
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{
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2016-11-14 10:58:05 -07:00
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return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
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2016-04-01 03:37:28 -06:00
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}
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static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
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{
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2016-11-14 10:58:05 -07:00
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p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
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2016-04-01 03:37:28 -06:00
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}
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static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
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{
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2016-11-14 01:27:29 -07:00
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/* Context type from W/B descriptor must be zero */
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2016-11-22 09:29:28 -07:00
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if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
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2017-06-08 15:03:09 -06:00
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return 0;
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2016-11-14 01:27:29 -07:00
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/* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
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2016-11-22 09:29:28 -07:00
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if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
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2017-06-08 15:03:09 -06:00
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return 1;
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2016-11-14 01:27:29 -07:00
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2017-06-08 15:03:09 -06:00
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return 0;
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2016-04-01 03:37:28 -06:00
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}
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2018-04-16 09:08:12 -06:00
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static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
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2016-04-01 03:37:28 -06:00
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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u64 ns;
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2016-11-14 10:58:05 -07:00
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ns = le32_to_cpu(p->des0);
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2016-04-01 03:37:28 -06:00
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/* convert high/sec time stamp value to nanosecond */
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2016-11-14 10:58:05 -07:00
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ns += le32_to_cpu(p->des1) * 1000000000ULL;
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2016-04-01 03:37:28 -06:00
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2018-04-16 09:08:12 -06:00
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*ts = ns;
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2016-04-01 03:37:28 -06:00
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}
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2016-11-14 01:27:29 -07:00
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static int dwmac4_rx_check_timestamp(void *desc)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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2019-02-15 02:49:09 -07:00
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unsigned int rdes0 = le32_to_cpu(p->des0);
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unsigned int rdes1 = le32_to_cpu(p->des1);
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unsigned int rdes3 = le32_to_cpu(p->des3);
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2016-11-14 01:27:29 -07:00
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u32 own, ctxt;
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int ret = 1;
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2019-02-15 02:49:09 -07:00
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own = rdes3 & RDES3_OWN;
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ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
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2016-11-14 01:27:29 -07:00
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>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
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if (likely(!own && ctxt)) {
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2019-02-15 02:49:09 -07:00
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if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
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2016-11-14 01:27:29 -07:00
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/* Corrupted value */
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ret = -EINVAL;
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else
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/* A valid Timestamp is ready to be read */
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ret = 0;
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}
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/* Timestamp not ready */
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return ret;
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}
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2017-12-18 15:34:00 -07:00
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static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
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u32 ats)
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2016-04-01 03:37:28 -06:00
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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2016-11-14 01:27:29 -07:00
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int ret = -EINVAL;
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/* Get the status from normal w/b descriptor */
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2019-02-14 09:03:44 -07:00
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if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
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2016-11-22 09:29:28 -07:00
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if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
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2016-11-14 01:27:29 -07:00
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int i = 0;
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/* Check if timestamp is OK from context descriptor */
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do {
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2017-12-18 15:34:00 -07:00
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ret = dwmac4_rx_check_timestamp(next_desc);
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2016-11-14 01:27:29 -07:00
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if (ret < 0)
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goto exit;
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i++;
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2016-04-01 03:37:28 -06:00
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2017-10-20 07:37:36 -06:00
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} while ((ret == 1) && (i < 10));
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2016-11-14 01:27:29 -07:00
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if (i == 10)
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ret = -EBUSY;
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}
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}
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exit:
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2017-06-08 15:03:09 -06:00
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if (likely(ret == 0))
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return 1;
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return 0;
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2016-04-01 03:37:28 -06:00
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}
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|
static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
|
2019-03-27 14:35:35 -06:00
|
|
|
int mode, int end, int bfsize)
|
2016-04-01 03:37:28 -06:00
|
|
|
{
|
2018-05-18 07:56:07 -06:00
|
|
|
dwmac4_set_rx_owner(p, disable_rx_ic);
|
2016-04-01 03:37:28 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
|
|
|
|
{
|
|
|
|
p->des0 = 0;
|
|
|
|
p->des1 = 0;
|
|
|
|
p->des2 = 0;
|
|
|
|
p->des3 = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
|
|
|
|
bool csum_flag, int mode, bool tx_own,
|
2017-04-10 12:33:29 -06:00
|
|
|
bool ls, unsigned int tot_pkt_len)
|
2016-04-01 03:37:28 -06:00
|
|
|
{
|
2016-11-14 10:58:05 -07:00
|
|
|
unsigned int tdes3 = le32_to_cpu(p->des3);
|
2016-04-01 03:37:28 -06:00
|
|
|
|
2016-11-14 10:58:05 -07:00
|
|
|
p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
|
2016-04-01 03:37:28 -06:00
|
|
|
|
2017-04-10 12:33:29 -06:00
|
|
|
tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
|
2016-04-01 03:37:28 -06:00
|
|
|
if (is_fs)
|
|
|
|
tdes3 |= TDES3_FIRST_DESCRIPTOR;
|
|
|
|
else
|
|
|
|
tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
|
|
|
|
|
|
|
|
if (likely(csum_flag))
|
|
|
|
tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
|
|
|
|
else
|
|
|
|
tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
|
|
|
|
|
|
|
|
if (ls)
|
|
|
|
tdes3 |= TDES3_LAST_DESCRIPTOR;
|
|
|
|
else
|
|
|
|
tdes3 &= ~TDES3_LAST_DESCRIPTOR;
|
|
|
|
|
|
|
|
/* Finally set the OWN bit. Later the DMA will start! */
|
|
|
|
if (tx_own)
|
|
|
|
tdes3 |= TDES3_OWN;
|
|
|
|
|
2018-01-22 08:59:50 -07:00
|
|
|
if (is_fs && tx_own)
|
2016-04-01 03:37:28 -06:00
|
|
|
/* When the own bit, for the first frame, has to be set, all
|
|
|
|
* descriptors for the same frame has to be set before, to
|
|
|
|
* avoid race condition.
|
|
|
|
*/
|
2016-12-18 13:38:12 -07:00
|
|
|
dma_wmb();
|
2016-04-01 03:37:28 -06:00
|
|
|
|
2016-11-14 10:58:05 -07:00
|
|
|
p->des3 = cpu_to_le32(tdes3);
|
2016-04-01 03:37:28 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
|
|
|
|
int len1, int len2, bool tx_own,
|
|
|
|
bool ls, unsigned int tcphdrlen,
|
|
|
|
unsigned int tcppayloadlen)
|
|
|
|
{
|
2016-11-14 10:58:05 -07:00
|
|
|
unsigned int tdes3 = le32_to_cpu(p->des3);
|
2016-04-01 03:37:28 -06:00
|
|
|
|
|
|
|
if (len1)
|
2016-11-14 10:58:05 -07:00
|
|
|
p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
|
2016-04-01 03:37:28 -06:00
|
|
|
|
|
|
|
if (len2)
|
2016-11-14 10:58:05 -07:00
|
|
|
p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
|
|
|
|
& TDES2_BUFFER2_SIZE_MASK);
|
2016-04-01 03:37:28 -06:00
|
|
|
|
|
|
|
if (is_fs) {
|
|
|
|
tdes3 |= TDES3_FIRST_DESCRIPTOR |
|
|
|
|
TDES3_TCP_SEGMENTATION_ENABLE |
|
|
|
|
((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
|
|
|
|
TDES3_SLOT_NUMBER_MASK) |
|
|
|
|
((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
|
|
|
|
} else {
|
|
|
|
tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ls)
|
|
|
|
tdes3 |= TDES3_LAST_DESCRIPTOR;
|
|
|
|
else
|
|
|
|
tdes3 &= ~TDES3_LAST_DESCRIPTOR;
|
|
|
|
|
|
|
|
/* Finally set the OWN bit. Later the DMA will start! */
|
|
|
|
if (tx_own)
|
|
|
|
tdes3 |= TDES3_OWN;
|
|
|
|
|
2018-01-22 08:59:50 -07:00
|
|
|
if (is_fs && tx_own)
|
2016-04-01 03:37:28 -06:00
|
|
|
/* When the own bit, for the first frame, has to be set, all
|
|
|
|
* descriptors for the same frame has to be set before, to
|
|
|
|
* avoid race condition.
|
|
|
|
*/
|
2016-12-18 13:38:12 -07:00
|
|
|
dma_wmb();
|
2016-04-01 03:37:28 -06:00
|
|
|
|
2016-11-14 10:58:05 -07:00
|
|
|
p->des3 = cpu_to_le32(tdes3);
|
2016-04-01 03:37:28 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
|
|
|
|
{
|
net: stmmac: make dwmac4_release_tx_desc() clear all descriptor fields
Make dwmac4_release_tx_desc() clear all descriptor fields, not just
TDES2 and TDES3.
I'm suspecting that TDES0 and TDES1 wasn't cleared because the DMA
engine uses them to store the tx hardware timestamp (if PTP is enabled).
However, stmmac_tx_clean() calls stmmac_get_tx_hwtstamp(), which reads
and saves the timestamp, before it calls release_tx_desc(), so this
is not an issue.
stmmac_xmit() and stmmac_tso_xmit() both always overwrite TDES0,
however, stmmac_tso_xmit() sometimes sets TDES1, and since neither
stmmac_xmit() nor stmmac_tso_xmit() explicitly clears TDES1, both
functions might reuse a DMA descriptor with old TDES1 data.
I haven't observed any misbehavior even though TDES1 sometimes
point to an old skb, however, explicitly clearing both TDES0 and TDES1
in dwmac4_release_tx_desc() minimizes the chances of undefined behavior.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-02-26 14:47:09 -07:00
|
|
|
p->des0 = 0;
|
|
|
|
p->des1 = 0;
|
2016-04-01 03:37:28 -06:00
|
|
|
p->des2 = 0;
|
|
|
|
p->des3 = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
|
|
|
|
{
|
2016-11-14 10:58:05 -07:00
|
|
|
p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
|
2016-04-01 03:37:28 -06:00
|
|
|
}
|
|
|
|
|
2021-02-25 02:01:12 -07:00
|
|
|
static void dwmac4_display_ring(void *head, unsigned int size, bool rx,
|
|
|
|
dma_addr_t dma_rx_phy, unsigned int desc_size)
|
2016-04-01 03:37:28 -06:00
|
|
|
{
|
2021-02-25 02:01:12 -07:00
|
|
|
dma_addr_t dma_addr;
|
2016-04-01 03:37:28 -06:00
|
|
|
int i;
|
|
|
|
|
|
|
|
pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
|
|
|
|
|
2021-02-25 02:01:12 -07:00
|
|
|
if (desc_size == sizeof(struct dma_desc)) {
|
|
|
|
struct dma_desc *p = (struct dma_desc *)head;
|
|
|
|
|
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
dma_addr = dma_rx_phy + i * sizeof(*p);
|
|
|
|
pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
|
|
|
|
i, &dma_addr,
|
|
|
|
le32_to_cpu(p->des0), le32_to_cpu(p->des1),
|
|
|
|
le32_to_cpu(p->des2), le32_to_cpu(p->des3));
|
|
|
|
p++;
|
|
|
|
}
|
|
|
|
} else if (desc_size == sizeof(struct dma_extended_desc)) {
|
|
|
|
struct dma_extended_desc *extp = (struct dma_extended_desc *)head;
|
|
|
|
|
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
dma_addr = dma_rx_phy + i * sizeof(*extp);
|
|
|
|
pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
|
|
|
|
i, &dma_addr,
|
|
|
|
le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1),
|
|
|
|
le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3),
|
|
|
|
le32_to_cpu(extp->des4), le32_to_cpu(extp->des5),
|
|
|
|
le32_to_cpu(extp->des6), le32_to_cpu(extp->des7));
|
|
|
|
extp++;
|
|
|
|
}
|
|
|
|
} else if (desc_size == sizeof(struct dma_edesc)) {
|
|
|
|
struct dma_edesc *ep = (struct dma_edesc *)head;
|
|
|
|
|
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
dma_addr = dma_rx_phy + i * sizeof(*ep);
|
|
|
|
pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
|
|
|
|
i, &dma_addr,
|
|
|
|
le32_to_cpu(ep->des4), le32_to_cpu(ep->des5),
|
|
|
|
le32_to_cpu(ep->des6), le32_to_cpu(ep->des7),
|
|
|
|
le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1),
|
|
|
|
le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3));
|
|
|
|
ep++;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
pr_err("unsupported descriptor!");
|
2016-04-01 03:37:28 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
|
|
|
|
{
|
|
|
|
p->des0 = 0;
|
|
|
|
p->des1 = 0;
|
2016-11-14 10:58:05 -07:00
|
|
|
p->des2 = cpu_to_le32(mss);
|
|
|
|
p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
|
2016-04-01 03:37:28 -06:00
|
|
|
}
|
|
|
|
|
2018-05-18 07:56:08 -06:00
|
|
|
static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr)
|
|
|
|
{
|
|
|
|
*addr = le32_to_cpu(p->des0);
|
|
|
|
}
|
|
|
|
|
2018-05-18 07:56:00 -06:00
|
|
|
static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
|
|
|
|
{
|
2019-10-02 08:52:58 -06:00
|
|
|
p->des0 = cpu_to_le32(lower_32_bits(addr));
|
|
|
|
p->des1 = cpu_to_le32(upper_32_bits(addr));
|
2018-05-18 07:56:00 -06:00
|
|
|
}
|
|
|
|
|
2018-05-18 07:56:01 -06:00
|
|
|
static void dwmac4_clear(struct dma_desc *p)
|
|
|
|
{
|
|
|
|
p->des0 = 0;
|
|
|
|
p->des1 = 0;
|
|
|
|
p->des2 = 0;
|
|
|
|
p->des3 = 0;
|
|
|
|
}
|
|
|
|
|
2019-09-10 08:41:25 -06:00
|
|
|
static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
|
|
|
|
{
|
|
|
|
sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
|
|
|
|
|
|
|
|
p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
|
|
|
|
}
|
|
|
|
|
2019-07-03 10:59:10 -06:00
|
|
|
static int set_16kib_bfsize(int mtu)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (unlikely(mtu >= BUF_SIZE_8KiB))
|
|
|
|
ret = BUF_SIZE_16KiB;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-09-10 08:41:26 -06:00
|
|
|
static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
|
|
|
|
u32 inner_type)
|
|
|
|
{
|
|
|
|
p->des0 = 0;
|
|
|
|
p->des1 = 0;
|
|
|
|
p->des2 = 0;
|
|
|
|
p->des3 = 0;
|
|
|
|
|
|
|
|
/* Inner VLAN */
|
|
|
|
if (inner_type) {
|
|
|
|
u32 des = inner_tag << TDES2_IVT_SHIFT;
|
|
|
|
|
|
|
|
des &= TDES2_IVT_MASK;
|
|
|
|
p->des2 = cpu_to_le32(des);
|
|
|
|
|
|
|
|
des = inner_type << TDES3_IVTIR_SHIFT;
|
|
|
|
des &= TDES3_IVTIR_MASK;
|
|
|
|
p->des3 = cpu_to_le32(des | TDES3_IVLTV);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Outer VLAN */
|
|
|
|
p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);
|
|
|
|
p->des3 |= cpu_to_le32(TDES3_VLTV);
|
|
|
|
|
|
|
|
p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
|
|
|
|
{
|
|
|
|
type <<= TDES2_VLAN_TAG_SHIFT;
|
|
|
|
p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
|
|
|
|
}
|
|
|
|
|
2020-09-10 21:55:58 -06:00
|
|
|
static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
|
2019-11-11 07:42:35 -07:00
|
|
|
{
|
|
|
|
*len = le32_to_cpu(p->des2) & RDES2_HL;
|
|
|
|
}
|
|
|
|
|
2021-02-25 02:01:13 -07:00
|
|
|
static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)
|
2019-11-11 07:42:35 -07:00
|
|
|
{
|
|
|
|
p->des2 = cpu_to_le32(lower_32_bits(addr));
|
2021-02-25 02:01:13 -07:00
|
|
|
p->des3 = cpu_to_le32(upper_32_bits(addr));
|
|
|
|
|
|
|
|
if (buf2_valid)
|
|
|
|
p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR);
|
|
|
|
else
|
|
|
|
p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR);
|
2019-11-11 07:42:35 -07:00
|
|
|
}
|
|
|
|
|
2020-01-13 09:24:12 -07:00
|
|
|
static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
|
|
|
|
{
|
|
|
|
p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);
|
|
|
|
p->des5 = cpu_to_le32(nsec & TDES5_LT);
|
|
|
|
p->des6 = 0;
|
|
|
|
p->des7 = 0;
|
|
|
|
}
|
|
|
|
|
2016-04-01 03:37:28 -06:00
|
|
|
const struct stmmac_desc_ops dwmac4_desc_ops = {
|
|
|
|
.tx_status = dwmac4_wrback_get_tx_status,
|
|
|
|
.rx_status = dwmac4_wrback_get_rx_status,
|
|
|
|
.get_tx_len = dwmac4_rd_get_tx_len,
|
|
|
|
.get_tx_owner = dwmac4_get_tx_owner,
|
|
|
|
.set_tx_owner = dwmac4_set_tx_owner,
|
|
|
|
.set_rx_owner = dwmac4_set_rx_owner,
|
|
|
|
.get_tx_ls = dwmac4_get_tx_ls,
|
|
|
|
.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
|
|
|
|
.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
|
|
|
|
.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
|
2016-11-14 01:27:29 -07:00
|
|
|
.get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
|
|
|
|
.get_timestamp = dwmac4_get_timestamp,
|
2016-04-01 03:37:28 -06:00
|
|
|
.set_tx_ic = dwmac4_rd_set_tx_ic,
|
|
|
|
.prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
|
|
|
|
.prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
|
|
|
|
.release_tx_desc = dwmac4_release_tx_desc,
|
|
|
|
.init_rx_desc = dwmac4_rd_init_rx_desc,
|
|
|
|
.init_tx_desc = dwmac4_rd_init_tx_desc,
|
|
|
|
.display_ring = dwmac4_display_ring,
|
|
|
|
.set_mss = dwmac4_set_mss_ctxt,
|
2018-05-18 07:56:08 -06:00
|
|
|
.get_addr = dwmac4_get_addr,
|
2018-05-18 07:56:00 -06:00
|
|
|
.set_addr = dwmac4_set_addr,
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2018-05-18 07:56:01 -06:00
|
|
|
.clear = dwmac4_clear,
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2019-09-10 08:41:25 -06:00
|
|
|
.set_sarc = dwmac4_set_sarc,
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2019-09-10 08:41:26 -06:00
|
|
|
.set_vlan_tag = dwmac4_set_vlan_tag,
|
|
|
|
.set_vlan = dwmac4_set_vlan,
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2019-11-11 07:42:35 -07:00
|
|
|
.get_rx_header_len = dwmac4_get_rx_header_len,
|
|
|
|
.set_sec_addr = dwmac4_set_sec_addr,
|
2020-01-13 09:24:12 -07:00
|
|
|
.set_tbs = dwmac4_set_tbs,
|
2016-04-01 03:37:28 -06:00
|
|
|
};
|
|
|
|
|
2019-07-03 10:59:10 -06:00
|
|
|
const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
|
|
|
|
.set_16kib_bfsize = set_16kib_bfsize,
|
|
|
|
};
|