2006-06-26 05:56:40 -06:00
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/*
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* Shared support code for AMD K8 northbridges and derivates.
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* Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
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*/
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#include <linux/types.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2006-06-26 05:56:40 -06:00
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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2010-09-17 10:03:43 -06:00
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#include <asm/amd_nb.h>
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2006-06-26 05:56:40 -06:00
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static u32 *flush_words;
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2011-02-09 01:26:53 -07:00
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const struct pci_device_id amd_nb_misc_ids[] = {
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2008-09-02 05:13:40 -06:00
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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2011-01-19 10:22:11 -07:00
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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2006-06-26 05:56:40 -06:00
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{}
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};
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2010-10-29 09:14:31 -06:00
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EXPORT_SYMBOL(amd_nb_misc_ids);
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2006-06-26 05:56:40 -06:00
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2011-01-24 08:05:42 -07:00
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static struct pci_device_id amd_nb_link_ids[] = {
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2011-03-30 12:34:47 -06:00
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
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2011-01-24 08:05:42 -07:00
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{}
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};
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2011-01-10 09:20:23 -07:00
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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{ 0x00, 0x18, 0x20 },
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{ 0xff, 0x00, 0x20 },
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{ 0xfe, 0x00, 0x20 },
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{ }
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};
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2010-10-29 09:14:30 -06:00
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struct amd_northbridge_info amd_northbridges;
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EXPORT_SYMBOL(amd_northbridges);
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2006-06-26 05:56:40 -06:00
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2010-10-29 09:14:31 -06:00
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static struct pci_dev *next_northbridge(struct pci_dev *dev,
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2011-02-09 01:26:53 -07:00
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const struct pci_device_id *ids)
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2006-06-26 05:56:40 -06:00
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{
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do {
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dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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if (!dev)
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break;
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2010-10-29 09:14:31 -06:00
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} while (!pci_match_id(ids, dev));
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2006-06-26 05:56:40 -06:00
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return dev;
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}
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2010-10-29 09:14:31 -06:00
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int amd_cache_northbridges(void)
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2006-06-26 05:56:40 -06:00
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{
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2011-03-03 04:59:32 -07:00
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u16 i = 0;
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2010-10-29 09:14:31 -06:00
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struct amd_northbridge *nb;
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2011-01-24 08:05:42 -07:00
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struct pci_dev *misc, *link;
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2007-05-23 14:57:43 -06:00
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2010-10-29 09:14:31 -06:00
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if (amd_nb_num())
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2006-06-26 05:56:40 -06:00
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return 0;
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2010-10-29 09:14:31 -06:00
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misc = NULL;
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while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
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i++;
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2010-09-17 10:02:54 -06:00
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2010-10-29 09:14:31 -06:00
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if (i == 0)
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return 0;
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2006-06-26 05:56:40 -06:00
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2010-10-29 09:14:31 -06:00
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nb = kzalloc(i * sizeof(struct amd_northbridge), GFP_KERNEL);
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if (!nb)
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2006-06-26 05:56:40 -06:00
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return -ENOMEM;
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2010-10-29 09:14:31 -06:00
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amd_northbridges.nb = nb;
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amd_northbridges.num = i;
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2007-05-23 14:57:43 -06:00
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2011-01-24 08:05:42 -07:00
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link = misc = NULL;
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2010-10-29 09:14:31 -06:00
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for (i = 0; i != amd_nb_num(); i++) {
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, amd_nb_misc_ids);
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2011-01-24 08:05:42 -07:00
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node_to_amd_nb(i)->link = link =
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next_northbridge(link, amd_nb_link_ids);
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2010-10-29 09:14:31 -06:00
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}
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/* some CPU families (e.g. family 0x11) do not support GART */
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
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boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_GART;
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2006-06-26 05:56:40 -06:00
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2010-10-29 09:14:32 -06:00
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/*
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* Some CPU families support L3 Cache Index Disable. There are some
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* limitations because of E382 and E388 on family 0x10.
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*/
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if (boot_cpu_data.x86 == 0x10 &&
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boot_cpu_data.x86_model >= 0x8 &&
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(boot_cpu_data.x86_model > 0x9 ||
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boot_cpu_data.x86_mask >= 0x1))
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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2011-01-24 08:05:41 -07:00
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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2011-02-07 10:10:39 -07:00
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/* L3 cache partitioning is supported on family 0x15 */
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
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2006-06-26 05:56:40 -06:00
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return 0;
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}
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2010-10-29 09:14:31 -06:00
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EXPORT_SYMBOL_GPL(amd_cache_northbridges);
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2006-06-26 05:56:40 -06:00
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2011-03-03 04:59:32 -07:00
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/*
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* Ignores subdevice/subvendor but as far as I can figure out
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* they're useless anyways
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*/
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bool __init early_is_amd_nb(u32 device)
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2006-06-26 05:56:40 -06:00
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{
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2011-02-09 01:26:53 -07:00
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const struct pci_device_id *id;
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2006-06-26 05:56:40 -06:00
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u32 vendor = device & 0xffff;
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2011-02-09 01:26:53 -07:00
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2006-06-26 05:56:40 -06:00
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device >>= 16;
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2010-10-29 09:14:31 -06:00
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for (id = amd_nb_misc_ids; id->vendor; id++)
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2006-06-26 05:56:40 -06:00
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if (vendor == id->vendor && device == id->device)
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2011-03-03 04:59:32 -07:00
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return true;
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return false;
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2006-06-26 05:56:40 -06:00
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}
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2011-02-07 10:10:39 -07:00
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int amd_get_subcaches(int cpu)
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{
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struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
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unsigned int mask;
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int cuid = 0;
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if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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return 0;
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pci_read_config_dword(link, 0x1d4, &mask);
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#ifdef CONFIG_SMP
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cuid = cpu_data(cpu).compute_unit_id;
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#endif
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return (mask >> (4 * cuid)) & 0xf;
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}
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int amd_set_subcaches(int cpu, int mask)
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{
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static unsigned int reset, ban;
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struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
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unsigned int reg;
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int cuid = 0;
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if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
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return -EINVAL;
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/* if necessary, collect reset state of L3 partitioning and BAN mode */
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if (reset == 0) {
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pci_read_config_dword(nb->link, 0x1d4, &reset);
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pci_read_config_dword(nb->misc, 0x1b8, &ban);
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ban &= 0x180000;
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}
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/* deactivate BAN mode if any subcaches are to be disabled */
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if (mask != 0xf) {
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pci_read_config_dword(nb->misc, 0x1b8, ®);
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pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
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}
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#ifdef CONFIG_SMP
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cuid = cpu_data(cpu).compute_unit_id;
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#endif
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mask <<= 4 * cuid;
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mask |= (0xf ^ (1 << cuid)) << 26;
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pci_write_config_dword(nb->link, 0x1d4, mask);
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/* reset BAN mode if L3 partitioning returned to reset state */
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pci_read_config_dword(nb->link, 0x1d4, ®);
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if (reg == reset) {
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pci_read_config_dword(nb->misc, 0x1b8, ®);
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reg &= ~0x180000;
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pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
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}
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return 0;
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}
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2011-03-03 04:59:32 -07:00
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static int amd_cache_gart(void)
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2010-10-29 09:14:31 -06:00
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{
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2011-03-03 04:59:32 -07:00
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u16 i;
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2010-10-29 09:14:31 -06:00
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if (!amd_nb_has_feature(AMD_NB_GART))
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return 0;
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flush_words = kmalloc(amd_nb_num() * sizeof(u32), GFP_KERNEL);
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if (!flush_words) {
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amd_northbridges.flags &= ~AMD_NB_GART;
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return -ENOMEM;
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}
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for (i = 0; i != amd_nb_num(); i++)
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pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c,
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&flush_words[i]);
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return 0;
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}
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2010-10-29 09:14:30 -06:00
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void amd_flush_garts(void)
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2006-06-26 05:56:40 -06:00
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{
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int flushed, i;
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unsigned long flags;
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static DEFINE_SPINLOCK(gart_lock);
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2010-10-29 09:14:31 -06:00
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if (!amd_nb_has_feature(AMD_NB_GART))
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2010-09-17 10:02:54 -06:00
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return;
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|
2006-06-26 05:56:40 -06:00
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/* Avoid races between AGP and IOMMU. In theory it's not needed
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but I'm not sure if the hardware won't lose flush requests
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when another is pending. This whole thing is so expensive anyways
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that it doesn't matter to serialize more. -AK */
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spin_lock_irqsave(&gart_lock, flags);
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flushed = 0;
|
2010-10-29 09:14:31 -06:00
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for (i = 0; i < amd_nb_num(); i++) {
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pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
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flush_words[i] | 1);
|
2006-06-26 05:56:40 -06:00
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flushed++;
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}
|
2010-10-29 09:14:31 -06:00
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for (i = 0; i < amd_nb_num(); i++) {
|
2006-06-26 05:56:40 -06:00
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u32 w;
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/* Make sure the hardware actually executed the flush*/
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for (;;) {
|
2010-10-29 09:14:31 -06:00
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pci_read_config_dword(node_to_amd_nb(i)->misc,
|
2006-06-26 05:56:40 -06:00
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0x9c, &w);
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if (!(w & 1))
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break;
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cpu_relax();
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}
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}
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spin_unlock_irqrestore(&gart_lock, flags);
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|
|
if (!flushed)
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printk("nothing to flush?\n");
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|
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}
|
2010-10-29 09:14:30 -06:00
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EXPORT_SYMBOL_GPL(amd_flush_garts);
|
2006-06-26 05:56:40 -06:00
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|
2010-10-29 09:14:30 -06:00
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static __init int init_amd_nbs(void)
|
2010-03-12 07:43:03 -07:00
|
|
|
{
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int err = 0;
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|
2010-10-29 09:14:31 -06:00
|
|
|
err = amd_cache_northbridges();
|
2010-03-12 07:43:03 -07:00
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|
if (err < 0)
|
2010-10-29 09:14:30 -06:00
|
|
|
printk(KERN_NOTICE "AMD NB: Cannot enumerate AMD northbridges.\n");
|
2010-03-12 07:43:03 -07:00
|
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|
2010-10-29 09:14:31 -06:00
|
|
|
if (amd_cache_gart() < 0)
|
|
|
|
printk(KERN_NOTICE "AMD NB: Cannot initialize GART flush words, "
|
|
|
|
"GART support disabled.\n");
|
|
|
|
|
2010-03-12 07:43:03 -07:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* This has to go after the PCI subsystem */
|
2010-10-29 09:14:30 -06:00
|
|
|
fs_initcall(init_amd_nbs);
|