2015-05-10 23:30:56 -06:00
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#ifndef WILC_WLAN_H
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#define WILC_WLAN_H
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#define ISWILC1000(id) (((id & 0xfffff000) == 0x100000) ? 1 : 0)
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/********************************************
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*
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* Mac eth header length
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*
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********************************************/
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#define DRIVER_HANDLER_SIZE 4
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#define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */
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#define SUB_MSDU_HEADER_LENGTH 14
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#define SNAP_HDR_LEN 8
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#define ETHERNET_HDR_LEN 14
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#define WORD_ALIGNMENT_PAD 0
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#define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + SUB_MSDU_HEADER_LENGTH + \
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SNAP_HDR_LEN - ETHERNET_HDR_LEN + WORD_ALIGNMENT_PAD)
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#define HOST_HDR_OFFSET 4
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#define ETHERNET_HDR_LEN 14
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#define IP_HDR_LEN 20
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#define IP_HDR_OFFSET ETHERNET_HDR_LEN
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#define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
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#define UDP_HDR_LEN 8
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#define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
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#define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
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#define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
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ETH_CONFIG_PKT_HDR_LEN)
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/********************************************
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*
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* Endian Conversion
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*
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********************************************/
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#define BYTE_SWAP(val) ((((val) & 0x000000FF) << 24) + \
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(((val) & 0x0000FF00) << 8) + \
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(((val) & 0x00FF0000) >> 8) + \
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(((val) & 0xFF000000) >> 24))
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/********************************************
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*
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* Register Defines
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*
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********************************************/
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#define WILC_PERIPH_REG_BASE 0x1000
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#define WILC_CHANGING_VIR_IF (0x108c)
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#define WILC_CHIPID (WILC_PERIPH_REG_BASE)
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#define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
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#define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
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#define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
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#define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
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#define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
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#define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
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#define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
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#define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
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#define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
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#define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428)
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#define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
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#define WILC_INTR_ENABLE (WILC_INTR_REG_BASE)
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#define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
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#define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
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#define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
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#define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
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#define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
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#define WILC_VMM_TBL_SIZE 64
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#define WILC_VMM_TX_TBL_BASE (0x150400)
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#define WILC_VMM_RX_TBL_BASE (0x150500)
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#define WILC_VMM_BASE 0x150000
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#define WILC_VMM_CORE_CTL (WILC_VMM_BASE)
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#define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
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#define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
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#define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
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#define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
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#define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
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#define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
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#define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
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#define WILC_SPI_REG_BASE 0xe800
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#define WILC_SPI_CTL (WILC_SPI_REG_BASE)
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#define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
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#define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
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#define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
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#define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
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#define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
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#define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
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#define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
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#define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - WILC_SPI_REG_BASE)
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#define WILC_AHB_DATA_MEM_BASE 0x30000
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#define WILC_AHB_SHARE_MEM_BASE 0xd0000
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2015-09-20 00:51:19 -06:00
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#define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
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#define WILC_VMM_TBL_RX_SHADOW_SIZE (256)
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2015-05-10 23:30:56 -06:00
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#define WILC_GP_REG_0 0x149c
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#define WILC_GP_REG_1 0x14a0
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#define rHAVE_SDIO_IRQ_GPIO_BIT (0)
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#define rHAVE_USE_PMU_BIT (1)
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#define rHAVE_SLEEP_CLK_SRC_RTC_BIT (2)
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#define rHAVE_SLEEP_CLK_SRC_XO_BIT (3)
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#define rHAVE_EXT_PA_INV_TX_RX_BIT (4)
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#define rHAVE_LEGACY_RF_SETTINGS_BIT (5)
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#define rHAVE_XTAL_24_BIT (6)
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#define rHAVE_DISABLE_WILC_UART_BIT (7)
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#define WILC_HAVE_SDIO_IRQ_GPIO (1 << rHAVE_SDIO_IRQ_GPIO_BIT)
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#define WILC_HAVE_USE_PMU (1 << rHAVE_USE_PMU_BIT)
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#define WILC_HAVE_SLEEP_CLK_SRC_RTC (1 << rHAVE_SLEEP_CLK_SRC_RTC_BIT)
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#define WILC_HAVE_SLEEP_CLK_SRC_XO (1 << rHAVE_SLEEP_CLK_SRC_XO_BIT)
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#define WILC_HAVE_EXT_PA_INV_TX_RX (1 << rHAVE_EXT_PA_INV_TX_RX_BIT)
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#define WILC_HAVE_LEGACY_RF_SETTINGS (1 << rHAVE_LEGACY_RF_SETTINGS_BIT)
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#define WILC_HAVE_XTAL_24 (1 << rHAVE_XTAL_24_BIT)
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#define WILC_HAVE_DISABLE_WILC_UART (1 << rHAVE_DISABLE_WILC_UART_BIT)
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/********************************************
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*
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* Wlan Defines
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*
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********************************************/
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#define WILC_CFG_PKT 1
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#define WILC_NET_PKT 0
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#define WILC_MGMT_PKT 2
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#define WILC_CFG_SET 1
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#define WILC_CFG_QUERY 0
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#define WILC_CFG_RSP 1
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#define WILC_CFG_RSP_STATUS 2
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#define WILC_CFG_RSP_SCAN 3
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#ifdef WILC_SDIO
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#define WILC_PLL_TO 4
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#else
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#define WILC_PLL_TO 2
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#endif
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2015-09-29 13:15:49 -06:00
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#define ABORT_INT BIT(31)
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2015-05-10 23:30:56 -06:00
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/*******************************************/
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/* E0 and later Interrupt flags. */
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/*******************************************/
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/*******************************************/
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/* E0 and later Interrupt flags. */
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/* IRQ Status word */
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/* 15:0 = DMA count in words. */
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/* 16: INT0 flag */
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/* 17: INT1 flag */
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/* 18: INT2 flag */
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/* 19: INT3 flag */
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/* 20: INT4 flag */
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/* 21: INT5 flag */
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/*******************************************/
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#define IRG_FLAGS_OFFSET 16
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#define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1)
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#define INT_0 (1 << (IRG_FLAGS_OFFSET))
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#define INT_1 (1 << (IRG_FLAGS_OFFSET + 1))
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#define INT_2 (1 << (IRG_FLAGS_OFFSET + 2))
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#define INT_3 (1 << (IRG_FLAGS_OFFSET + 3))
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#define INT_4 (1 << (IRG_FLAGS_OFFSET + 4))
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#define INT_5 (1 << (IRG_FLAGS_OFFSET + 5))
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#define MAX_NUM_INT (6)
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/*******************************************/
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/* E0 and later Interrupt flags. */
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/* IRQ Clear word */
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/* 0: Clear INT0 */
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/* 1: Clear INT1 */
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/* 2: Clear INT2 */
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/* 3: Clear INT3 */
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/* 4: Clear INT4 */
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/* 5: Clear INT5 */
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/* 6: Select VMM table 1 */
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/* 7: Select VMM table 2 */
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/* 8: Enable VMM */
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/*******************************************/
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2015-09-29 13:15:49 -06:00
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#define CLR_INT0 BIT(0)
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#define CLR_INT1 BIT(1)
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#define CLR_INT2 BIT(2)
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#define CLR_INT3 BIT(3)
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#define CLR_INT4 BIT(4)
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#define CLR_INT5 BIT(5)
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#define SEL_VMM_TBL0 BIT(6)
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#define SEL_VMM_TBL1 BIT(7)
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#define EN_VMM BIT(8)
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2015-05-10 23:30:56 -06:00
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#define DATA_INT_EXT INT_0
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#define PLL_INT_EXT INT_1
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#define SLEEP_INT_EXT INT_2
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#define ALL_INT_EXT (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT)
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#define NUM_INT_EXT (3)
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#define DATA_INT_CLR CLR_INT0
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#define PLL_INT_CLR CLR_INT1
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#define SLEEP_INT_CLR CLR_INT2
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#define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
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#define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
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/*time for expiring the semaphores of cfg packets*/
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#define CFG_PKTS_TIMEOUT 2000
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/********************************************
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*
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* Debug Type
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*
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********************************************/
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2015-09-14 23:06:16 -06:00
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typedef void (*wilc_debug_func)(u32, char *, ...);
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2015-05-10 23:30:56 -06:00
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/********************************************
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*
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* Tx/Rx Queue Structure
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*
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********************************************/
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struct txq_entry_t {
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struct txq_entry_t *next;
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struct txq_entry_t *prev;
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int type;
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int tcp_PendingAck_index;
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2015-09-14 23:06:14 -06:00
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u8 *buffer;
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2015-05-10 23:30:56 -06:00
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int buffer_size;
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void *priv;
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int status;
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void (*tx_complete_func)(void *, int);
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};
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struct rxq_entry_t {
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struct rxq_entry_t *next;
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2015-09-14 23:06:14 -06:00
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u8 *buffer;
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2015-05-10 23:30:56 -06:00
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int buffer_size;
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};
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/********************************************
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*
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* Host IF Structure
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*
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********************************************/
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typedef struct {
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int (*hif_init)(wilc_wlan_inp_t *, wilc_debug_func);
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int (*hif_deinit)(void *);
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2015-09-14 23:06:16 -06:00
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int (*hif_read_reg)(u32, u32 *);
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int (*hif_write_reg)(u32, u32);
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int (*hif_block_rx)(u32, u8 *, u32);
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int (*hif_block_tx)(u32, u8 *, u32);
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2015-05-10 23:30:56 -06:00
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int (*hif_sync)(void);
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int (*hif_clear_int)(void);
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2015-09-14 23:06:16 -06:00
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int (*hif_read_int)(u32 *);
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int (*hif_clear_int_ext)(u32);
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int (*hif_read_size)(u32 *);
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int (*hif_block_tx_ext)(u32, u8 *, u32);
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int (*hif_block_rx_ext)(u32, u8 *, u32);
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2015-05-10 23:30:56 -06:00
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int (*hif_sync_ext)(int);
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void (*hif_set_max_bus_speed)(void);
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void (*hif_set_default_bus_speed)(void);
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} wilc_hif_func_t;
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/********************************************
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*
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* Configuration Structure
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*
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********************************************/
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#define MAX_CFG_FRAME_SIZE 1468
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typedef struct {
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2015-09-14 23:06:14 -06:00
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u8 ether_header[14];
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u8 ip_header[20];
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u8 udp_header[8];
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u8 wid_header[8];
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u8 frame[MAX_CFG_FRAME_SIZE];
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2015-05-10 23:30:56 -06:00
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} wilc_cfg_frame_t;
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typedef struct {
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2015-09-14 23:06:16 -06:00
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int (*wlan_tx)(u8 *, u32, wilc_tx_complete_func_t);
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2015-05-10 23:30:56 -06:00
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} wilc_wlan_cfg_func_t;
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typedef struct {
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int type;
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2015-09-14 23:06:16 -06:00
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u32 seq_no;
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2015-05-10 23:30:56 -06:00
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} wilc_cfg_rsp_t;
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typedef struct {
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2015-09-14 23:06:16 -06:00
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int (*cfg_wid_set)(u8 *, u32, u16, u8 *, int);
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int (*cfg_wid_get)(u8 *, u32, u16);
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int (*cfg_wid_get_val)(u16, u8 *, u32);
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2015-09-14 23:06:14 -06:00
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int (*rx_indicate)(u8 *, int, wilc_cfg_rsp_t *);
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2015-05-10 23:30:56 -06:00
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int (*cfg_init)(wilc_debug_func);
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} wilc_cfg_func_t;
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2015-10-01 01:03:32 -06:00
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int wilc_wlan_firmware_download(const u8 *buffer, u32 buffer_size);
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2015-10-01 01:03:33 -06:00
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int wilc_wlan_start(void);
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2015-10-01 01:03:34 -06:00
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int wilc_wlan_stop(void);
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2015-10-01 01:03:35 -06:00
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int wilc_wlan_txq_add_net_pkt(void *priv, u8 *buffer, u32 buffer_size,
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wilc_tx_complete_func_t func);
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2015-10-01 01:03:36 -06:00
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int wilc_wlan_handle_txq(u32 *pu32TxqCount);
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2015-10-01 01:03:37 -06:00
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void wilc_handle_isr(void);
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2015-10-01 01:03:38 -06:00
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void wilc_wlan_cleanup(void);
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2015-10-01 01:03:40 -06:00
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int wilc_wlan_cfg_set(int start, u32 wid, u8 *buffer, u32 buffer_size,
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int commit, u32 drvHandler);
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2015-10-01 01:03:41 -06:00
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int wilc_wlan_cfg_get(int start, u32 wid, int commit, u32 drvHandler);
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2015-05-10 23:30:56 -06:00
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#endif
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