License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 08:07:57 -06:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2007-08-16 02:47:25 -06:00
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/* NG2memcpy.S: Niagara-2 optimized memcpy.
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*
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* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
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*/
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#ifdef __KERNEL__
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2016-10-24 21:46:44 -06:00
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#include <linux/linkage.h>
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2007-08-16 02:47:25 -06:00
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#include <asm/visasm.h>
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#include <asm/asi.h>
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#define GLOBAL_SPARE %g7
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#else
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#define ASI_PNF 0x82
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#define ASI_BLK_P 0xf0
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#define ASI_BLK_INIT_QUAD_LDD_P 0xe2
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#define FPRS_FEF 0x04
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#ifdef MEMCPY_DEBUG
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#define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
|
2012-09-27 02:06:43 -06:00
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clr %g1; clr %g2; clr %g3; clr %g5; subcc %g0, %g0, %g0;
|
2007-08-16 02:47:25 -06:00
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#define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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#else
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#define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
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#define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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#endif
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#define GLOBAL_SPARE %g5
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#endif
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#ifndef STORE_ASI
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#ifndef SIMULATE_NIAGARA_ON_NON_NIAGARA
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#define STORE_ASI ASI_BLK_INIT_QUAD_LDD_P
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#else
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#define STORE_ASI 0x80 /* ASI_P */
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#endif
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#endif
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#ifndef EX_LD
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2016-10-24 21:46:44 -06:00
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#define EX_LD(x,y) x
|
2007-08-16 02:47:25 -06:00
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#endif
|
sparc64: fix FP corruption in user copy functions
Short story: Exception handlers used by some copy_to_user() and
copy_from_user() functions do not diligently clean up floating point
register usage, and this can result in a user process seeing invalid
values in floating point registers. This sometimes makes the process
fail.
Long story: Several cpu-specific (NG4, NG2, U1, U3) memcpy functions
use floating point registers and VIS alignaddr/faligndata to
accelerate data copying when source and dest addresses don't align
well. Linux uses a lazy scheme for saving floating point registers; It
is not done upon entering the kernel since it's a very expensive
operation. Rather, it is done only when needed. If the kernel ends up
not using FP regs during the course of some trap or system call, then
it can return to user space without saving or restoring them.
The various memcpy functions begin their FP code with VISEntry (or a
variation thereof), which saves the FP regs. They conclude their FP
code with VISExit (or a variation) which essentially marks the FP regs
"clean", ie, they contain no unsaved values. fprs.FPRS_FEF is turned
off so that a lazy restore will be triggered when/if the user process
accesses floating point regs again.
The bug is that the user copy variants of memcpy, copy_from_user() and
copy_to_user(), employ an exception handling mechanism to detect faults
when accessing user space addresses, and when this handler is invoked,
an immediate return from the function is forced, and VISExit is not
executed, thus leaving the fprs register in an indeterminate state,
but often with fprs.FPRS_FEF set and one or more dirty bits. This
results in a return to user space with invalid values in the FP regs,
and since fprs.FPRS_FEF is on, no lazy restore occurs.
This bug affects copy_to_user() and copy_from_user() for NG4, NG2,
U3, and U1. All are fixed by using a new exception handler for those
loads and stores that are done during the time between VISEnter and
VISExit.
n.b. In NG4memcpy, the problematic code can be triggered by a copy
size greater than 128 bytes and an unaligned source address. This bug
is known to be the cause of random user process memory corruptions
while perf is running with the callgraph option (ie, perf record -g).
This occurs because perf uses copy_from_user() to read user stacks,
and may fault when it follows a stack frame pointer off to an
invalid page. Validation checks on the stack address just obscure
the underlying problem.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-22 23:24:49 -07:00
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|
|
#ifndef EX_LD_FP
|
2016-10-24 21:46:44 -06:00
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#define EX_LD_FP(x,y) x
|
sparc64: fix FP corruption in user copy functions
Short story: Exception handlers used by some copy_to_user() and
copy_from_user() functions do not diligently clean up floating point
register usage, and this can result in a user process seeing invalid
values in floating point registers. This sometimes makes the process
fail.
Long story: Several cpu-specific (NG4, NG2, U1, U3) memcpy functions
use floating point registers and VIS alignaddr/faligndata to
accelerate data copying when source and dest addresses don't align
well. Linux uses a lazy scheme for saving floating point registers; It
is not done upon entering the kernel since it's a very expensive
operation. Rather, it is done only when needed. If the kernel ends up
not using FP regs during the course of some trap or system call, then
it can return to user space without saving or restoring them.
The various memcpy functions begin their FP code with VISEntry (or a
variation thereof), which saves the FP regs. They conclude their FP
code with VISExit (or a variation) which essentially marks the FP regs
"clean", ie, they contain no unsaved values. fprs.FPRS_FEF is turned
off so that a lazy restore will be triggered when/if the user process
accesses floating point regs again.
The bug is that the user copy variants of memcpy, copy_from_user() and
copy_to_user(), employ an exception handling mechanism to detect faults
when accessing user space addresses, and when this handler is invoked,
an immediate return from the function is forced, and VISExit is not
executed, thus leaving the fprs register in an indeterminate state,
but often with fprs.FPRS_FEF set and one or more dirty bits. This
results in a return to user space with invalid values in the FP regs,
and since fprs.FPRS_FEF is on, no lazy restore occurs.
This bug affects copy_to_user() and copy_from_user() for NG4, NG2,
U3, and U1. All are fixed by using a new exception handler for those
loads and stores that are done during the time between VISEnter and
VISExit.
n.b. In NG4memcpy, the problematic code can be triggered by a copy
size greater than 128 bytes and an unaligned source address. This bug
is known to be the cause of random user process memory corruptions
while perf is running with the callgraph option (ie, perf record -g).
This occurs because perf uses copy_from_user() to read user stacks,
and may fault when it follows a stack frame pointer off to an
invalid page. Validation checks on the stack address just obscure
the underlying problem.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-22 23:24:49 -07:00
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#endif
|
2007-08-16 02:47:25 -06:00
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|
#ifndef EX_ST
|
2016-10-24 21:46:44 -06:00
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#define EX_ST(x,y) x
|
2007-08-16 02:47:25 -06:00
|
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|
#endif
|
sparc64: fix FP corruption in user copy functions
Short story: Exception handlers used by some copy_to_user() and
copy_from_user() functions do not diligently clean up floating point
register usage, and this can result in a user process seeing invalid
values in floating point registers. This sometimes makes the process
fail.
Long story: Several cpu-specific (NG4, NG2, U1, U3) memcpy functions
use floating point registers and VIS alignaddr/faligndata to
accelerate data copying when source and dest addresses don't align
well. Linux uses a lazy scheme for saving floating point registers; It
is not done upon entering the kernel since it's a very expensive
operation. Rather, it is done only when needed. If the kernel ends up
not using FP regs during the course of some trap or system call, then
it can return to user space without saving or restoring them.
The various memcpy functions begin their FP code with VISEntry (or a
variation thereof), which saves the FP regs. They conclude their FP
code with VISExit (or a variation) which essentially marks the FP regs
"clean", ie, they contain no unsaved values. fprs.FPRS_FEF is turned
off so that a lazy restore will be triggered when/if the user process
accesses floating point regs again.
The bug is that the user copy variants of memcpy, copy_from_user() and
copy_to_user(), employ an exception handling mechanism to detect faults
when accessing user space addresses, and when this handler is invoked,
an immediate return from the function is forced, and VISExit is not
executed, thus leaving the fprs register in an indeterminate state,
but often with fprs.FPRS_FEF set and one or more dirty bits. This
results in a return to user space with invalid values in the FP regs,
and since fprs.FPRS_FEF is on, no lazy restore occurs.
This bug affects copy_to_user() and copy_from_user() for NG4, NG2,
U3, and U1. All are fixed by using a new exception handler for those
loads and stores that are done during the time between VISEnter and
VISExit.
n.b. In NG4memcpy, the problematic code can be triggered by a copy
size greater than 128 bytes and an unaligned source address. This bug
is known to be the cause of random user process memory corruptions
while perf is running with the callgraph option (ie, perf record -g).
This occurs because perf uses copy_from_user() to read user stacks,
and may fault when it follows a stack frame pointer off to an
invalid page. Validation checks on the stack address just obscure
the underlying problem.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-22 23:24:49 -07:00
|
|
|
#ifndef EX_ST_FP
|
2016-10-24 21:46:44 -06:00
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#define EX_ST_FP(x,y) x
|
2007-08-16 02:47:25 -06:00
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#endif
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#ifndef LOAD
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#define LOAD(type,addr,dest) type [addr], dest
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#endif
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#ifndef LOAD_BLK
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#define LOAD_BLK(addr,dest) ldda [addr] ASI_BLK_P, dest
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#endif
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#ifndef STORE
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#ifndef MEMCPY_DEBUG
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#define STORE(type,src,addr) type src, [addr]
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#else
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#define STORE(type,src,addr) type##a src, [addr] 0x80
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#endif
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#endif
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#ifndef STORE_BLK
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#define STORE_BLK(src,addr) stda src, [addr] ASI_BLK_P
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#endif
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#ifndef STORE_INIT
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#define STORE_INIT(src,addr) stxa src, [addr] STORE_ASI
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#endif
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#ifndef FUNC_NAME
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#define FUNC_NAME NG2memcpy
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#endif
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#ifndef PREAMBLE
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#define PREAMBLE
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#endif
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#ifndef XCC
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#define XCC xcc
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#endif
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#define FREG_FROB(x0, x1, x2, x3, x4, x5, x6, x7, x8) \
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faligndata %x0, %x1, %f0; \
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faligndata %x1, %x2, %f2; \
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faligndata %x2, %x3, %f4; \
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faligndata %x3, %x4, %f6; \
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faligndata %x4, %x5, %f8; \
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faligndata %x5, %x6, %f10; \
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faligndata %x6, %x7, %f12; \
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faligndata %x7, %x8, %f14;
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#define FREG_MOVE_1(x0) \
|
2012-06-27 02:25:23 -06:00
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fsrc2 %x0, %f0;
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2007-08-16 02:47:25 -06:00
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#define FREG_MOVE_2(x0, x1) \
|
2012-06-27 02:25:23 -06:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2;
|
2007-08-16 02:47:25 -06:00
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#define FREG_MOVE_3(x0, x1, x2) \
|
2012-06-27 02:25:23 -06:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4;
|
2007-08-16 02:47:25 -06:00
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#define FREG_MOVE_4(x0, x1, x2, x3) \
|
2012-06-27 02:25:23 -06:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6;
|
2007-08-16 02:47:25 -06:00
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#define FREG_MOVE_5(x0, x1, x2, x3, x4) \
|
2012-06-27 02:25:23 -06:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6; \
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fsrc2 %x4, %f8;
|
2007-08-16 02:47:25 -06:00
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#define FREG_MOVE_6(x0, x1, x2, x3, x4, x5) \
|
2012-06-27 02:25:23 -06:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6; \
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fsrc2 %x4, %f8; \
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fsrc2 %x5, %f10;
|
2007-08-16 02:47:25 -06:00
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#define FREG_MOVE_7(x0, x1, x2, x3, x4, x5, x6) \
|
2012-06-27 02:25:23 -06:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6; \
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fsrc2 %x4, %f8; \
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fsrc2 %x5, %f10; \
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fsrc2 %x6, %f12;
|
2007-08-16 02:47:25 -06:00
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#define FREG_MOVE_8(x0, x1, x2, x3, x4, x5, x6, x7) \
|
2012-06-27 02:25:23 -06:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6; \
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fsrc2 %x4, %f8; \
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fsrc2 %x5, %f10; \
|
|
|
|
|
fsrc2 %x6, %f12; \
|
|
|
|
|
fsrc2 %x7, %f14;
|
2007-08-16 02:47:25 -06:00
|
|
|
#define FREG_LOAD_1(base, x0) \
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
#define FREG_LOAD_2(base, x0, x1) \
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1);
|
2007-08-16 02:47:25 -06:00
|
|
|
#define FREG_LOAD_3(base, x0, x1, x2) \
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1);
|
2007-08-16 02:47:25 -06:00
|
|
|
#define FREG_LOAD_4(base, x0, x1, x2, x3) \
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x18, %x3), NG2_retl_o2_plus_g1);
|
2007-08-16 02:47:25 -06:00
|
|
|
#define FREG_LOAD_5(base, x0, x1, x2, x3, x4) \
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x18, %x3), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x20, %x4), NG2_retl_o2_plus_g1);
|
2007-08-16 02:47:25 -06:00
|
|
|
#define FREG_LOAD_6(base, x0, x1, x2, x3, x4, x5) \
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x18, %x3), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x20, %x4), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x28, %x5), NG2_retl_o2_plus_g1);
|
2007-08-16 02:47:25 -06:00
|
|
|
#define FREG_LOAD_7(base, x0, x1, x2, x3, x4, x5, x6) \
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x18, %x3), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x20, %x4), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x28, %x5), NG2_retl_o2_plus_g1); \
|
|
|
|
|
EX_LD_FP(LOAD(ldd, base + 0x30, %x6), NG2_retl_o2_plus_g1);
|
2007-08-16 02:47:25 -06:00
|
|
|
|
|
|
|
|
.register %g2,#scratch
|
|
|
|
|
.register %g3,#scratch
|
|
|
|
|
|
|
|
|
|
.text
|
2016-10-24 21:46:44 -06:00
|
|
|
#ifndef EX_RETVAL
|
|
|
|
|
#define EX_RETVAL(x) x
|
|
|
|
|
__restore_fp:
|
|
|
|
|
VISExitHalf
|
|
|
|
|
__restore_asi:
|
|
|
|
|
retl
|
|
|
|
|
wr %g0, ASI_AIUS, %asi
|
|
|
|
|
ENTRY(NG2_retl_o2)
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
mov %o2, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_1)
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, 1, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_1)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_4)
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, 4, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_4)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_8)
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, 8, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_8)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_o4_plus_1)
|
|
|
|
|
add %o4, 1, %o4
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, %o4, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_o4_plus_1)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_o4_plus_8)
|
|
|
|
|
add %o4, 8, %o4
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, %o4, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_o4_plus_8)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_o4_plus_16)
|
|
|
|
|
add %o4, 16, %o4
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, %o4, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_o4_plus_16)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_g1_fp)
|
|
|
|
|
ba,pt %xcc, __restore_fp
|
|
|
|
|
add %o2, %g1, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_g1_fp)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_g1_plus_64_fp)
|
|
|
|
|
add %g1, 64, %g1
|
|
|
|
|
ba,pt %xcc, __restore_fp
|
|
|
|
|
add %o2, %g1, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_g1_plus_64_fp)
|
|
|
|
|
ENTRY(NG2_retl_o2_plus_g1_plus_1)
|
|
|
|
|
add %g1, 1, %g1
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, %g1, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_plus_g1_plus_1)
|
|
|
|
|
ENTRY(NG2_retl_o2_and_7_plus_o4)
|
|
|
|
|
and %o2, 7, %o2
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, %o4, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_and_7_plus_o4)
|
|
|
|
|
ENTRY(NG2_retl_o2_and_7_plus_o4_plus_8)
|
|
|
|
|
and %o2, 7, %o2
|
|
|
|
|
add %o4, 8, %o4
|
|
|
|
|
ba,pt %xcc, __restore_asi
|
|
|
|
|
add %o2, %o4, %o0
|
|
|
|
|
ENDPROC(NG2_retl_o2_and_7_plus_o4_plus_8)
|
|
|
|
|
#endif
|
|
|
|
|
|
2007-08-16 02:47:25 -06:00
|
|
|
.align 64
|
|
|
|
|
|
|
|
|
|
.globl FUNC_NAME
|
|
|
|
|
.type FUNC_NAME,#function
|
|
|
|
|
FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
|
|
|
|
|
srlx %o2, 31, %g2
|
|
|
|
|
cmp %g2, 0
|
|
|
|
|
tne %xcc, 5
|
|
|
|
|
PREAMBLE
|
2012-09-27 02:06:43 -06:00
|
|
|
mov %o0, %o3
|
2007-08-16 02:47:25 -06:00
|
|
|
cmp %o2, 0
|
|
|
|
|
be,pn %XCC, 85f
|
2012-09-27 02:06:43 -06:00
|
|
|
or %o0, %o1, GLOBAL_SPARE
|
2007-08-16 02:47:25 -06:00
|
|
|
cmp %o2, 16
|
|
|
|
|
blu,a,pn %XCC, 80f
|
2012-09-27 02:06:43 -06:00
|
|
|
or GLOBAL_SPARE, %o2, GLOBAL_SPARE
|
2007-08-16 02:47:25 -06:00
|
|
|
|
|
|
|
|
/* 2 blocks (128 bytes) is the minimum we can do the block
|
|
|
|
|
* copy with. We need to ensure that we'll iterate at least
|
|
|
|
|
* once in the block copy loop. At worst we'll need to align
|
|
|
|
|
* the destination to a 64-byte boundary which can chew up
|
|
|
|
|
* to (64 - 1) bytes from the length before we perform the
|
|
|
|
|
* block copy loop.
|
|
|
|
|
*
|
|
|
|
|
* However, the cut-off point, performance wise, is around
|
|
|
|
|
* 4 64-byte blocks.
|
|
|
|
|
*/
|
|
|
|
|
cmp %o2, (4 * 64)
|
|
|
|
|
blu,pt %XCC, 75f
|
2012-09-27 02:06:43 -06:00
|
|
|
andcc GLOBAL_SPARE, 0x7, %g0
|
2007-08-16 02:47:25 -06:00
|
|
|
|
|
|
|
|
/* %o0: dst
|
|
|
|
|
* %o1: src
|
|
|
|
|
* %o2: len (known to be >= 128)
|
|
|
|
|
*
|
|
|
|
|
* The block copy loops can use %o4, %g2, %g3 as
|
|
|
|
|
* temporaries while copying the data. %o5 must
|
|
|
|
|
* be preserved between VISEntryHalf and VISExitHalf
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
LOAD(prefetch, %o1 + 0x000, #one_read)
|
|
|
|
|
LOAD(prefetch, %o1 + 0x040, #one_read)
|
|
|
|
|
LOAD(prefetch, %o1 + 0x080, #one_read)
|
|
|
|
|
|
|
|
|
|
/* Align destination on 64-byte boundary. */
|
|
|
|
|
andcc %o0, (64 - 1), %o4
|
|
|
|
|
be,pt %XCC, 2f
|
|
|
|
|
sub %o4, 64, %o4
|
|
|
|
|
sub %g0, %o4, %o4 ! bytes to align dst
|
|
|
|
|
sub %o2, %o4, %o2
|
|
|
|
|
1: subcc %o4, 1, %o4
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD(LOAD(ldub, %o1, %g1), NG2_retl_o2_plus_o4_plus_1)
|
|
|
|
|
EX_ST(STORE(stb, %g1, %o0), NG2_retl_o2_plus_o4_plus_1)
|
2007-08-16 02:47:25 -06:00
|
|
|
add %o1, 1, %o1
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
add %o0, 1, %o0
|
|
|
|
|
|
|
|
|
|
2:
|
|
|
|
|
/* Clobbers o5/g1/g2/g3/g7/icc/xcc. We must preserve
|
|
|
|
|
* o5 from here until we hit VISExitHalf.
|
|
|
|
|
*/
|
|
|
|
|
VISEntryHalf
|
|
|
|
|
|
2014-05-17 12:28:05 -06:00
|
|
|
membar #Sync
|
2007-08-16 02:47:25 -06:00
|
|
|
alignaddr %o1, %g0, %g0
|
|
|
|
|
|
|
|
|
|
add %o1, (64 - 1), %o4
|
|
|
|
|
andn %o4, (64 - 1), %o4
|
|
|
|
|
andn %o2, (64 - 1), %g1
|
|
|
|
|
sub %o2, %g1, %o2
|
|
|
|
|
|
|
|
|
|
and %o1, (64 - 1), %g2
|
|
|
|
|
add %o1, %g1, %o1
|
|
|
|
|
sub %o0, %o4, %g3
|
|
|
|
|
brz,pt %g2, 190f
|
|
|
|
|
cmp %g2, 32
|
|
|
|
|
blu,a 5f
|
|
|
|
|
cmp %g2, 16
|
|
|
|
|
cmp %g2, 48
|
|
|
|
|
blu,a 4f
|
|
|
|
|
cmp %g2, 40
|
|
|
|
|
cmp %g2, 56
|
|
|
|
|
blu 170f
|
|
|
|
|
nop
|
|
|
|
|
ba,a,pt %xcc, 180f
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
|
|
|
nop
|
2007-08-16 02:47:25 -06:00
|
|
|
|
|
|
|
|
4: /* 32 <= low bits < 48 */
|
|
|
|
|
blu 150f
|
|
|
|
|
nop
|
|
|
|
|
ba,a,pt %xcc, 160f
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
|
|
|
nop
|
2007-08-16 02:47:25 -06:00
|
|
|
5: /* 0 < low bits < 32 */
|
|
|
|
|
blu,a 6f
|
|
|
|
|
cmp %g2, 8
|
|
|
|
|
cmp %g2, 24
|
|
|
|
|
blu 130f
|
|
|
|
|
nop
|
|
|
|
|
ba,a,pt %xcc, 140f
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
|
|
|
nop
|
2007-08-16 02:47:25 -06:00
|
|
|
6: /* 0 < low bits < 16 */
|
|
|
|
|
bgeu 120f
|
|
|
|
|
nop
|
|
|
|
|
/* fall through for 0 < low bits < 8 */
|
|
|
|
|
110: sub %o4, 64, %g2
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD_BLK(%g2, %f0), NG2_retl_o2_plus_g1)
|
|
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
|
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f16), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f14, f16)
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_MOVE_8(f16, f18, f20, f22, f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
120: sub %o4, 56, %g2
|
|
|
|
|
FREG_LOAD_7(%g2, f0, f2, f4, f6, f8, f10, f12)
|
2016-10-24 21:46:44 -06:00
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
|
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f16), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f16, f18)
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_MOVE_7(f18, f20, f22, f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
130: sub %o4, 48, %g2
|
|
|
|
|
FREG_LOAD_6(%g2, f0, f2, f4, f6, f8, f10)
|
2016-10-24 21:46:44 -06:00
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
|
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f16), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_FROB(f0, f2, f4, f6, f8, f10, f16, f18, f20)
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_MOVE_6(f20, f22, f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
140: sub %o4, 40, %g2
|
|
|
|
|
FREG_LOAD_5(%g2, f0, f2, f4, f6, f8)
|
2016-10-24 21:46:44 -06:00
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
|
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f16), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_FROB(f0, f2, f4, f6, f8, f16, f18, f20, f22)
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_MOVE_5(f22, f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
150: sub %o4, 32, %g2
|
|
|
|
|
FREG_LOAD_4(%g2, f0, f2, f4, f6)
|
2016-10-24 21:46:44 -06:00
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
|
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f16), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_FROB(f0, f2, f4, f6, f16, f18, f20, f22, f24)
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_MOVE_4(f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
160: sub %o4, 24, %g2
|
|
|
|
|
FREG_LOAD_3(%g2, f0, f2, f4)
|
2016-10-24 21:46:44 -06:00
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
|
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f16), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_FROB(f0, f2, f4, f16, f18, f20, f22, f24, f26)
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_MOVE_3(f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
170: sub %o4, 16, %g2
|
|
|
|
|
FREG_LOAD_2(%g2, f0, f2)
|
2016-10-24 21:46:44 -06:00
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
|
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f16), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_FROB(f0, f2, f16, f18, f20, f22, f24, f26, f28)
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_MOVE_2(f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
180: sub %o4, 8, %g2
|
|
|
|
|
FREG_LOAD_1(%g2, f0)
|
2016-10-24 21:46:44 -06:00
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
|
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f16), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_FROB(f0, f16, f18, f20, f22, f24, f26, f28, f30)
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
FREG_MOVE_1(f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
190:
|
2016-10-24 21:46:44 -06:00
|
|
|
1: EX_ST_FP(STORE_INIT(%g0, %o4 + %g3), NG2_retl_o2_plus_g1)
|
2007-08-16 02:47:25 -06:00
|
|
|
subcc %g1, 64, %g1
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD_FP(LOAD_BLK(%o4, %f0), NG2_retl_o2_plus_g1_plus_64)
|
|
|
|
|
EX_ST_FP(STORE_BLK(%f0, %o4 + %g3), NG2_retl_o2_plus_g1_plus_64)
|
2007-08-16 02:47:25 -06:00
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
|
|
|
|
|
195:
|
|
|
|
|
add %o4, %g3, %o0
|
|
|
|
|
membar #Sync
|
|
|
|
|
|
|
|
|
|
VISExitHalf
|
|
|
|
|
|
|
|
|
|
/* %o2 contains any final bytes still needed to be copied
|
|
|
|
|
* over. If anything is left, we copy it one byte at a time.
|
|
|
|
|
*/
|
|
|
|
|
brz,pt %o2, 85f
|
2012-09-27 02:06:43 -06:00
|
|
|
sub %o0, %o1, GLOBAL_SPARE
|
2007-08-16 02:47:25 -06:00
|
|
|
ba,a,pt %XCC, 90f
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
|
|
|
nop
|
2007-08-16 02:47:25 -06:00
|
|
|
|
|
|
|
|
.align 64
|
|
|
|
|
75: /* 16 < len <= 64 */
|
|
|
|
|
bne,pn %XCC, 75f
|
2012-09-27 02:06:43 -06:00
|
|
|
sub %o0, %o1, GLOBAL_SPARE
|
2007-08-16 02:47:25 -06:00
|
|
|
|
|
|
|
|
72:
|
|
|
|
|
andn %o2, 0xf, %o4
|
|
|
|
|
and %o2, 0xf, %o2
|
|
|
|
|
1: subcc %o4, 0x10, %o4
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD(LOAD(ldx, %o1, %o5), NG2_retl_o2_plus_o4_plus_16)
|
2007-08-16 02:47:25 -06:00
|
|
|
add %o1, 0x08, %o1
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD(LOAD(ldx, %o1, %g1), NG2_retl_o2_plus_o4_plus_16)
|
2007-08-16 02:47:25 -06:00
|
|
|
sub %o1, 0x08, %o1
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST(STORE(stx, %o5, %o1 + GLOBAL_SPARE), NG2_retl_o2_plus_o4_plus_16)
|
2007-08-16 02:47:25 -06:00
|
|
|
add %o1, 0x8, %o1
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_ST(STORE(stx, %g1, %o1 + GLOBAL_SPARE), NG2_retl_o2_plus_o4_plus_8)
|
2007-08-16 02:47:25 -06:00
|
|
|
bgu,pt %XCC, 1b
|
|
|
|
|
add %o1, 0x8, %o1
|
|
|
|
|
73: andcc %o2, 0x8, %g0
|
|
|
|
|
be,pt %XCC, 1f
|
|
|
|
|
nop
|
|
|
|
|
sub %o2, 0x8, %o2
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD(LOAD(ldx, %o1, %o5), NG2_retl_o2_plus_8)
|
|
|
|
|
EX_ST(STORE(stx, %o5, %o1 + GLOBAL_SPARE), NG2_retl_o2_plus_8)
|
2007-08-16 02:47:25 -06:00
|
|
|
add %o1, 0x8, %o1
|
|
|
|
|
1: andcc %o2, 0x4, %g0
|
|
|
|
|
be,pt %XCC, 1f
|
|
|
|
|
nop
|
|
|
|
|
sub %o2, 0x4, %o2
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD(LOAD(lduw, %o1, %o5), NG2_retl_o2_plus_4)
|
|
|
|
|
EX_ST(STORE(stw, %o5, %o1 + GLOBAL_SPARE), NG2_retl_o2_plus_4)
|
2007-08-16 02:47:25 -06:00
|
|
|
add %o1, 0x4, %o1
|
|
|
|
|
1: cmp %o2, 0
|
|
|
|
|
be,pt %XCC, 85f
|
|
|
|
|
nop
|
|
|
|
|
ba,pt %xcc, 90f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
75:
|
|
|
|
|
andcc %o0, 0x7, %g1
|
|
|
|
|
sub %g1, 0x8, %g1
|
|
|
|
|
be,pn %icc, 2f
|
|
|
|
|
sub %g0, %g1, %g1
|
|
|
|
|
sub %o2, %g1, %o2
|
|
|
|
|
|
|
|
|
|
1: subcc %g1, 1, %g1
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD(LOAD(ldub, %o1, %o5), NG2_retl_o2_plus_g1_plus_1)
|
|
|
|
|
EX_ST(STORE(stb, %o5, %o1 + GLOBAL_SPARE), NG2_retl_o2_plus_g1_plus_1)
|
2007-08-16 02:47:25 -06:00
|
|
|
bgu,pt %icc, 1b
|
|
|
|
|
add %o1, 1, %o1
|
|
|
|
|
|
2012-09-27 02:06:43 -06:00
|
|
|
2: add %o1, GLOBAL_SPARE, %o0
|
2007-08-16 02:47:25 -06:00
|
|
|
andcc %o1, 0x7, %g1
|
|
|
|
|
bne,pt %icc, 8f
|
|
|
|
|
sll %g1, 3, %g1
|
|
|
|
|
|
|
|
|
|
cmp %o2, 16
|
|
|
|
|
bgeu,pt %icc, 72b
|
|
|
|
|
nop
|
|
|
|
|
ba,a,pt %xcc, 73b
|
|
|
|
|
|
2012-09-27 02:06:43 -06:00
|
|
|
8: mov 64, GLOBAL_SPARE
|
2007-08-16 02:47:25 -06:00
|
|
|
andn %o1, 0x7, %o1
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD(LOAD(ldx, %o1, %g2), NG2_retl_o2)
|
2012-09-27 02:06:43 -06:00
|
|
|
sub GLOBAL_SPARE, %g1, GLOBAL_SPARE
|
2007-08-16 02:47:25 -06:00
|
|
|
andn %o2, 0x7, %o4
|
|
|
|
|
sllx %g2, %g1, %g2
|
|
|
|
|
1: add %o1, 0x8, %o1
|
2016-10-24 21:46:44 -06:00
|
|
|
EX_LD(LOAD(ldx, %o1, %g3), NG2_retl_o2_and_7_plus_o4)
|
2007-08-16 02:47:25 -06:00
|
|
|
subcc %o4, 0x8, %o4
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2012-09-27 02:06:43 -06:00
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srlx %g3, GLOBAL_SPARE, %o5
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2007-08-16 02:47:25 -06:00
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or %o5, %g2, %o5
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2016-10-24 21:46:44 -06:00
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EX_ST(STORE(stx, %o5, %o0), NG2_retl_o2_and_7_plus_o4_plus_8)
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2007-08-16 02:47:25 -06:00
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add %o0, 0x8, %o0
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bgu,pt %icc, 1b
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sllx %g3, %g1, %g2
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srl %g1, 3, %g1
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andcc %o2, 0x7, %o2
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be,pn %icc, 85f
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add %o1, %g1, %o1
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ba,pt %xcc, 90f
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2012-09-27 02:06:43 -06:00
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sub %o0, %o1, GLOBAL_SPARE
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2007-08-16 02:47:25 -06:00
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.align 64
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80: /* 0 < len <= 16 */
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2012-09-27 02:06:43 -06:00
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andcc GLOBAL_SPARE, 0x3, %g0
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2007-08-16 02:47:25 -06:00
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bne,pn %XCC, 90f
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2012-09-27 02:06:43 -06:00
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sub %o0, %o1, GLOBAL_SPARE
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2007-08-16 02:47:25 -06:00
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1:
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subcc %o2, 4, %o2
|
2016-10-24 21:46:44 -06:00
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EX_LD(LOAD(lduw, %o1, %g1), NG2_retl_o2_plus_4)
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EX_ST(STORE(stw, %g1, %o1 + GLOBAL_SPARE), NG2_retl_o2_plus_4)
|
2007-08-16 02:47:25 -06:00
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bgu,pt %XCC, 1b
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add %o1, 4, %o1
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85: retl
|
2012-09-27 02:06:43 -06:00
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mov EX_RETVAL(%o3), %o0
|
2007-08-16 02:47:25 -06:00
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.align 32
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90:
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subcc %o2, 1, %o2
|
2016-10-24 21:46:44 -06:00
|
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|
EX_LD(LOAD(ldub, %o1, %g1), NG2_retl_o2_plus_1)
|
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EX_ST(STORE(stb, %g1, %o1 + GLOBAL_SPARE), NG2_retl_o2_plus_1)
|
2007-08-16 02:47:25 -06:00
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|
bgu,pt %XCC, 90b
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add %o1, 1, %o1
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retl
|
2012-09-27 02:06:43 -06:00
|
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|
mov EX_RETVAL(%o3), %o0
|
2007-08-16 02:47:25 -06:00
|
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|
.size FUNC_NAME, .-FUNC_NAME
|