2017-10-06 07:31:47 -06:00
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#ifndef __PERF_MMAP_H
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#define __PERF_MMAP_H 1
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#include <linux/compiler.h>
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#include <linux/refcount.h>
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#include <linux/types.h>
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tools, perf: add and use optimized ring_buffer_{read_head, write_tail} helpers
Currently, on x86-64, perf uses LFENCE and MFENCE (rmb() and mb(),
respectively) when processing events from the perf ring buffer which
is unnecessarily expensive as we can do more lightweight in particular
given this is critical fast-path in perf.
According to Peter rmb()/mb() were added back then via a94d342b9cb0
("tools/perf: Add required memory barriers") at a time where kernel
still supported chips that needed it, but nowadays support for these
has been ditched completely, therefore we can fix them up as well.
While for x86-64, replacing rmb() and mb() with smp_*() variants would
result in just a compiler barrier for the former and LOCK + ADD for
the latter (__sync_synchronize() uses slower MFENCE by the way), Peter
suggested we can use smp_{load_acquire,store_release}() instead for
architectures where its implementation doesn't resolve in slower smp_mb().
Thus, e.g. in x86-64 we would be able to avoid CPU barrier entirely due
to TSO. For architectures where the latter needs to use smp_mb() e.g.
on arm, we stick to cheaper smp_rmb() variant for fetching the head.
This work adds helpers ring_buffer_read_head() and ring_buffer_write_tail()
for tools infrastructure that either switches to smp_load_acquire() for
architectures where it is cheaper or uses READ_ONCE() + smp_rmb() barrier
for those where it's not in order to fetch the data_head from the perf
control page, and it uses smp_store_release() to write the data_tail.
Latter is smp_mb() + WRITE_ONCE() combination or a cheaper variant if
architecture allows for it. Those that rely on smp_rmb() and smp_mb() can
further improve performance in a follow up step by implementing the two
under tools/arch/*/include/asm/barrier.h such that they don't have to
fallback to rmb() and mb() in tools/include/asm/barrier.h.
Switch perf to use ring_buffer_read_head() and ring_buffer_write_tail()
so it can make use of the optimizations. Later, we convert libbpf as
well to use the same helpers.
Side note [0]: the topic has been raised of whether one could simply use
the C11 gcc builtins [1] for the smp_load_acquire() and smp_store_release()
instead:
__atomic_load_n(ptr, __ATOMIC_ACQUIRE);
__atomic_store_n(ptr, val, __ATOMIC_RELEASE);
Kernel and (presumably) tooling shipped along with the kernel has a
minimum requirement of being able to build with gcc-4.6 and the latter
does not have C11 builtins. While generally the C11 memory models don't
align with the kernel's, the C11 load-acquire and store-release alone
/could/ suffice, however. Issue is that this is implementation dependent
on how the load-acquire and store-release is done by the compiler and
the mapping of supported compilers must align to be compatible with the
kernel's implementation, and thus needs to be verified/tracked on a
case by case basis whether they match (unless an architecture uses them
also from kernel side). The implementations for smp_load_acquire() and
smp_store_release() in this patch have been adapted from the kernel side
ones to have a concrete and compatible mapping in place.
[0] http://patchwork.ozlabs.org/patch/985422/
[1] https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2018-10-19 07:51:02 -06:00
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#include <linux/ring_buffer.h>
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2017-10-06 07:31:47 -06:00
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#include <stdbool.h>
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2018-11-06 02:03:35 -07:00
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#ifdef HAVE_AIO_SUPPORT
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#include <aio.h>
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#endif
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2017-10-06 07:31:47 -06:00
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#include "auxtrace.h"
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#include "event.h"
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/**
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* struct perf_mmap - perf's ring buffer mmap details
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*
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* @refcnt - e.g. code using PERF_EVENT_IOC_SET_OUTPUT to share this
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*/
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struct perf_mmap {
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void *base;
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int mask;
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int fd;
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2018-08-17 05:45:55 -06:00
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int cpu;
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2017-10-06 07:31:47 -06:00
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refcount_t refcnt;
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u64 prev;
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2018-03-06 08:36:01 -07:00
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u64 start;
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u64 end;
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2018-03-06 08:36:00 -07:00
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bool overwrite;
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2017-10-06 07:31:47 -06:00
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struct auxtrace_mmap auxtrace_mmap;
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char event_copy[PERF_SAMPLE_MAX_SIZE] __aligned(8);
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2018-11-06 02:03:35 -07:00
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#ifdef HAVE_AIO_SUPPORT
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struct {
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void *data;
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struct aiocb cblock;
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} aio;
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#endif
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2017-10-06 07:31:47 -06:00
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};
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/*
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* State machine of bkw_mmap_state:
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*
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* .________________(forbid)_____________.
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* | V
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* NOTREADY --(0)--> RUNNING --(1)--> DATA_PENDING --(2)--> EMPTY
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* ^ ^ | ^ |
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* | |__(forbid)____/ |___(forbid)___/|
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* | |
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* \_________________(3)_______________/
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*
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* NOTREADY : Backward ring buffers are not ready
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* RUNNING : Backward ring buffers are recording
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* DATA_PENDING : We are required to collect data from backward ring buffers
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* EMPTY : We have collected data from backward ring buffers.
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*
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* (0): Setup backward ring buffer
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* (1): Pause ring buffers for reading
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* (2): Read from ring buffers
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* (3): Resume ring buffers for recording
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*/
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enum bkw_mmap_state {
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BKW_MMAP_NOTREADY,
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BKW_MMAP_RUNNING,
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BKW_MMAP_DATA_PENDING,
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BKW_MMAP_EMPTY,
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};
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struct mmap_params {
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2018-11-06 02:03:35 -07:00
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int prot, mask, nr_cblocks;
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2017-10-06 07:31:47 -06:00
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struct auxtrace_mmap_params auxtrace_mp;
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};
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2018-08-17 05:45:55 -06:00
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int perf_mmap__mmap(struct perf_mmap *map, struct mmap_params *mp, int fd, int cpu);
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2017-10-06 07:31:47 -06:00
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void perf_mmap__munmap(struct perf_mmap *map);
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void perf_mmap__get(struct perf_mmap *map);
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void perf_mmap__put(struct perf_mmap *map);
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2018-03-06 08:36:05 -07:00
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void perf_mmap__consume(struct perf_mmap *map);
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2017-10-06 07:31:47 -06:00
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static inline u64 perf_mmap__read_head(struct perf_mmap *mm)
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{
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tools, perf: add and use optimized ring_buffer_{read_head, write_tail} helpers
Currently, on x86-64, perf uses LFENCE and MFENCE (rmb() and mb(),
respectively) when processing events from the perf ring buffer which
is unnecessarily expensive as we can do more lightweight in particular
given this is critical fast-path in perf.
According to Peter rmb()/mb() were added back then via a94d342b9cb0
("tools/perf: Add required memory barriers") at a time where kernel
still supported chips that needed it, but nowadays support for these
has been ditched completely, therefore we can fix them up as well.
While for x86-64, replacing rmb() and mb() with smp_*() variants would
result in just a compiler barrier for the former and LOCK + ADD for
the latter (__sync_synchronize() uses slower MFENCE by the way), Peter
suggested we can use smp_{load_acquire,store_release}() instead for
architectures where its implementation doesn't resolve in slower smp_mb().
Thus, e.g. in x86-64 we would be able to avoid CPU barrier entirely due
to TSO. For architectures where the latter needs to use smp_mb() e.g.
on arm, we stick to cheaper smp_rmb() variant for fetching the head.
This work adds helpers ring_buffer_read_head() and ring_buffer_write_tail()
for tools infrastructure that either switches to smp_load_acquire() for
architectures where it is cheaper or uses READ_ONCE() + smp_rmb() barrier
for those where it's not in order to fetch the data_head from the perf
control page, and it uses smp_store_release() to write the data_tail.
Latter is smp_mb() + WRITE_ONCE() combination or a cheaper variant if
architecture allows for it. Those that rely on smp_rmb() and smp_mb() can
further improve performance in a follow up step by implementing the two
under tools/arch/*/include/asm/barrier.h such that they don't have to
fallback to rmb() and mb() in tools/include/asm/barrier.h.
Switch perf to use ring_buffer_read_head() and ring_buffer_write_tail()
so it can make use of the optimizations. Later, we convert libbpf as
well to use the same helpers.
Side note [0]: the topic has been raised of whether one could simply use
the C11 gcc builtins [1] for the smp_load_acquire() and smp_store_release()
instead:
__atomic_load_n(ptr, __ATOMIC_ACQUIRE);
__atomic_store_n(ptr, val, __ATOMIC_RELEASE);
Kernel and (presumably) tooling shipped along with the kernel has a
minimum requirement of being able to build with gcc-4.6 and the latter
does not have C11 builtins. While generally the C11 memory models don't
align with the kernel's, the C11 load-acquire and store-release alone
/could/ suffice, however. Issue is that this is implementation dependent
on how the load-acquire and store-release is done by the compiler and
the mapping of supported compilers must align to be compatible with the
kernel's implementation, and thus needs to be verified/tracked on a
case by case basis whether they match (unless an architecture uses them
also from kernel side). The implementations for smp_load_acquire() and
smp_store_release() in this patch have been adapted from the kernel side
ones to have a concrete and compatible mapping in place.
[0] http://patchwork.ozlabs.org/patch/985422/
[1] https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2018-10-19 07:51:02 -06:00
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return ring_buffer_read_head(mm->base);
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2017-10-06 07:31:47 -06:00
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}
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static inline void perf_mmap__write_tail(struct perf_mmap *md, u64 tail)
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{
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tools, perf: add and use optimized ring_buffer_{read_head, write_tail} helpers
Currently, on x86-64, perf uses LFENCE and MFENCE (rmb() and mb(),
respectively) when processing events from the perf ring buffer which
is unnecessarily expensive as we can do more lightweight in particular
given this is critical fast-path in perf.
According to Peter rmb()/mb() were added back then via a94d342b9cb0
("tools/perf: Add required memory barriers") at a time where kernel
still supported chips that needed it, but nowadays support for these
has been ditched completely, therefore we can fix them up as well.
While for x86-64, replacing rmb() and mb() with smp_*() variants would
result in just a compiler barrier for the former and LOCK + ADD for
the latter (__sync_synchronize() uses slower MFENCE by the way), Peter
suggested we can use smp_{load_acquire,store_release}() instead for
architectures where its implementation doesn't resolve in slower smp_mb().
Thus, e.g. in x86-64 we would be able to avoid CPU barrier entirely due
to TSO. For architectures where the latter needs to use smp_mb() e.g.
on arm, we stick to cheaper smp_rmb() variant for fetching the head.
This work adds helpers ring_buffer_read_head() and ring_buffer_write_tail()
for tools infrastructure that either switches to smp_load_acquire() for
architectures where it is cheaper or uses READ_ONCE() + smp_rmb() barrier
for those where it's not in order to fetch the data_head from the perf
control page, and it uses smp_store_release() to write the data_tail.
Latter is smp_mb() + WRITE_ONCE() combination or a cheaper variant if
architecture allows for it. Those that rely on smp_rmb() and smp_mb() can
further improve performance in a follow up step by implementing the two
under tools/arch/*/include/asm/barrier.h such that they don't have to
fallback to rmb() and mb() in tools/include/asm/barrier.h.
Switch perf to use ring_buffer_read_head() and ring_buffer_write_tail()
so it can make use of the optimizations. Later, we convert libbpf as
well to use the same helpers.
Side note [0]: the topic has been raised of whether one could simply use
the C11 gcc builtins [1] for the smp_load_acquire() and smp_store_release()
instead:
__atomic_load_n(ptr, __ATOMIC_ACQUIRE);
__atomic_store_n(ptr, val, __ATOMIC_RELEASE);
Kernel and (presumably) tooling shipped along with the kernel has a
minimum requirement of being able to build with gcc-4.6 and the latter
does not have C11 builtins. While generally the C11 memory models don't
align with the kernel's, the C11 load-acquire and store-release alone
/could/ suffice, however. Issue is that this is implementation dependent
on how the load-acquire and store-release is done by the compiler and
the mapping of supported compilers must align to be compatible with the
kernel's implementation, and thus needs to be verified/tracked on a
case by case basis whether they match (unless an architecture uses them
also from kernel side). The implementations for smp_load_acquire() and
smp_store_release() in this patch have been adapted from the kernel side
ones to have a concrete and compatible mapping in place.
[0] http://patchwork.ozlabs.org/patch/985422/
[1] https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2018-10-19 07:51:02 -06:00
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ring_buffer_write_tail(md->base, tail);
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2017-10-06 07:31:47 -06:00
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}
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2017-12-02 19:00:41 -07:00
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union perf_event *perf_mmap__read_forward(struct perf_mmap *map);
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2017-10-06 07:31:47 -06:00
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2018-03-06 08:36:06 -07:00
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union perf_event *perf_mmap__read_event(struct perf_mmap *map);
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2018-01-18 14:26:23 -07:00
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2018-03-06 08:36:02 -07:00
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int perf_mmap__push(struct perf_mmap *md, void *to,
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2018-09-13 06:54:06 -06:00
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int push(struct perf_mmap *map, void *to, void *buf, size_t size));
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2017-10-06 07:46:01 -06:00
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2017-10-06 07:31:47 -06:00
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size_t perf_mmap__mmap_len(struct perf_mmap *map);
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2018-03-06 08:36:07 -07:00
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int perf_mmap__read_init(struct perf_mmap *md);
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2018-01-18 14:26:22 -07:00
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void perf_mmap__read_done(struct perf_mmap *map);
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2017-10-06 07:31:47 -06:00
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#endif /*__PERF_MMAP_H */
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