184 lines
4.1 KiB
C
184 lines
4.1 KiB
C
![]() |
/*
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* Atheros AR71XX/AR724X/AR913X common routines
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*
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#define AR71XX_BASE_FREQ 40000000
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#define AR724X_BASE_FREQ 5000000
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#define AR913X_BASE_FREQ 5000000
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struct clk {
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unsigned long rate;
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};
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static struct clk ath79_ref_clk;
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static struct clk ath79_cpu_clk;
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static struct clk ath79_ddr_clk;
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static struct clk ath79_ahb_clk;
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static struct clk ath79_wdt_clk;
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static struct clk ath79_uart_clk;
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static void __init ar71xx_clocks_init(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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ath79_ref_clk.rate = AR71XX_BASE_FREQ;
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pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
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freq = div * ath79_ref_clk.rate;
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div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
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ath79_cpu_clk.rate = freq / div;
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div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
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ath79_ddr_clk.rate = freq / div;
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
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ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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ath79_uart_clk.rate = ath79_ahb_clk.rate;
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}
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static void __init ar724x_clocks_init(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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ath79_ref_clk.rate = AR724X_BASE_FREQ;
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pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
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freq = div * ath79_ref_clk.rate;
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div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
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freq *= div;
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ath79_cpu_clk.rate = freq;
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div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
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ath79_ddr_clk.rate = freq / div;
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div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
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ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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ath79_uart_clk.rate = ath79_ahb_clk.rate;
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}
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static void __init ar913x_clocks_init(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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ath79_ref_clk.rate = AR913X_BASE_FREQ;
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pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
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freq = div * ath79_ref_clk.rate;
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ath79_cpu_clk.rate = freq;
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div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
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ath79_ddr_clk.rate = freq / div;
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div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
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ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
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ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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ath79_uart_clk.rate = ath79_ahb_clk.rate;
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}
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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ar71xx_clocks_init();
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else if (soc_is_ar724x())
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ar724x_clocks_init();
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else if (soc_is_ar913x())
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ar913x_clocks_init();
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else
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BUG();
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pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, "
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"Ref:%lu.%03luMHz",
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ath79_cpu_clk.rate / 1000000,
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(ath79_cpu_clk.rate / 1000) % 1000,
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ath79_ddr_clk.rate / 1000000,
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(ath79_ddr_clk.rate / 1000) % 1000,
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ath79_ahb_clk.rate / 1000000,
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(ath79_ahb_clk.rate / 1000) % 1000,
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ath79_ref_clk.rate / 1000000,
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(ath79_ref_clk.rate / 1000) % 1000);
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}
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/*
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* Linux clock API
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*/
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struct clk *clk_get(struct device *dev, const char *id)
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{
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if (!strcmp(id, "ref"))
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return &ath79_ref_clk;
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if (!strcmp(id, "cpu"))
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return &ath79_cpu_clk;
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if (!strcmp(id, "ddr"))
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return &ath79_ddr_clk;
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if (!strcmp(id, "ahb"))
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return &ath79_ahb_clk;
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if (!strcmp(id, "wdt"))
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return &ath79_wdt_clk;
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if (!strcmp(id, "uart"))
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return &ath79_uart_clk;
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return ERR_PTR(-ENOENT);
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}
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EXPORT_SYMBOL(clk_get);
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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void clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_put);
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