2019-06-04 02:11:33 -06:00
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// SPDX-License-Identifier: GPL-2.0-only
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2012-07-31 08:16:24 -06:00
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/*
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* VFIO PCI config space virtualization
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*
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* Copyright (C) 2012 Red Hat, Inc. All rights reserved.
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* Author: Alex Williamson <alex.williamson@redhat.com>
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*
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* Derived from original vfio:
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* Copyright 2010 Cisco Systems, Inc. All rights reserved.
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* Author: Tom Lyon, pugs@cisco.com
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*/
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/*
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* This code handles reading and writing of PCI configuration registers.
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* This is hairy because we want to allow a lot of flexibility to the
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* user driver, but cannot trust it with all of the config fields.
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* Tables determine which fields can be read and written, as well as
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* which fields are 'virtualized' - special actions and translations to
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* make it appear to the user that he has control, when in fact things
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* must be negotiated with the underlying OS.
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*/
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#include <linux/fs.h>
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#include <linux/pci.h>
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#include <linux/uaccess.h>
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#include <linux/vfio.h>
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2013-03-15 12:58:20 -06:00
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#include <linux/slab.h>
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2012-07-31 08:16:24 -06:00
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#include "vfio_pci_private.h"
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2016-02-22 16:02:41 -07:00
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/* Fake capability ID for standard config space */
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2012-07-31 08:16:24 -06:00
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#define PCI_CAP_ID_BASIC 0
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#define is_bar(offset) \
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((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
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(offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
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/*
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* Lengths of PCI Config Capabilities
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* 0: Removed from the user visible capability list
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* FF: Variable length
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*/
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2015-11-09 05:24:55 -07:00
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static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
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2012-07-31 08:16:24 -06:00
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[PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
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[PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
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[PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
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[PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
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[PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
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[PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
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[PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
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[PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
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[PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
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[PCI_CAP_ID_VNDR] = 0xFF, /* variable */
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[PCI_CAP_ID_DBG] = 0, /* debug - don't care */
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[PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
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[PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
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[PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
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[PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
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[PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
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[PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
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[PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
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[PCI_CAP_ID_SATA] = 0xFF,
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[PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
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};
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/*
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* Lengths of PCIe/PCI-X Extended Config Capabilities
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2016-08-17 00:37:05 -06:00
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* 0: Removed or masked from the user visible capability list
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2012-07-31 08:16:24 -06:00
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* FF: Variable length
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*/
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2015-11-09 05:24:55 -07:00
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static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
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2012-07-31 08:16:24 -06:00
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[PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
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[PCI_EXT_CAP_ID_VC] = 0xFF,
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[PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
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[PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
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[PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
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[PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
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[PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
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[PCI_EXT_CAP_ID_MFVC] = 0xFF,
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[PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
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[PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
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[PCI_EXT_CAP_ID_VNDR] = 0xFF,
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[PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
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[PCI_EXT_CAP_ID_ACS] = 0xFF,
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[PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
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[PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
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[PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
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[PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
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[PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
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[PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
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[PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
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[PCI_EXT_CAP_ID_REBAR] = 0xFF,
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[PCI_EXT_CAP_ID_DPA] = 0xFF,
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[PCI_EXT_CAP_ID_TPH] = 0xFF,
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[PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
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[PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
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[PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
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[PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
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};
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/*
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* Read/Write Permission Bits - one bit for each bit in capability
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* Any field can be read if it exists, but what is read depends on
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* whether the field is 'virtualized', or just pass thru to the
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* hardware. Any virtualized field is also virtualized for writes.
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* Writes are only permitted if they have a 1 bit here.
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*/
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struct perm_bits {
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u8 *virt; /* read/write virtual data, not hw */
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u8 *write; /* writeable bits */
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int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
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struct perm_bits *perm, int offset, __le32 *val);
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int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
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struct perm_bits *perm, int offset, __le32 val);
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};
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#define NO_VIRT 0
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#define ALL_VIRT 0xFFFFFFFFU
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#define NO_WRITE 0
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#define ALL_WRITE 0xFFFFFFFFU
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static int vfio_user_config_read(struct pci_dev *pdev, int offset,
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__le32 *val, int count)
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{
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int ret = -EINVAL;
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u32 tmp_val = 0;
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switch (count) {
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case 1:
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{
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u8 tmp;
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ret = pci_user_read_config_byte(pdev, offset, &tmp);
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tmp_val = tmp;
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break;
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}
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case 2:
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{
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u16 tmp;
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ret = pci_user_read_config_word(pdev, offset, &tmp);
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tmp_val = tmp;
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break;
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}
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case 4:
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ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
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break;
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}
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*val = cpu_to_le32(tmp_val);
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2016-11-18 04:47:38 -07:00
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return ret;
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2012-07-31 08:16:24 -06:00
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}
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static int vfio_user_config_write(struct pci_dev *pdev, int offset,
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__le32 val, int count)
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{
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int ret = -EINVAL;
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u32 tmp_val = le32_to_cpu(val);
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switch (count) {
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case 1:
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ret = pci_user_write_config_byte(pdev, offset, tmp_val);
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break;
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case 2:
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ret = pci_user_write_config_word(pdev, offset, tmp_val);
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break;
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case 4:
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ret = pci_user_write_config_dword(pdev, offset, tmp_val);
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break;
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}
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2016-11-18 04:47:38 -07:00
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return ret;
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2012-07-31 08:16:24 -06:00
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}
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static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
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int count, struct perm_bits *perm,
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int offset, __le32 *val)
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{
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__le32 virt = 0;
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memcpy(val, vdev->vconfig + pos, count);
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memcpy(&virt, perm->virt + offset, count);
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/* Any non-virtualized bits? */
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if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
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struct pci_dev *pdev = vdev->pdev;
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__le32 phys_val = 0;
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int ret;
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ret = vfio_user_config_read(pdev, pos, &phys_val, count);
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if (ret)
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return ret;
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*val = (phys_val & ~virt) | (*val & virt);
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}
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return count;
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}
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static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
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int count, struct perm_bits *perm,
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int offset, __le32 val)
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{
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__le32 virt = 0, write = 0;
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memcpy(&write, perm->write + offset, count);
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if (!write)
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return count; /* drop, no writable bits */
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memcpy(&virt, perm->virt + offset, count);
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/* Virtualized and writable bits go to vconfig */
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if (write & virt) {
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__le32 virt_val = 0;
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memcpy(&virt_val, vdev->vconfig + pos, count);
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virt_val &= ~(write & virt);
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virt_val |= (val & (write & virt));
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memcpy(vdev->vconfig + pos, &virt_val, count);
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}
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/* Non-virtualzed and writable bits go to hardware */
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if (write & ~virt) {
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struct pci_dev *pdev = vdev->pdev;
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__le32 phys_val = 0;
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int ret;
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ret = vfio_user_config_read(pdev, pos, &phys_val, count);
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if (ret)
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return ret;
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phys_val &= ~(write & ~virt);
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phys_val |= (val & (write & ~virt));
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ret = vfio_user_config_write(pdev, pos, phys_val, count);
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if (ret)
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return ret;
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}
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return count;
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}
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/* Allow direct read from hardware, except for capability next pointer */
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static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
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int count, struct perm_bits *perm,
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int offset, __le32 *val)
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{
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int ret;
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ret = vfio_user_config_read(vdev->pdev, pos, val, count);
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if (ret)
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2016-11-18 04:47:38 -07:00
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return ret;
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2012-07-31 08:16:24 -06:00
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if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
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if (offset < 4)
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memcpy(val, vdev->vconfig + pos, count);
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} else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
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if (offset == PCI_CAP_LIST_ID && count > 1)
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memcpy(val, vdev->vconfig + pos,
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min(PCI_CAP_FLAGS, count));
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else if (offset == PCI_CAP_LIST_NEXT)
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memcpy(val, vdev->vconfig + pos, 1);
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}
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return count;
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}
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2013-04-01 09:04:12 -06:00
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/* Raw access skips any kind of virtualization */
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static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
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int count, struct perm_bits *perm,
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int offset, __le32 val)
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2012-07-31 08:16:24 -06:00
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{
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int ret;
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ret = vfio_user_config_write(vdev->pdev, pos, val, count);
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if (ret)
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return ret;
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return count;
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}
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2013-04-01 09:04:12 -06:00
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static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
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int count, struct perm_bits *perm,
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int offset, __le32 *val)
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{
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int ret;
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ret = vfio_user_config_read(vdev->pdev, pos, val, count);
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if (ret)
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2016-11-18 04:47:38 -07:00
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return ret;
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2013-04-01 09:04:12 -06:00
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return count;
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}
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2016-02-22 16:02:41 -07:00
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/* Virt access uses only virtualization */
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static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
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int count, struct perm_bits *perm,
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int offset, __le32 val)
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{
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memcpy(vdev->vconfig + pos, &val, count);
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return count;
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}
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static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
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int count, struct perm_bits *perm,
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int offset, __le32 *val)
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{
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memcpy(val, vdev->vconfig + pos, count);
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return count;
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}
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2013-04-01 09:04:12 -06:00
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/* Default capability regions to read-only, no-virtualization */
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2012-07-31 08:16:24 -06:00
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static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
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[0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
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};
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static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
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[0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
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};
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2013-04-01 09:04:12 -06:00
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/*
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* Default unassigned regions to raw read-write access. Some devices
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* require this to function as they hide registers between the gaps in
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* config space (be2net). Like MMIO and I/O port registers, we have
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* to trust the hardware isolation.
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*/
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static struct perm_bits unassigned_perms = {
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.readfn = vfio_raw_config_read,
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.writefn = vfio_raw_config_write
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};
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2016-02-22 16:02:41 -07:00
|
|
|
static struct perm_bits virt_perms = {
|
|
|
|
.readfn = vfio_virt_config_read,
|
|
|
|
.writefn = vfio_virt_config_write
|
|
|
|
};
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
static void free_perm_bits(struct perm_bits *perm)
|
|
|
|
{
|
|
|
|
kfree(perm->virt);
|
|
|
|
kfree(perm->write);
|
|
|
|
perm->virt = NULL;
|
|
|
|
perm->write = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int alloc_perm_bits(struct perm_bits *perm, int size)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Round up all permission bits to the next dword, this lets us
|
|
|
|
* ignore whether a read/write exceeds the defined capability
|
|
|
|
* structure. We can do this because:
|
|
|
|
* - Standard config space is already dword aligned
|
2016-08-17 00:37:05 -06:00
|
|
|
* - Capabilities are all dword aligned (bits 0:1 of next reserved)
|
2012-07-31 08:16:24 -06:00
|
|
|
* - Express capabilities defined as dword aligned
|
|
|
|
*/
|
|
|
|
size = round_up(size, 4);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Zero state is
|
|
|
|
* - All Readable, None Writeable, None Virtualized
|
|
|
|
*/
|
|
|
|
perm->virt = kzalloc(size, GFP_KERNEL);
|
|
|
|
perm->write = kzalloc(size, GFP_KERNEL);
|
|
|
|
if (!perm->virt || !perm->write) {
|
|
|
|
free_perm_bits(perm);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
perm->readfn = vfio_default_config_read;
|
|
|
|
perm->writefn = vfio_default_config_write;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Helper functions for filling in permission tables
|
|
|
|
*/
|
|
|
|
static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
|
|
|
|
{
|
|
|
|
p->virt[off] = virt;
|
|
|
|
p->write[off] = write;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle endian-ness - pci and tables are little-endian */
|
|
|
|
static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
|
|
|
|
{
|
|
|
|
*(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
|
|
|
|
*(__le16 *)(&p->write[off]) = cpu_to_le16(write);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle endian-ness - pci and tables are little-endian */
|
|
|
|
static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
|
|
|
|
{
|
|
|
|
*(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
|
|
|
|
*(__le32 *)(&p->write[off]) = cpu_to_le32(write);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Restore the *real* BARs after we detect a FLR or backdoor reset.
|
|
|
|
* (backdoor = some device specific technique that we didn't catch)
|
|
|
|
*/
|
|
|
|
static void vfio_bar_restore(struct vfio_pci_device *vdev)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
u32 *rbar = vdev->rbar;
|
vfio/pci: Hide broken INTx support from user
INTx masking has two components, the first is that we need the ability
to prevent the device from continuing to assert INTx. This is
provided via the DisINTx bit in the command register and is the only
thing we can really probe for when testing if INTx masking is
supported. The second component is that the device needs to indicate
if INTx is asserted via the interrupt status bit in the device status
register. With these two features we can generically determine if one
of the devices we own is asserting INTx, signal the user, and mask the
interrupt while the user services the device.
Generally if one or both of these components is broken we resort to
APIC level interrupt masking, which requires an exclusive interrupt
since we have no way to determine the source of the interrupt in a
shared configuration. This often makes it difficult or impossible to
configure the system for userspace use of the device, for an interrupt
mode that the user may not need.
One possible configuration of broken INTx masking is that the DisINTx
support is fully functional, but the interrupt status bit never
signals interrupt assertion. In this case we do have the ability to
prevent the device from asserting INTx, but lack the ability to
identify the interrupt source. For this case we can simply pretend
that the device lacks INTx support entirely, keeping DisINTx set on
the physical device, virtualizing this bit for the user, and
virtualizing the interrupt pin register to indicate no INTx support.
We already support virtualization of the DisINTx bit and already
virtualize the interrupt pin for platforms without INTx support. By
tying these components together, setting DisINTx on open and reset,
and identifying devices broken in this particular way, we can provide
support for them w/o the handicap of APIC level INTx masking.
Intel i40e (XL710/X710) 10/20/40GbE NICs have been identified as being
broken in this specific way. We leave the vfio-pci.nointxmask option
as a mechanism to bypass this support, enabling INTx on the device
with all the requirements of APIC level masking.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Cc: John Ronciak <john.ronciak@intel.com>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
2016-03-24 13:05:18 -06:00
|
|
|
u16 cmd;
|
2012-07-31 08:16:24 -06:00
|
|
|
int i;
|
|
|
|
|
|
|
|
if (pdev->is_virtfn)
|
|
|
|
return;
|
|
|
|
|
2019-03-30 08:41:35 -06:00
|
|
|
pci_info(pdev, "%s: reset recovery - restoring BARs\n", __func__);
|
2012-07-31 08:16:24 -06:00
|
|
|
|
|
|
|
for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
|
|
|
|
pci_user_write_config_dword(pdev, i, *rbar);
|
|
|
|
|
|
|
|
pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
|
vfio/pci: Hide broken INTx support from user
INTx masking has two components, the first is that we need the ability
to prevent the device from continuing to assert INTx. This is
provided via the DisINTx bit in the command register and is the only
thing we can really probe for when testing if INTx masking is
supported. The second component is that the device needs to indicate
if INTx is asserted via the interrupt status bit in the device status
register. With these two features we can generically determine if one
of the devices we own is asserting INTx, signal the user, and mask the
interrupt while the user services the device.
Generally if one or both of these components is broken we resort to
APIC level interrupt masking, which requires an exclusive interrupt
since we have no way to determine the source of the interrupt in a
shared configuration. This often makes it difficult or impossible to
configure the system for userspace use of the device, for an interrupt
mode that the user may not need.
One possible configuration of broken INTx masking is that the DisINTx
support is fully functional, but the interrupt status bit never
signals interrupt assertion. In this case we do have the ability to
prevent the device from asserting INTx, but lack the ability to
identify the interrupt source. For this case we can simply pretend
that the device lacks INTx support entirely, keeping DisINTx set on
the physical device, virtualizing this bit for the user, and
virtualizing the interrupt pin register to indicate no INTx support.
We already support virtualization of the DisINTx bit and already
virtualize the interrupt pin for platforms without INTx support. By
tying these components together, setting DisINTx on open and reset,
and identifying devices broken in this particular way, we can provide
support for them w/o the handicap of APIC level INTx masking.
Intel i40e (XL710/X710) 10/20/40GbE NICs have been identified as being
broken in this specific way. We leave the vfio-pci.nointxmask option
as a mechanism to bypass this support, enabling INTx on the device
with all the requirements of APIC level masking.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Cc: John Ronciak <john.ronciak@intel.com>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
2016-03-24 13:05:18 -06:00
|
|
|
|
|
|
|
if (vdev->nointx) {
|
|
|
|
pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
|
|
cmd |= PCI_COMMAND_INTX_DISABLE;
|
|
|
|
pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
|
|
}
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
|
|
|
|
{
|
|
|
|
unsigned long flags = pci_resource_flags(pdev, bar);
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (flags & IORESOURCE_IO)
|
|
|
|
return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
|
|
|
|
|
|
|
|
val = PCI_BASE_ADDRESS_SPACE_MEMORY;
|
|
|
|
|
|
|
|
if (flags & IORESOURCE_PREFETCH)
|
|
|
|
val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
|
|
|
|
|
|
|
|
if (flags & IORESOURCE_MEM_64)
|
|
|
|
val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
|
|
|
|
|
|
|
|
return cpu_to_le32(val);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Pretend we're hardware and tweak the values of the *virtual* PCI BARs
|
|
|
|
* to reflect the hardware capabilities. This implements BAR sizing.
|
|
|
|
*/
|
|
|
|
static void vfio_bar_fixup(struct vfio_pci_device *vdev)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
int i;
|
2019-09-27 17:43:08 -06:00
|
|
|
__le32 *vbar;
|
2012-07-31 08:16:24 -06:00
|
|
|
u64 mask;
|
|
|
|
|
2019-09-27 17:43:08 -06:00
|
|
|
vbar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2019-09-27 17:43:08 -06:00
|
|
|
for (i = 0; i < PCI_STD_NUM_BARS; i++, vbar++) {
|
|
|
|
int bar = i + PCI_STD_RESOURCES;
|
|
|
|
|
|
|
|
if (!pci_resource_start(pdev, bar)) {
|
|
|
|
*vbar = 0; /* Unmapped by host = unimplemented to user */
|
2012-07-31 08:16:24 -06:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2019-09-27 17:43:08 -06:00
|
|
|
mask = ~(pci_resource_len(pdev, bar) - 1);
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2019-09-27 17:43:08 -06:00
|
|
|
*vbar &= cpu_to_le32((u32)mask);
|
|
|
|
*vbar |= vfio_generate_bar_flags(pdev, bar);
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2019-09-27 17:43:08 -06:00
|
|
|
if (*vbar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
|
|
|
|
vbar++;
|
|
|
|
*vbar &= cpu_to_le32((u32)(mask >> 32));
|
2012-07-31 08:16:24 -06:00
|
|
|
i++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-27 17:43:08 -06:00
|
|
|
vbar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
|
2012-07-31 08:16:24 -06:00
|
|
|
|
|
|
|
/*
|
2016-02-22 16:02:46 -07:00
|
|
|
* NB. REGION_INFO will have reported zero size if we weren't able
|
|
|
|
* to read the ROM, but we still return the actual BAR size here if
|
|
|
|
* it exists (or the shadow ROM space).
|
2012-07-31 08:16:24 -06:00
|
|
|
*/
|
|
|
|
if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
|
|
|
|
mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
|
|
|
|
mask |= PCI_ROM_ADDRESS_ENABLE;
|
2019-09-27 17:43:08 -06:00
|
|
|
*vbar &= cpu_to_le32((u32)mask);
|
2016-02-22 16:02:46 -07:00
|
|
|
} else if (pdev->resource[PCI_ROM_RESOURCE].flags &
|
|
|
|
IORESOURCE_ROM_SHADOW) {
|
|
|
|
mask = ~(0x20000 - 1);
|
|
|
|
mask |= PCI_ROM_ADDRESS_ENABLE;
|
2019-09-27 17:43:08 -06:00
|
|
|
*vbar &= cpu_to_le32((u32)mask);
|
2012-07-31 08:16:24 -06:00
|
|
|
} else
|
2019-09-27 17:43:08 -06:00
|
|
|
*vbar = 0;
|
2012-07-31 08:16:24 -06:00
|
|
|
|
|
|
|
vdev->bardirty = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
|
|
|
|
int count, struct perm_bits *perm,
|
|
|
|
int offset, __le32 *val)
|
|
|
|
{
|
|
|
|
if (is_bar(offset)) /* pos == offset for basic config */
|
|
|
|
vfio_bar_fixup(vdev);
|
|
|
|
|
|
|
|
count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
|
|
|
|
|
|
|
|
/* Mask in virtual memory enable for SR-IOV devices */
|
|
|
|
if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
|
|
|
|
u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
|
|
|
|
u32 tmp_val = le32_to_cpu(*val);
|
|
|
|
|
|
|
|
tmp_val |= cmd & PCI_COMMAND_MEMORY;
|
|
|
|
*val = cpu_to_le32(tmp_val);
|
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2016-03-24 13:06:16 -06:00
|
|
|
/* Test whether BARs match the value we think they should contain */
|
|
|
|
static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
|
|
|
|
{
|
|
|
|
int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
|
|
|
|
u32 bar;
|
|
|
|
|
|
|
|
for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
|
|
|
|
if (vdev->rbar[i]) {
|
|
|
|
ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
|
|
|
|
if (ret || vdev->rbar[i] != bar)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
|
|
|
|
int count, struct perm_bits *perm,
|
|
|
|
int offset, __le32 val)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
__le16 *virt_cmd;
|
|
|
|
u16 new_cmd = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
|
|
|
|
|
|
|
|
if (offset == PCI_COMMAND) {
|
|
|
|
bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
|
|
|
|
u16 phys_cmd;
|
|
|
|
|
|
|
|
ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
new_cmd = le32_to_cpu(val);
|
|
|
|
|
|
|
|
phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
|
|
|
|
virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
|
|
|
|
new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
|
|
|
|
|
|
|
|
phys_io = !!(phys_cmd & PCI_COMMAND_IO);
|
|
|
|
virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
|
|
|
|
new_io = !!(new_cmd & PCI_COMMAND_IO);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the user is writing mem/io enable (new_mem/io) and we
|
|
|
|
* think it's already enabled (virt_mem/io), but the hardware
|
|
|
|
* shows it disabled (phys_mem/io, then the device has
|
|
|
|
* undergone some kind of backdoor reset and needs to be
|
|
|
|
* restored before we allow it to enable the bars.
|
|
|
|
* SR-IOV devices will trigger this, but we catch them later
|
|
|
|
*/
|
|
|
|
if ((new_mem && virt_mem && !phys_mem) ||
|
2016-03-24 13:06:16 -06:00
|
|
|
(new_io && virt_io && !phys_io) ||
|
|
|
|
vfio_need_bar_restore(vdev))
|
2012-07-31 08:16:24 -06:00
|
|
|
vfio_bar_restore(vdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
|
|
|
|
if (count < 0)
|
|
|
|
return count;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Save current memory/io enable bits in vconfig to allow for
|
|
|
|
* the test above next time.
|
|
|
|
*/
|
|
|
|
if (offset == PCI_COMMAND) {
|
|
|
|
u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
|
|
|
|
|
|
|
|
*virt_cmd &= cpu_to_le16(~mask);
|
|
|
|
*virt_cmd |= cpu_to_le16(new_cmd & mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Emulate INTx disable */
|
|
|
|
if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
|
|
|
|
bool virt_intx_disable;
|
|
|
|
|
|
|
|
virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
|
|
|
|
PCI_COMMAND_INTX_DISABLE);
|
|
|
|
|
|
|
|
if (virt_intx_disable && !vdev->virq_disabled) {
|
|
|
|
vdev->virq_disabled = true;
|
|
|
|
vfio_pci_intx_mask(vdev);
|
|
|
|
} else if (!virt_intx_disable && vdev->virq_disabled) {
|
|
|
|
vdev->virq_disabled = false;
|
|
|
|
vfio_pci_intx_unmask(vdev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_bar(offset))
|
|
|
|
vdev->bardirty = true;
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Permissions for the Basic PCI Header */
|
|
|
|
static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
|
|
|
|
{
|
|
|
|
if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
perm->readfn = vfio_basic_config_read;
|
|
|
|
perm->writefn = vfio_basic_config_write;
|
|
|
|
|
|
|
|
/* Virtualized for SR-IOV functions, which just have FFFF */
|
|
|
|
p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
|
|
|
|
p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Virtualize INTx disable, we use it internally for interrupt
|
|
|
|
* control and can emulate it for non-PCI 2.3 devices.
|
|
|
|
*/
|
|
|
|
p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
|
|
|
|
|
|
|
|
/* Virtualize capability list, we might want to skip/disable */
|
|
|
|
p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
|
|
|
|
|
|
|
|
/* No harm to write */
|
|
|
|
p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
|
|
|
|
p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
|
|
|
|
p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
|
|
|
|
|
|
|
|
/* Virtualize all bars, can't touch the real ones */
|
|
|
|
p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
|
|
|
|
|
|
|
|
/* Allow us to adjust capability chain */
|
|
|
|
p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
/* Sometimes used by sw, just virtualize */
|
|
|
|
p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
|
2014-11-07 09:52:22 -07:00
|
|
|
|
|
|
|
/* Virtualize interrupt pin to allow hiding INTx */
|
|
|
|
p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-18 10:10:33 -07:00
|
|
|
static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
|
|
|
|
int count, struct perm_bits *perm,
|
|
|
|
int offset, __le32 val)
|
|
|
|
{
|
|
|
|
count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
|
|
|
|
if (count < 0)
|
|
|
|
return count;
|
|
|
|
|
|
|
|
if (offset == PCI_PM_CTRL) {
|
|
|
|
pci_power_t state;
|
|
|
|
|
|
|
|
switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
|
|
|
|
case 0:
|
|
|
|
state = PCI_D0;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
state = PCI_D1;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
state = PCI_D2;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
state = PCI_D3hot;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-02-09 13:43:30 -07:00
|
|
|
vfio_pci_set_power_state(vdev, state);
|
2013-02-18 10:10:33 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
/* Permissions for the Power Management capability */
|
|
|
|
static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
|
|
|
|
{
|
|
|
|
if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2013-02-18 10:10:33 -07:00
|
|
|
perm->writefn = vfio_pm_config_write;
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
/*
|
|
|
|
* We always virtualize the next field so we can remove
|
|
|
|
* capabilities from the chain if we want to.
|
|
|
|
*/
|
|
|
|
p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
/*
|
2013-02-18 10:10:33 -07:00
|
|
|
* Power management is defined *per function*, so we can let
|
|
|
|
* the user change power state, but we trap and initiate the
|
|
|
|
* change ourselves, so the state bits are read-only.
|
2012-07-31 08:16:24 -06:00
|
|
|
*/
|
2013-02-18 10:10:33 -07:00
|
|
|
p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
|
2012-07-31 08:16:24 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-10-27 14:53:05 -06:00
|
|
|
static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
|
|
|
|
int count, struct perm_bits *perm,
|
|
|
|
int offset, __le32 val)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
__le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
|
|
|
|
__le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
|
|
|
|
u16 addr;
|
|
|
|
u32 data;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write through to emulation. If the write includes the upper byte
|
|
|
|
* of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
|
|
|
|
* have work to do.
|
|
|
|
*/
|
|
|
|
count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
|
|
|
|
if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
|
|
|
|
offset + count <= PCI_VPD_ADDR + 1)
|
|
|
|
return count;
|
|
|
|
|
|
|
|
addr = le16_to_cpu(*paddr);
|
|
|
|
|
|
|
|
if (addr & PCI_VPD_ADDR_F) {
|
|
|
|
data = le32_to_cpu(*pdata);
|
|
|
|
if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
|
|
|
|
return count;
|
|
|
|
} else {
|
2016-05-31 21:25:52 -06:00
|
|
|
data = 0;
|
|
|
|
if (pci_read_vpd(pdev, addr, 4, &data) < 0)
|
2015-10-27 14:53:05 -06:00
|
|
|
return count;
|
|
|
|
*pdata = cpu_to_le32(data);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
|
|
|
|
* signal completion. If an error occurs above, we assume that not
|
|
|
|
* toggling this bit will induce a driver timeout.
|
|
|
|
*/
|
|
|
|
addr ^= PCI_VPD_ADDR_F;
|
|
|
|
*paddr = cpu_to_le16(addr);
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Permissions for Vital Product Data capability */
|
|
|
|
static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
|
|
|
|
{
|
|
|
|
if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
perm->writefn = vfio_vpd_config_write;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We always virtualize the next field so we can remove
|
|
|
|
* capabilities from the chain if we want to.
|
|
|
|
*/
|
|
|
|
p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Both the address and data registers are virtualized to
|
|
|
|
* enable access through the pci_vpd_read/write functions
|
|
|
|
*/
|
|
|
|
p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
/* Permissions for PCI-X capability */
|
|
|
|
static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
|
|
|
|
{
|
|
|
|
/* Alloc 24, but only 8 are used in v0 */
|
|
|
|
if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
|
|
|
|
int count, struct perm_bits *perm,
|
|
|
|
int offset, __le32 val)
|
|
|
|
{
|
|
|
|
__le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
|
|
|
|
offset + PCI_EXP_DEVCTL);
|
2017-10-02 12:39:10 -06:00
|
|
|
int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
|
|
|
|
count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
|
|
|
|
if (count < 0)
|
|
|
|
return count;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The FLR bit is virtualized, if set and the device supports PCIe
|
|
|
|
* FLR, issue a reset_function. Regardless, clear the bit, the spec
|
|
|
|
* requires it to be always read as zero. NB, reset_function might
|
|
|
|
* not use a PCIe FLR, we don't have that level of granularity.
|
|
|
|
*/
|
|
|
|
if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
|
|
|
|
u32 cap;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
|
|
|
|
|
|
|
|
ret = pci_user_read_config_dword(vdev->pdev,
|
|
|
|
pos - offset + PCI_EXP_DEVCAP,
|
|
|
|
&cap);
|
|
|
|
|
|
|
|
if (!ret && (cap & PCI_EXP_DEVCAP_FLR))
|
|
|
|
pci_try_reset_function(vdev->pdev);
|
|
|
|
}
|
|
|
|
|
2017-10-02 12:39:10 -06:00
|
|
|
/*
|
|
|
|
* MPS is virtualized to the user, writes do not change the physical
|
|
|
|
* register since determining a proper MPS value requires a system wide
|
|
|
|
* device view. The MRRS is largely independent of MPS, but since the
|
|
|
|
* user does not have that system-wide view, they might set a safe, but
|
|
|
|
* inefficiently low value. Here we allow writes through to hardware,
|
|
|
|
* but we set the floor to the physical device MPS setting, so that
|
|
|
|
* we can at least use full TLPs, as defined by the MPS value.
|
|
|
|
*
|
|
|
|
* NB, if any devices actually depend on an artificially low MRRS
|
|
|
|
* setting, this will need to be revisited, perhaps with a quirk
|
|
|
|
* though pcie_set_readrq().
|
|
|
|
*/
|
|
|
|
if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
|
|
|
|
readrq = 128 <<
|
|
|
|
((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
|
|
|
|
readrq = max(readrq, pcie_get_mps(vdev->pdev));
|
|
|
|
|
|
|
|
pcie_set_readrq(vdev->pdev, readrq);
|
|
|
|
}
|
|
|
|
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
/* Permissions for PCI Express capability */
|
|
|
|
static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
|
|
|
|
{
|
2017-07-27 10:39:33 -06:00
|
|
|
/* Alloc largest of possible sizes */
|
2012-07-31 08:16:24 -06:00
|
|
|
if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
perm->writefn = vfio_exp_config_write;
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
/*
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
* Allow writes to device control fields, except devctl_phantom,
|
2017-10-02 12:39:09 -06:00
|
|
|
* which could confuse IOMMU, MPS, which can break communication
|
|
|
|
* with other physical devices, and the ARI bit in devctl2, which
|
2017-10-02 12:39:10 -06:00
|
|
|
* is set at probe time. FLR and MRRS get virtualized via our
|
|
|
|
* writefn.
|
2012-07-31 08:16:24 -06:00
|
|
|
*/
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
p_setw(perm, PCI_EXP_DEVCTL,
|
2017-10-02 12:39:10 -06:00
|
|
|
PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
|
|
|
|
PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
|
2012-07-31 08:16:24 -06:00
|
|
|
p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
|
|
|
|
int count, struct perm_bits *perm,
|
|
|
|
int offset, __le32 val)
|
|
|
|
{
|
|
|
|
u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
|
|
|
|
|
|
|
|
count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
|
|
|
|
if (count < 0)
|
|
|
|
return count;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The FLR bit is virtualized, if set and the device supports AF
|
|
|
|
* FLR, issue a reset_function. Regardless, clear the bit, the spec
|
|
|
|
* requires it to be always read as zero. NB, reset_function might
|
|
|
|
* not use an AF FLR, we don't have that level of granularity.
|
|
|
|
*/
|
|
|
|
if (*ctrl & PCI_AF_CTRL_FLR) {
|
|
|
|
u8 cap;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*ctrl &= ~PCI_AF_CTRL_FLR;
|
|
|
|
|
|
|
|
ret = pci_user_read_config_byte(vdev->pdev,
|
|
|
|
pos - offset + PCI_AF_CAP,
|
|
|
|
&cap);
|
|
|
|
|
|
|
|
if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP))
|
|
|
|
pci_try_reset_function(vdev->pdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
/* Permissions for Advanced Function capability */
|
|
|
|
static int __init init_pci_cap_af_perm(struct perm_bits *perm)
|
|
|
|
{
|
|
|
|
if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
perm->writefn = vfio_af_config_write;
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
|
vfio-pci: Virtualize PCIe & AF FLR
We use a BAR restore trick to try to detect when a user has performed
a device reset, possibly through FLR or other backdoors, to put things
back into a working state. This is important for backdoor resets, but
we can actually just virtualize the "front door" resets provided via
PCIe and AF FLR. Set these bits as virtualized + writable, allowing
the default write to set them in vconfig, then we can simply check the
bit, perform an FLR of our own, and clear the bit. We don't actually
have the granularity in PCI to specify the type of reset we want to
do, but generally devices don't implement both PCIe and AF FLR and
we'll favor these over other types of reset, so we should generally
lineup. We do test whether the device provides the requested FLR type
to stay consistent with hardware capabilities though.
This seems to fix several instance of devices getting into bad states
with userspace drivers, like dpdk, running inside a VM.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Greg Rose <grose@lightfleet.com>
2016-09-26 13:52:16 -06:00
|
|
|
p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
|
2012-07-31 08:16:24 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Permissions for Advanced Error Reporting extended capability */
|
|
|
|
static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
|
|
|
|
{
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Virtualize the first dword of all express capabilities
|
|
|
|
* because it includes the next pointer. This lets us later
|
|
|
|
* remove capabilities from the chain if we need to.
|
|
|
|
*/
|
|
|
|
p_setd(perm, 0, ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
/* Writable bits mask */
|
2014-08-13 00:22:40 -06:00
|
|
|
mask = PCI_ERR_UNC_UND | /* Undefined */
|
2012-07-31 08:16:24 -06:00
|
|
|
PCI_ERR_UNC_DLP | /* Data Link Protocol */
|
|
|
|
PCI_ERR_UNC_SURPDN | /* Surprise Down */
|
|
|
|
PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
|
|
|
|
PCI_ERR_UNC_FCP | /* Flow Control Protocol */
|
|
|
|
PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
|
|
|
|
PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
|
|
|
|
PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
|
|
|
|
PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
|
|
|
|
PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
|
|
|
|
PCI_ERR_UNC_ECRC | /* ECRC Error Status */
|
|
|
|
PCI_ERR_UNC_UNSUP | /* Unsupported Request */
|
|
|
|
PCI_ERR_UNC_ACSV | /* ACS Violation */
|
|
|
|
PCI_ERR_UNC_INTN | /* internal error */
|
|
|
|
PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
|
|
|
|
PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
|
|
|
|
PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
|
|
|
|
p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
|
|
|
|
p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
|
|
|
|
p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
|
|
|
|
|
|
|
|
mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
|
|
|
|
PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
|
|
|
|
PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
|
|
|
|
PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
|
|
|
|
PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
|
|
|
|
PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
|
|
|
|
PCI_ERR_COR_INTERNAL | /* Corrected Internal */
|
|
|
|
PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
|
|
|
|
p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
|
|
|
|
p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
|
|
|
|
|
|
|
|
mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
|
|
|
|
PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
|
|
|
|
p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Permissions for Power Budgeting extended capability */
|
|
|
|
static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
|
|
|
|
{
|
|
|
|
if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
p_setd(perm, 0, ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
/* Writing the data selector is OK, the info is still read-only */
|
|
|
|
p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the shared permission tables
|
|
|
|
*/
|
|
|
|
void vfio_pci_uninit_perm_bits(void)
|
|
|
|
{
|
|
|
|
free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
|
|
|
|
|
|
|
|
free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
|
2015-10-27 14:53:05 -06:00
|
|
|
free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
|
2012-07-31 08:16:24 -06:00
|
|
|
free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
|
|
|
|
free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
|
|
|
|
free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
|
|
|
|
|
|
|
|
free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
|
|
|
|
free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
|
|
|
|
}
|
|
|
|
|
|
|
|
int __init vfio_pci_init_perm_bits(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Basic config space */
|
|
|
|
ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
|
|
|
|
|
|
|
|
/* Capabilities */
|
|
|
|
ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
|
2015-10-27 14:53:05 -06:00
|
|
|
ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
|
2012-07-31 08:16:24 -06:00
|
|
|
ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
|
2013-04-01 09:04:12 -06:00
|
|
|
cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
|
2012-07-31 08:16:24 -06:00
|
|
|
ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
|
|
|
|
ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
|
|
|
|
|
|
|
|
/* Extended capabilities */
|
|
|
|
ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
|
|
|
|
ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
|
2013-04-01 09:04:12 -06:00
|
|
|
ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
|
2012-07-31 08:16:24 -06:00
|
|
|
|
|
|
|
if (ret)
|
|
|
|
vfio_pci_uninit_perm_bits();
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
|
|
|
|
{
|
|
|
|
u8 cap;
|
|
|
|
int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
|
|
|
|
PCI_STD_HEADER_SIZEOF;
|
|
|
|
cap = vdev->pci_config_map[pos];
|
|
|
|
|
|
|
|
if (cap == PCI_CAP_ID_BASIC)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* XXX Can we have to abutting capabilities of the same type? */
|
|
|
|
while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
|
|
|
|
pos--;
|
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
return pos;
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
|
|
|
|
int count, struct perm_bits *perm,
|
|
|
|
int offset, __le32 *val)
|
|
|
|
{
|
|
|
|
/* Update max available queue size from msi_qmax */
|
|
|
|
if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
|
|
|
|
__le16 *flags;
|
|
|
|
int start;
|
|
|
|
|
|
|
|
start = vfio_find_cap_start(vdev, pos);
|
|
|
|
|
|
|
|
flags = (__le16 *)&vdev->vconfig[start];
|
|
|
|
|
|
|
|
*flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
|
|
|
|
*flags |= cpu_to_le16(vdev->msi_qmax << 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return vfio_default_config_read(vdev, pos, count, perm, offset, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
|
|
|
|
int count, struct perm_bits *perm,
|
|
|
|
int offset, __le32 val)
|
|
|
|
{
|
|
|
|
count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
|
|
|
|
if (count < 0)
|
|
|
|
return count;
|
|
|
|
|
|
|
|
/* Fixup and write configured queue size and enable to hardware */
|
|
|
|
if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
|
|
|
|
__le16 *pflags;
|
|
|
|
u16 flags;
|
|
|
|
int start, ret;
|
|
|
|
|
|
|
|
start = vfio_find_cap_start(vdev, pos);
|
|
|
|
|
|
|
|
pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
|
|
|
|
|
|
|
|
flags = le16_to_cpu(*pflags);
|
|
|
|
|
|
|
|
/* MSI is enabled via ioctl */
|
|
|
|
if (!is_msi(vdev))
|
|
|
|
flags &= ~PCI_MSI_FLAGS_ENABLE;
|
|
|
|
|
|
|
|
/* Check queue size */
|
|
|
|
if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
|
|
|
|
flags &= ~PCI_MSI_FLAGS_QSIZE;
|
|
|
|
flags |= vdev->msi_qmax << 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write back to virt and to hardware */
|
|
|
|
*pflags = cpu_to_le16(flags);
|
|
|
|
ret = pci_user_write_config_word(vdev->pdev,
|
|
|
|
start + PCI_MSI_FLAGS,
|
|
|
|
flags);
|
|
|
|
if (ret)
|
2016-11-18 04:47:38 -07:00
|
|
|
return ret;
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* MSI determination is per-device, so this routine gets used beyond
|
|
|
|
* initialization time. Don't add __init
|
|
|
|
*/
|
|
|
|
static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
|
|
|
|
{
|
|
|
|
if (alloc_perm_bits(perm, len))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
perm->readfn = vfio_msi_config_read;
|
|
|
|
perm->writefn = vfio_msi_config_write;
|
|
|
|
|
|
|
|
p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The upper byte of the control register is reserved,
|
|
|
|
* just setup the lower byte.
|
|
|
|
*/
|
|
|
|
p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
|
|
|
|
if (flags & PCI_MSI_FLAGS_64BIT) {
|
|
|
|
p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
|
|
|
|
p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
|
|
|
|
if (flags & PCI_MSI_FLAGS_MASKBIT) {
|
|
|
|
p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
|
|
|
|
if (flags & PCI_MSI_FLAGS_MASKBIT) {
|
|
|
|
p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
|
|
|
|
p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
|
|
|
|
static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
int len, ret;
|
|
|
|
u16 flags;
|
|
|
|
|
|
|
|
ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
len = 10; /* Minimum size */
|
|
|
|
if (flags & PCI_MSI_FLAGS_64BIT)
|
|
|
|
len += 4;
|
|
|
|
if (flags & PCI_MSI_FLAGS_MASKBIT)
|
|
|
|
len += 10;
|
|
|
|
|
|
|
|
if (vdev->msi_perm)
|
|
|
|
return len;
|
|
|
|
|
|
|
|
vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
|
|
|
|
if (!vdev->msi_perm)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
|
2018-09-25 13:01:27 -06:00
|
|
|
if (ret) {
|
|
|
|
kfree(vdev->msi_perm);
|
2012-07-31 08:16:24 -06:00
|
|
|
return ret;
|
2018-09-25 13:01:27 -06:00
|
|
|
}
|
2012-07-31 08:16:24 -06:00
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Determine extended capability length for VC (2 & 9) and MFVC */
|
|
|
|
static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
u32 tmp;
|
|
|
|
int ret, evcc, phases, vc_arb;
|
|
|
|
int len = PCI_CAP_VC_BASE_SIZEOF;
|
|
|
|
|
2013-12-17 16:43:57 -07:00
|
|
|
ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
|
2012-07-31 08:16:24 -06:00
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
2013-12-17 16:43:57 -07:00
|
|
|
evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
|
|
|
|
ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
|
2012-07-31 08:16:24 -06:00
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
2013-12-17 16:43:57 -07:00
|
|
|
if (tmp & PCI_VC_CAP2_128_PHASE)
|
2012-07-31 08:16:24 -06:00
|
|
|
phases = 128;
|
2013-12-17 16:43:57 -07:00
|
|
|
else if (tmp & PCI_VC_CAP2_64_PHASE)
|
2012-07-31 08:16:24 -06:00
|
|
|
phases = 64;
|
2013-12-17 16:43:57 -07:00
|
|
|
else if (tmp & PCI_VC_CAP2_32_PHASE)
|
2012-07-31 08:16:24 -06:00
|
|
|
phases = 32;
|
|
|
|
else
|
|
|
|
phases = 0;
|
|
|
|
|
|
|
|
vc_arb = phases * 4;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Port arbitration tables are root & switch only;
|
|
|
|
* function arbitration tables are function 0 only.
|
|
|
|
* In either case, we'll never let user write them so
|
|
|
|
* we don't care how big they are
|
|
|
|
*/
|
|
|
|
len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
|
|
|
|
if (vc_arb) {
|
|
|
|
len = round_up(len, 16);
|
|
|
|
len += vc_arb / 8;
|
|
|
|
}
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
2013-09-04 10:58:52 -06:00
|
|
|
u32 dword;
|
2012-07-31 08:16:24 -06:00
|
|
|
u16 word;
|
|
|
|
u8 byte;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (cap) {
|
|
|
|
case PCI_CAP_ID_MSI:
|
|
|
|
return vfio_msi_cap_len(vdev, pos);
|
|
|
|
case PCI_CAP_ID_PCIX:
|
|
|
|
ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
if (PCI_X_CMD_VERSION(word)) {
|
2016-04-28 22:11:52 -06:00
|
|
|
if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
|
|
|
|
/* Test for extended capabilities */
|
|
|
|
pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
|
|
|
|
&dword);
|
|
|
|
vdev->extended_caps = (dword != 0);
|
|
|
|
}
|
2012-07-31 08:16:24 -06:00
|
|
|
return PCI_CAP_PCIX_SIZEOF_V2;
|
|
|
|
} else
|
|
|
|
return PCI_CAP_PCIX_SIZEOF_V0;
|
|
|
|
case PCI_CAP_ID_VNDR:
|
|
|
|
/* length follows next field */
|
|
|
|
ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
return byte;
|
|
|
|
case PCI_CAP_ID_EXP:
|
2016-04-28 22:11:52 -06:00
|
|
|
if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
|
|
|
|
/* Test for extended capabilities */
|
|
|
|
pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
|
|
|
|
vdev->extended_caps = (dword != 0);
|
|
|
|
}
|
2013-02-14 10:45:31 -07:00
|
|
|
|
2017-07-27 10:39:33 -06:00
|
|
|
/* length based on version and type */
|
|
|
|
if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) {
|
|
|
|
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
|
|
|
|
return 0xc; /* "All Devices" only, no link */
|
2012-07-31 08:16:24 -06:00
|
|
|
return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
|
2017-07-27 10:39:33 -06:00
|
|
|
} else {
|
|
|
|
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
|
|
|
|
return 0x2c; /* No link */
|
2012-07-31 08:16:24 -06:00
|
|
|
return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
|
2017-07-27 10:39:33 -06:00
|
|
|
}
|
2012-07-31 08:16:24 -06:00
|
|
|
case PCI_CAP_ID_HT:
|
|
|
|
ret = pci_read_config_byte(pdev, pos + 3, &byte);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
return (byte & HT_3BIT_CAP_MASK) ?
|
|
|
|
HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
|
|
|
|
case PCI_CAP_ID_SATA:
|
|
|
|
ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
byte &= PCI_SATA_REGS_MASK;
|
|
|
|
if (byte == PCI_SATA_REGS_INLINE)
|
|
|
|
return PCI_SATA_SIZEOF_LONG;
|
|
|
|
else
|
|
|
|
return PCI_SATA_SIZEOF_SHORT;
|
|
|
|
default:
|
2019-03-30 08:41:35 -06:00
|
|
|
pci_warn(pdev, "%s: unknown length for PCI cap %#x@%#x\n",
|
|
|
|
__func__, cap, pos);
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
u8 byte;
|
|
|
|
u32 dword;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (ecap) {
|
|
|
|
case PCI_EXT_CAP_ID_VNDR:
|
|
|
|
ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
return dword >> PCI_VSEC_HDR_LEN_SHIFT;
|
|
|
|
case PCI_EXT_CAP_ID_VC:
|
|
|
|
case PCI_EXT_CAP_ID_VC9:
|
|
|
|
case PCI_EXT_CAP_ID_MFVC:
|
|
|
|
return vfio_vc_cap_len(vdev, epos);
|
|
|
|
case PCI_EXT_CAP_ID_ACS:
|
|
|
|
ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
if (byte & PCI_ACS_EC) {
|
|
|
|
int bits;
|
|
|
|
|
|
|
|
ret = pci_read_config_byte(pdev,
|
|
|
|
epos + PCI_ACS_EGRESS_BITS,
|
|
|
|
&byte);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
bits = byte ? round_up(byte, 32) : 256;
|
|
|
|
return 8 + (bits / 8);
|
|
|
|
}
|
|
|
|
return 8;
|
|
|
|
|
|
|
|
case PCI_EXT_CAP_ID_REBAR:
|
|
|
|
ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
byte &= PCI_REBAR_CTRL_NBAR_MASK;
|
|
|
|
byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
|
|
|
|
|
|
|
|
return 4 + (byte * 8);
|
|
|
|
case PCI_EXT_CAP_ID_DPA:
|
|
|
|
ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
byte &= PCI_DPA_CAP_SUBSTATE_MASK;
|
2014-05-30 10:50:31 -06:00
|
|
|
return PCI_DPA_BASE_SIZEOF + byte + 1;
|
2012-07-31 08:16:24 -06:00
|
|
|
case PCI_EXT_CAP_ID_TPH:
|
|
|
|
ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
|
|
|
|
if (ret)
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
|
|
|
|
if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
|
|
|
|
int sts;
|
|
|
|
|
2014-05-30 10:50:31 -06:00
|
|
|
sts = dword & PCI_TPH_CAP_ST_MASK;
|
2012-07-31 08:16:24 -06:00
|
|
|
sts >>= PCI_TPH_CAP_ST_SHIFT;
|
2014-05-30 10:50:31 -06:00
|
|
|
return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
return PCI_TPH_BASE_SIZEOF;
|
|
|
|
default:
|
2019-03-30 08:41:35 -06:00
|
|
|
pci_warn(pdev, "%s: unknown length for PCI ecap %#x@%#x\n",
|
|
|
|
__func__, ecap, epos);
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
|
|
|
|
int offset, int size)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We try to read physical config space in the largest chunks
|
|
|
|
* we can, assuming that all of the fields support dword access.
|
|
|
|
* pci_save_state() makes this same assumption and seems to do ok.
|
|
|
|
*/
|
|
|
|
while (size) {
|
|
|
|
int filled;
|
|
|
|
|
|
|
|
if (size >= 4 && !(offset % 4)) {
|
|
|
|
__le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
|
|
|
|
u32 dword;
|
|
|
|
|
|
|
|
ret = pci_read_config_dword(pdev, offset, &dword);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*dwordp = cpu_to_le32(dword);
|
|
|
|
filled = 4;
|
|
|
|
} else if (size >= 2 && !(offset % 2)) {
|
|
|
|
__le16 *wordp = (__le16 *)&vdev->vconfig[offset];
|
|
|
|
u16 word;
|
|
|
|
|
|
|
|
ret = pci_read_config_word(pdev, offset, &word);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*wordp = cpu_to_le16(word);
|
|
|
|
filled = 2;
|
|
|
|
} else {
|
|
|
|
u8 *byte = &vdev->vconfig[offset];
|
|
|
|
ret = pci_read_config_byte(pdev, offset, byte);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
filled = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset += filled;
|
|
|
|
size -= filled;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_cap_init(struct vfio_pci_device *vdev)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
u8 *map = vdev->pci_config_map;
|
|
|
|
u16 status;
|
|
|
|
u8 pos, *prev, cap;
|
|
|
|
int loops, ret, caps = 0;
|
|
|
|
|
|
|
|
/* Any capabilities? */
|
|
|
|
ret = pci_read_config_word(pdev, PCI_STATUS, &status);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (!(status & PCI_STATUS_CAP_LIST))
|
|
|
|
return 0; /* Done */
|
|
|
|
|
|
|
|
ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Mark the previous position in case we want to skip a capability */
|
|
|
|
prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
|
|
|
|
|
|
|
|
/* We can bound our loop, capabilities are dword aligned */
|
|
|
|
loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
|
|
|
|
while (pos && loops--) {
|
|
|
|
u8 next;
|
|
|
|
int i, len = 0;
|
|
|
|
|
|
|
|
ret = pci_read_config_byte(pdev, pos, &cap);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = pci_read_config_byte(pdev,
|
|
|
|
pos + PCI_CAP_LIST_NEXT, &next);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (cap <= PCI_CAP_ID_MAX) {
|
|
|
|
len = pci_cap_length[cap];
|
|
|
|
if (len == 0xFF) { /* Variable length */
|
|
|
|
len = vfio_cap_len(vdev, cap, pos);
|
|
|
|
if (len < 0)
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!len) {
|
2019-03-30 08:41:35 -06:00
|
|
|
pci_info(pdev, "%s: hiding cap %#x@%#x\n", __func__,
|
|
|
|
cap, pos);
|
2012-07-31 08:16:24 -06:00
|
|
|
*prev = next;
|
|
|
|
pos = next;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Sanity check, do we overlap other capabilities? */
|
2013-04-01 09:03:44 -06:00
|
|
|
for (i = 0; i < len; i++) {
|
|
|
|
if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
|
2012-07-31 08:16:24 -06:00
|
|
|
continue;
|
|
|
|
|
2019-03-30 08:41:35 -06:00
|
|
|
pci_warn(pdev, "%s: PCI config conflict @%#x, was cap %#x now cap %#x\n",
|
|
|
|
__func__, pos + i, map[pos + i], cap);
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
2016-02-22 16:02:41 -07:00
|
|
|
BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
|
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
memset(map + pos, cap, len);
|
2012-07-31 08:16:24 -06:00
|
|
|
ret = vfio_fill_vconfig_bytes(vdev, pos, len);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
|
|
|
|
pos = next;
|
|
|
|
caps++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If we didn't fill any capabilities, clear the status flag */
|
|
|
|
if (!caps) {
|
|
|
|
__le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
|
|
|
|
*vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vfio_ecap_init(struct vfio_pci_device *vdev)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
u8 *map = vdev->pci_config_map;
|
|
|
|
u16 epos;
|
|
|
|
__le32 *prev = NULL;
|
|
|
|
int loops, ret, ecaps = 0;
|
|
|
|
|
|
|
|
if (!vdev->extended_caps)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
epos = PCI_CFG_SPACE_SIZE;
|
|
|
|
|
|
|
|
loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
|
|
|
|
|
|
|
|
while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
|
|
|
|
u32 header;
|
|
|
|
u16 ecap;
|
|
|
|
int i, len = 0;
|
|
|
|
bool hidden = false;
|
|
|
|
|
|
|
|
ret = pci_read_config_dword(pdev, epos, &header);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ecap = PCI_EXT_CAP_ID(header);
|
|
|
|
|
|
|
|
if (ecap <= PCI_EXT_CAP_ID_MAX) {
|
|
|
|
len = pci_ext_cap_length[ecap];
|
|
|
|
if (len == 0xFF) {
|
|
|
|
len = vfio_ext_cap_len(vdev, ecap, epos);
|
|
|
|
if (len < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!len) {
|
2019-03-30 08:41:35 -06:00
|
|
|
pci_info(pdev, "%s: hiding ecap %#x@%#x\n",
|
|
|
|
__func__, ecap, epos);
|
2012-07-31 08:16:24 -06:00
|
|
|
|
|
|
|
/* If not the first in the chain, we can skip over it */
|
|
|
|
if (prev) {
|
|
|
|
u32 val = epos = PCI_EXT_CAP_NEXT(header);
|
|
|
|
*prev &= cpu_to_le32(~(0xffcU << 20));
|
|
|
|
*prev |= cpu_to_le32(val << 20);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Otherwise, fill in a placeholder, the direct
|
|
|
|
* readfn will virtualize this automatically
|
|
|
|
*/
|
|
|
|
len = PCI_CAP_SIZEOF;
|
|
|
|
hidden = true;
|
|
|
|
}
|
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
for (i = 0; i < len; i++) {
|
|
|
|
if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
|
2012-07-31 08:16:24 -06:00
|
|
|
continue;
|
|
|
|
|
2019-03-30 08:41:35 -06:00
|
|
|
pci_warn(pdev, "%s: PCI config conflict @%#x, was ecap %#x now ecap %#x\n",
|
|
|
|
__func__, epos + i, map[epos + i], ecap);
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Even though ecap is 2 bytes, we're currently a long way
|
|
|
|
* from exceeding 1 byte capabilities. If we ever make it
|
2016-02-22 16:02:41 -07:00
|
|
|
* up to 0xFE we'll need to up this to a two-byte, byte map.
|
2012-07-31 08:16:24 -06:00
|
|
|
*/
|
2016-02-22 16:02:41 -07:00
|
|
|
BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
memset(map + epos, ecap, len);
|
2012-07-31 08:16:24 -06:00
|
|
|
ret = vfio_fill_vconfig_bytes(vdev, epos, len);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we're just using this capability to anchor the list,
|
|
|
|
* hide the real ID. Only count real ecaps. XXX PCI spec
|
|
|
|
* indicates to use cap id = 0, version = 0, next = 0 if
|
|
|
|
* ecaps are absent, hope users check all the way to next.
|
|
|
|
*/
|
|
|
|
if (hidden)
|
|
|
|
*(__le32 *)&vdev->vconfig[epos] &=
|
|
|
|
cpu_to_le32((0xffcU << 20));
|
|
|
|
else
|
|
|
|
ecaps++;
|
|
|
|
|
|
|
|
prev = (__le32 *)&vdev->vconfig[epos];
|
|
|
|
epos = PCI_EXT_CAP_NEXT(header);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!ecaps)
|
|
|
|
*(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-09-25 13:01:27 -06:00
|
|
|
/*
|
|
|
|
* Nag about hardware bugs, hopefully to have vendors fix them, but at least
|
|
|
|
* to collect a list of dependencies for the VF INTx pin quirk below.
|
|
|
|
*/
|
|
|
|
static const struct pci_device_id known_bogus_vf_intx_pin[] = {
|
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
/*
|
|
|
|
* For each device we allocate a pci_config_map that indicates the
|
|
|
|
* capability occupying each dword and thus the struct perm_bits we
|
|
|
|
* use for read and write. We also allocate a virtualized config
|
|
|
|
* space which tracks reads and writes to bits that we emulate for
|
|
|
|
* the user. Initial values filled from device.
|
|
|
|
*
|
2016-08-17 00:37:05 -06:00
|
|
|
* Using shared struct perm_bits between all vfio-pci devices saves
|
2012-07-31 08:16:24 -06:00
|
|
|
* us from allocating cfg_size buffers for virt and write for every
|
|
|
|
* device. We could remove vconfig and allocate individual buffers
|
2016-08-17 00:37:05 -06:00
|
|
|
* for each area requiring emulated bits, but the array of pointers
|
2012-07-31 08:16:24 -06:00
|
|
|
* would be comparable in size (at least for standard config space).
|
|
|
|
*/
|
|
|
|
int vfio_config_init(struct vfio_pci_device *vdev)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
u8 *map, *vconfig;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
2013-04-01 09:03:44 -06:00
|
|
|
* Config space, caps and ecaps are all dword aligned, so we could
|
|
|
|
* use one byte per dword to record the type. However, there are
|
|
|
|
* no requiremenst on the length of a capability, so the gap between
|
|
|
|
* capabilities needs byte granularity.
|
2012-07-31 08:16:24 -06:00
|
|
|
*/
|
2013-04-01 09:03:44 -06:00
|
|
|
map = kmalloc(pdev->cfg_size, GFP_KERNEL);
|
2012-07-31 08:16:24 -06:00
|
|
|
if (!map)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
|
|
|
|
if (!vconfig) {
|
|
|
|
kfree(map);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
vdev->pci_config_map = map;
|
|
|
|
vdev->vconfig = vconfig;
|
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
|
|
|
|
memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
|
|
|
|
pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
|
2012-07-31 08:16:24 -06:00
|
|
|
|
|
|
|
ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
vdev->bardirty = true;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX can we just pci_load_saved_state/pci_restore_state?
|
|
|
|
* may need to rebuild vconfig after that
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* For restore after reset */
|
|
|
|
vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
|
|
|
|
vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
|
|
|
|
vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
|
|
|
|
vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
|
|
|
|
vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
|
|
|
|
vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
|
|
|
|
vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
|
|
|
|
|
|
|
|
if (pdev->is_virtfn) {
|
|
|
|
*(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
|
|
|
|
*(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
|
2018-09-25 13:01:27 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
|
|
|
|
* does not apply to VFs and VFs must implement this register
|
|
|
|
* as read-only with value zero. Userspace is not readily able
|
|
|
|
* to identify whether a device is a VF and thus that the pin
|
|
|
|
* definition on the device is bogus should it violate this
|
|
|
|
* requirement. We already virtualize the pin register for
|
|
|
|
* other purposes, so we simply need to replace the bogus value
|
|
|
|
* and consider VFs when we determine INTx IRQ count.
|
|
|
|
*/
|
|
|
|
if (vconfig[PCI_INTERRUPT_PIN] &&
|
|
|
|
!pci_match_id(known_bogus_vf_intx_pin, pdev))
|
|
|
|
pci_warn(pdev,
|
|
|
|
"Hardware bug: VF reports bogus INTx pin %d\n",
|
|
|
|
vconfig[PCI_INTERRUPT_PIN]);
|
|
|
|
|
|
|
|
vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
vfio/pci: Hide broken INTx support from user
INTx masking has two components, the first is that we need the ability
to prevent the device from continuing to assert INTx. This is
provided via the DisINTx bit in the command register and is the only
thing we can really probe for when testing if INTx masking is
supported. The second component is that the device needs to indicate
if INTx is asserted via the interrupt status bit in the device status
register. With these two features we can generically determine if one
of the devices we own is asserting INTx, signal the user, and mask the
interrupt while the user services the device.
Generally if one or both of these components is broken we resort to
APIC level interrupt masking, which requires an exclusive interrupt
since we have no way to determine the source of the interrupt in a
shared configuration. This often makes it difficult or impossible to
configure the system for userspace use of the device, for an interrupt
mode that the user may not need.
One possible configuration of broken INTx masking is that the DisINTx
support is fully functional, but the interrupt status bit never
signals interrupt assertion. In this case we do have the ability to
prevent the device from asserting INTx, but lack the ability to
identify the interrupt source. For this case we can simply pretend
that the device lacks INTx support entirely, keeping DisINTx set on
the physical device, virtualizing this bit for the user, and
virtualizing the interrupt pin register to indicate no INTx support.
We already support virtualization of the DisINTx bit and already
virtualize the interrupt pin for platforms without INTx support. By
tying these components together, setting DisINTx on open and reset,
and identifying devices broken in this particular way, we can provide
support for them w/o the handicap of APIC level INTx masking.
Intel i40e (XL710/X710) 10/20/40GbE NICs have been identified as being
broken in this specific way. We leave the vfio-pci.nointxmask option
as a mechanism to bypass this support, enabling INTx on the device
with all the requirements of APIC level masking.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Cc: John Ronciak <john.ronciak@intel.com>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
2016-03-24 13:05:18 -06:00
|
|
|
if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
|
2014-11-07 09:52:22 -07:00
|
|
|
vconfig[PCI_INTERRUPT_PIN] = 0;
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
ret = vfio_cap_init(vdev);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = vfio_ecap_init(vdev);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out:
|
|
|
|
kfree(map);
|
|
|
|
vdev->pci_config_map = NULL;
|
|
|
|
kfree(vconfig);
|
|
|
|
vdev->vconfig = NULL;
|
|
|
|
return pcibios_err_to_errno(ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
void vfio_config_free(struct vfio_pci_device *vdev)
|
|
|
|
{
|
|
|
|
kfree(vdev->vconfig);
|
|
|
|
vdev->vconfig = NULL;
|
|
|
|
kfree(vdev->pci_config_map);
|
|
|
|
vdev->pci_config_map = NULL;
|
|
|
|
kfree(vdev->msi_perm);
|
|
|
|
vdev->msi_perm = NULL;
|
|
|
|
}
|
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
/*
|
|
|
|
* Find the remaining number of bytes in a dword that match the given
|
|
|
|
* position. Stop at either the end of the capability or the dword boundary.
|
|
|
|
*/
|
|
|
|
static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
|
|
|
|
loff_t pos)
|
|
|
|
{
|
|
|
|
u8 cap = vdev->pci_config_map[pos];
|
|
|
|
size_t i;
|
|
|
|
|
|
|
|
for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
|
|
|
|
/* nop */;
|
|
|
|
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
2012-07-31 08:16:24 -06:00
|
|
|
static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
|
|
|
|
size_t count, loff_t *ppos, bool iswrite)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = vdev->pdev;
|
|
|
|
struct perm_bits *perm;
|
|
|
|
__le32 val = 0;
|
|
|
|
int cap_start = 0, offset;
|
|
|
|
u8 cap_id;
|
2013-04-01 09:03:44 -06:00
|
|
|
ssize_t ret;
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
if (*ppos < 0 || *ppos >= pdev->cfg_size ||
|
|
|
|
*ppos + count > pdev->cfg_size)
|
2012-07-31 08:16:24 -06:00
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
/*
|
2013-04-01 09:03:44 -06:00
|
|
|
* Chop accesses into aligned chunks containing no more than a
|
|
|
|
* single capability. Caller increments to the next chunk.
|
2012-07-31 08:16:24 -06:00
|
|
|
*/
|
2013-04-01 09:03:44 -06:00
|
|
|
count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
|
|
|
|
if (count >= 4 && !(*ppos % 4))
|
|
|
|
count = 4;
|
|
|
|
else if (count >= 2 && !(*ppos % 2))
|
|
|
|
count = 2;
|
|
|
|
else
|
|
|
|
count = 1;
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
ret = count;
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2013-04-01 09:03:44 -06:00
|
|
|
cap_id = vdev->pci_config_map[*ppos];
|
2012-07-31 08:16:24 -06:00
|
|
|
|
|
|
|
if (cap_id == PCI_CAP_ID_INVALID) {
|
2013-04-01 09:04:12 -06:00
|
|
|
perm = &unassigned_perms;
|
|
|
|
cap_start = *ppos;
|
2016-02-22 16:02:41 -07:00
|
|
|
} else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
|
|
|
|
perm = &virt_perms;
|
|
|
|
cap_start = *ppos;
|
2012-07-31 08:16:24 -06:00
|
|
|
} else {
|
2013-04-01 09:04:12 -06:00
|
|
|
if (*ppos >= PCI_CFG_SPACE_SIZE) {
|
|
|
|
WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2013-04-01 09:04:12 -06:00
|
|
|
perm = &ecap_perms[cap_id];
|
|
|
|
cap_start = vfio_find_cap_start(vdev, *ppos);
|
|
|
|
} else {
|
|
|
|
WARN_ON(cap_id > PCI_CAP_ID_MAX);
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2013-04-01 09:04:12 -06:00
|
|
|
perm = &cap_perms[cap_id];
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2013-04-01 09:04:12 -06:00
|
|
|
if (cap_id == PCI_CAP_ID_MSI)
|
|
|
|
perm = vdev->msi_perm;
|
2012-07-31 08:16:24 -06:00
|
|
|
|
2013-04-01 09:04:12 -06:00
|
|
|
if (cap_id > PCI_CAP_ID_BASIC)
|
|
|
|
cap_start = vfio_find_cap_start(vdev, *ppos);
|
|
|
|
}
|
2012-07-31 08:16:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
|
|
|
|
WARN_ON(cap_start > *ppos);
|
|
|
|
|
|
|
|
offset = *ppos - cap_start;
|
|
|
|
|
|
|
|
if (iswrite) {
|
|
|
|
if (!perm->writefn)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (copy_from_user(&val, buf, count))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
|
|
|
|
} else {
|
|
|
|
if (perm->readfn) {
|
|
|
|
ret = perm->readfn(vdev, *ppos, count,
|
|
|
|
perm, offset, &val);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (copy_to_user(buf, &val, count))
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-02-14 14:02:12 -07:00
|
|
|
ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
|
|
|
|
size_t count, loff_t *ppos, bool iswrite)
|
2012-07-31 08:16:24 -06:00
|
|
|
{
|
|
|
|
size_t done = 0;
|
|
|
|
int ret = 0;
|
|
|
|
loff_t pos = *ppos;
|
|
|
|
|
|
|
|
pos &= VFIO_PCI_OFFSET_MASK;
|
|
|
|
|
|
|
|
while (count) {
|
2013-04-01 09:03:44 -06:00
|
|
|
ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);
|
2012-07-31 08:16:24 -06:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
count -= ret;
|
|
|
|
done += ret;
|
|
|
|
buf += ret;
|
|
|
|
pos += ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
*ppos += done;
|
|
|
|
|
|
|
|
return done;
|
|
|
|
}
|