2009-04-25 08:30:44 -06:00
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/*
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* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*
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* File: mac.h
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*
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* Purpose: MAC routines
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*
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* Author: Tevin Chen
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*
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* Date: May 21, 1996
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2009-08-12 15:54:03 -06:00
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*
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2009-04-25 08:30:44 -06:00
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* Revision History:
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* 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
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* 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
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* 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
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*/
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#ifndef __MAC_H__
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#define __MAC_H__
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#include "ttype.h"
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#include "tmacro.h"
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#include "upc.h"
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/*--------------------- Export Definitions -------------------------*/
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//
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// Registers in the MAC
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//
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#define MAC_MAX_CONTEXT_SIZE_PAGE0 256
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#define MAC_MAX_CONTEXT_SIZE_PAGE1 128
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#define MAC_MAX_CONTEXT_SIZE MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1
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// Registers not related to 802.11b
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#define MAC_REG_BCFG0 0x00
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#define MAC_REG_BCFG1 0x01
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#define MAC_REG_FCR0 0x02
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#define MAC_REG_FCR1 0x03
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#define MAC_REG_BISTCMD 0x04
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#define MAC_REG_BISTSR0 0x05
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#define MAC_REG_BISTSR1 0x06
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#define MAC_REG_BISTSR2 0x07
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#define MAC_REG_I2MCSR 0x08
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#define MAC_REG_I2MTGID 0x09
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#define MAC_REG_I2MTGAD 0x0A
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#define MAC_REG_I2MCFG 0x0B
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#define MAC_REG_I2MDIPT 0x0C
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#define MAC_REG_I2MDOPT 0x0E
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#define MAC_REG_PMC0 0x10
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#define MAC_REG_PMC1 0x11
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#define MAC_REG_STICKHW 0x12
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#define MAC_REG_LOCALID 0x14
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#define MAC_REG_TESTCFG 0x15
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#define MAC_REG_JUMPER0 0x16
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#define MAC_REG_JUMPER1 0x17
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#define MAC_REG_TMCTL0 0x18
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#define MAC_REG_TMCTL1 0x19
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#define MAC_REG_TMDATA0 0x1C
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// MAC Parameter related
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#define MAC_REG_LRT 0x20 //
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#define MAC_REG_SRT 0x21 //
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#define MAC_REG_SIFS 0x22 //
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#define MAC_REG_DIFS 0x23 //
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#define MAC_REG_EIFS 0x24 //
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#define MAC_REG_SLOT 0x25 //
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#define MAC_REG_BI 0x26 //
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#define MAC_REG_CWMAXMIN0 0x28 //
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#define MAC_REG_LINKOFFTOTM 0x2A
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#define MAC_REG_SWTMOT 0x2B
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#define MAC_REG_MIBCNTR 0x2C
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#define MAC_REG_RTSOKCNT 0x2C
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#define MAC_REG_RTSFAILCNT 0x2D
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#define MAC_REG_ACKFAILCNT 0x2E
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#define MAC_REG_FCSERRCNT 0x2F
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// TSF Related
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#define MAC_REG_TSFCNTR 0x30 //
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#define MAC_REG_NEXTTBTT 0x38 //
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#define MAC_REG_TSFOFST 0x40 //
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#define MAC_REG_TFTCTL 0x48 //
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// WMAC Control/Status Related
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#define MAC_REG_ENCFG 0x4C //
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#define MAC_REG_PAGE1SEL 0x4F //
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#define MAC_REG_CFG 0x50 //
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#define MAC_REG_TEST 0x52 //
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#define MAC_REG_HOSTCR 0x54 //
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#define MAC_REG_MACCR 0x55 //
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#define MAC_REG_RCR 0x56 //
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#define MAC_REG_TCR 0x57 //
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#define MAC_REG_IMR 0x58 //
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#define MAC_REG_ISR 0x5C
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// Power Saving Related
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#define MAC_REG_PSCFG 0x60 //
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#define MAC_REG_PSCTL 0x61 //
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#define MAC_REG_PSPWRSIG 0x62 //
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#define MAC_REG_BBCR13 0x63
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#define MAC_REG_AIDATIM 0x64
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#define MAC_REG_PWBT 0x66
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#define MAC_REG_WAKEOKTMR 0x68
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#define MAC_REG_CALTMR 0x69
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#define MAC_REG_SYNSPACCNT 0x6A
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#define MAC_REG_WAKSYNOPT 0x6B
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// Baseband/IF Control Group
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#define MAC_REG_BBREGCTL 0x6C //
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#define MAC_REG_CHANNEL 0x6D
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#define MAC_REG_BBREGADR 0x6E
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#define MAC_REG_BBREGDATA 0x6F
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#define MAC_REG_IFREGCTL 0x70 //
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#define MAC_REG_IFDATA 0x71 //
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#define MAC_REG_ITRTMSET 0x74 //
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2009-08-12 15:54:03 -06:00
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#define MAC_REG_PAPEDELAY 0x77
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2009-04-25 08:30:44 -06:00
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#define MAC_REG_SOFTPWRCTL 0x78 //
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#define MAC_REG_GPIOCTL0 0x7A //
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#define MAC_REG_GPIOCTL1 0x7B //
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// MAC DMA Related Group
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#define MAC_REG_TXDMACTL0 0x7C //
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#define MAC_REG_TXDMAPTR0 0x80 //
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#define MAC_REG_AC0DMACTL 0x84 //
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#define MAC_REG_AC0DMAPTR 0x88 //
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#define MAC_REG_BCNDMACTL 0x8C //
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#define MAC_REG_BCNDMAPTR 0x90 //
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#define MAC_REG_RXDMACTL0 0x94 //
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#define MAC_REG_RXDMAPTR0 0x98 //
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#define MAC_REG_RXDMACTL1 0x9C //
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#define MAC_REG_RXDMAPTR1 0xA0 //
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#define MAC_REG_SYNCDMACTL 0xA4 //
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#define MAC_REG_SYNCDMAPTR 0xA8
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#define MAC_REG_ATIMDMACTL 0xAC
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#define MAC_REG_ATIMDMAPTR 0xB0
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// MiscFF PIO related
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#define MAC_REG_MISCFFNDEX 0xB4
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#define MAC_REG_MISCFFCTL 0xB6
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#define MAC_REG_MISCFFDATA 0xB8
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// Extend SW Timer
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#define MAC_REG_TMDATA1 0xBC
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// WOW Related Group
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#define MAC_REG_WAKEUPEN0 0xC0
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#define MAC_REG_WAKEUPEN1 0xC1
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#define MAC_REG_WAKEUPSR0 0xC2
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#define MAC_REG_WAKEUPSR1 0xC3
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#define MAC_REG_WAKE128_0 0xC4
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#define MAC_REG_WAKE128_1 0xD4
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#define MAC_REG_WAKE128_2 0xE4
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#define MAC_REG_WAKE128_3 0xF4
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/////////////// Page 1 ///////////////////
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#define MAC_REG_CRC_128_0 0x04
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#define MAC_REG_CRC_128_1 0x06
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#define MAC_REG_CRC_128_2 0x08
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#define MAC_REG_CRC_128_3 0x0A
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// MAC Configuration Group
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#define MAC_REG_PAR0 0x0C
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#define MAC_REG_PAR4 0x10
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#define MAC_REG_BSSID0 0x14
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#define MAC_REG_BSSID4 0x18
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#define MAC_REG_MAR0 0x1C
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#define MAC_REG_MAR4 0x20
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// MAC RSPPKT INFO Group
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#define MAC_REG_RSPINF_B_1 0x24
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#define MAC_REG_RSPINF_B_2 0x28
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#define MAC_REG_RSPINF_B_5 0x2C
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#define MAC_REG_RSPINF_B_11 0x30
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#define MAC_REG_RSPINF_A_6 0x34
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#define MAC_REG_RSPINF_A_9 0x36
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#define MAC_REG_RSPINF_A_12 0x38
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#define MAC_REG_RSPINF_A_18 0x3A
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#define MAC_REG_RSPINF_A_24 0x3C
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#define MAC_REG_RSPINF_A_36 0x3E
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#define MAC_REG_RSPINF_A_48 0x40
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#define MAC_REG_RSPINF_A_54 0x42
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#define MAC_REG_RSPINF_A_72 0x44
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// 802.11h relative
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#define MAC_REG_QUIETINIT 0x60
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#define MAC_REG_QUIETGAP 0x62
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#define MAC_REG_QUIETDUR 0x64
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#define MAC_REG_MSRCTL 0x66
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#define MAC_REG_MSRBBSTS 0x67
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#define MAC_REG_MSRSTART 0x68
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#define MAC_REG_MSRDURATION 0x70
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#define MAC_REG_CCAFRACTION 0x72
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#define MAC_REG_PWRCCK 0x73
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#define MAC_REG_PWROFDM 0x7C
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//
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// Bits in the BCFG0 register
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//
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#define BCFG0_PERROFF 0x40
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#define BCFG0_MRDMDIS 0x20
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#define BCFG0_MRDLDIS 0x10
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#define BCFG0_MWMEN 0x08
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#define BCFG0_VSERREN 0x02
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#define BCFG0_LATMEN 0x01
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//
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// Bits in the BCFG1 register
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//
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#define BCFG1_CFUNOPT 0x80
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#define BCFG1_CREQOPT 0x40
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#define BCFG1_DMA8 0x10
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#define BCFG1_ARBITOPT 0x08
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#define BCFG1_PCIMEN 0x04
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#define BCFG1_MIOEN 0x02
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#define BCFG1_CISDLYEN 0x01
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// Bits in RAMBIST registers
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#define BISTCMD_TSTPAT5 0x00 //
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#define BISTCMD_TSTPATA 0x80 //
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#define BISTCMD_TSTERR 0x20 //
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#define BISTCMD_TSTPATF 0x18 //
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#define BISTCMD_TSTPAT0 0x10 //
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#define BISTCMD_TSTMODE 0x04 //
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#define BISTCMD_TSTITTX 0x03 //
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#define BISTCMD_TSTATRX 0x02 //
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#define BISTCMD_TSTATTX 0x01 //
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#define BISTCMD_TSTRX 0x00 //
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#define BISTSR0_BISTGO 0x01 //
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#define BISTSR1_TSTSR 0x01 //
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#define BISTSR2_CMDPRTEN 0x02 //
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#define BISTSR2_RAMTSTEN 0x01 //
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//
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// Bits in the I2MCFG EEPROM register
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//
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#define I2MCFG_BOUNDCTL 0x80
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#define I2MCFG_WAITCTL 0x20
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#define I2MCFG_SCLOECTL 0x10
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#define I2MCFG_WBUSYCTL 0x08
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#define I2MCFG_NORETRY 0x04
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#define I2MCFG_I2MLDSEQ 0x02
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#define I2MCFG_I2CMFAST 0x01
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//
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// Bits in the I2MCSR EEPROM register
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//
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#define I2MCSR_EEMW 0x80
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#define I2MCSR_EEMR 0x40
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#define I2MCSR_AUTOLD 0x08
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#define I2MCSR_NACK 0x02
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#define I2MCSR_DONE 0x01
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//
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// Bits in the PMC1 register
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//
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#define SPS_RST 0x80
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#define PCISTIKY 0x40
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#define PME_OVR 0x02
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//
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// Bits in the STICKYHW register
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//
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#define STICKHW_DS1_SHADOW 0x02
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#define STICKHW_DS0_SHADOW 0x01
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//
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// Bits in the TMCTL register
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//
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#define TMCTL_TSUSP 0x04
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#define TMCTL_TMD 0x02
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#define TMCTL_TE 0x01
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//
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// Bits in the TFTCTL register
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//
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#define TFTCTL_HWUTSF 0x80 //
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#define TFTCTL_TBTTSYNC 0x40
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#define TFTCTL_HWUTSFEN 0x20
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#define TFTCTL_TSFCNTRRD 0x10 //
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#define TFTCTL_TBTTSYNCEN 0x08 //
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#define TFTCTL_TSFSYNCEN 0x04 //
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#define TFTCTL_TSFCNTRST 0x02 //
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#define TFTCTL_TSFCNTREN 0x01 //
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//
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// Bits in the EnhanceCFG register
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//
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#define EnCFG_BarkerPream 0x00020000
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#define EnCFG_NXTBTTCFPSTR 0x00010000
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//#define EnCFG_TXLMT3UPDATE 0x00008000
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//#define EnCFG_TXLMT2UPDATE 0x00004000
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//#define EnCFG_TXLMT1UPDATE 0x00002000
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//#define EnCFG_TXLMT3EN 0x00001000
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//#define EnCFG_TXLMT2EN 0x00000800
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//#define EnCFG_TXLMT1EN 0x00000400
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#define EnCFG_BcnSusClr 0x00000200
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#define EnCFG_BcnSusInd 0x00000100
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//#define EnCFG_CWOFF1 0x00000080
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#define EnCFG_CFP_ProtectEn 0x00000040
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#define EnCFG_ProtectMd 0x00000020
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#define EnCFG_HwParCFP 0x00000010
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//#define EnCFG_QOS 0x00000008
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#define EnCFG_CFNULRSP 0x00000004
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#define EnCFG_BBType_MASK 0x00000003
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#define EnCFG_BBType_g 0x00000002
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#define EnCFG_BBType_b 0x00000001
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#define EnCFG_BBType_a 0x00000000
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//
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// Bits in the Page1Sel register
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//
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#define PAGE1_SEL 0x01
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//
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// Bits in the CFG register
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//
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#define CFG_TKIPOPT 0x80
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#define CFG_RXDMAOPT 0x40
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#define CFG_TMOT_SW 0x20
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#define CFG_TMOT_HWLONG 0x10
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#define CFG_TMOT_HW 0x00
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#define CFG_CFPENDOPT 0x08
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#define CFG_BCNSUSEN 0x04
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#define CFG_NOTXTIMEOUT 0x02
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#define CFG_NOBUFOPT 0x01
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//
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// Bits in the TEST register
|
|
|
|
//
|
|
|
|
#define TEST_LBEXT 0x80 //
|
|
|
|
#define TEST_LBINT 0x40 //
|
|
|
|
#define TEST_LBNONE 0x00 //
|
|
|
|
#define TEST_SOFTINT 0x20 //
|
|
|
|
#define TEST_CONTTX 0x10 //
|
|
|
|
#define TEST_TXPE 0x08 //
|
|
|
|
#define TEST_NAVDIS 0x04 //
|
|
|
|
#define TEST_NOCTS 0x02 //
|
|
|
|
#define TEST_NOACK 0x01 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the HOSTCR register
|
|
|
|
//
|
|
|
|
#define HOSTCR_TXONST 0x80 //
|
|
|
|
#define HOSTCR_RXONST 0x40 //
|
|
|
|
#define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
|
|
|
|
#define HOSTCR_AP 0x10 // Port Type 1 = AP
|
|
|
|
#define HOSTCR_TXON 0x08 //0000 1000
|
|
|
|
#define HOSTCR_RXON 0x04 //0000 0100
|
|
|
|
#define HOSTCR_MACEN 0x02 //0000 0010
|
|
|
|
#define HOSTCR_SOFTRST 0x01 //0000 0001
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the MACCR register
|
|
|
|
//
|
|
|
|
#define MACCR_SYNCFLUSHOK 0x04 //
|
|
|
|
#define MACCR_SYNCFLUSH 0x02 //
|
|
|
|
#define MACCR_CLRNAV 0x01 //
|
|
|
|
|
|
|
|
// Bits in the MAC_REG_GPIOCTL0 register
|
|
|
|
//
|
|
|
|
#define LED_ACTSET 0x01 //
|
|
|
|
#define LED_RFOFF 0x02 //
|
|
|
|
#define LED_NOCONNECT 0x04 //
|
|
|
|
//
|
|
|
|
// Bits in the RCR register
|
|
|
|
//
|
|
|
|
#define RCR_SSID 0x80
|
|
|
|
#define RCR_RXALLTYPE 0x40 //
|
|
|
|
#define RCR_UNICAST 0x20 //
|
|
|
|
#define RCR_BROADCAST 0x10 //
|
|
|
|
#define RCR_MULTICAST 0x08 //
|
|
|
|
#define RCR_WPAERR 0x04 //
|
|
|
|
#define RCR_ERRCRC 0x02 //
|
|
|
|
#define RCR_BSSID 0x01 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the TCR register
|
|
|
|
//
|
|
|
|
#define TCR_SYNCDCFOPT 0x02 //
|
|
|
|
#define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the IMR register
|
|
|
|
//
|
|
|
|
#define IMR_MEASURESTART 0x80000000 //
|
|
|
|
#define IMR_QUIETSTART 0x20000000 //
|
|
|
|
#define IMR_RADARDETECT 0x10000000 //
|
|
|
|
#define IMR_MEASUREEND 0x08000000 //
|
|
|
|
#define IMR_SOFTTIMER1 0x00200000 //
|
|
|
|
//#define IMR_SYNCFLUSHOK 0x00100000 //
|
|
|
|
//#define IMR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000
|
|
|
|
//#define IMR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000
|
|
|
|
//#define IMR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000
|
|
|
|
//#define IMR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000
|
|
|
|
//#define IMR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000
|
|
|
|
//#define IMR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000
|
|
|
|
//#define IMR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000
|
|
|
|
#define IMR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
|
|
|
|
#define IMR_RXNOBUF 0x00000800 //
|
|
|
|
#define IMR_MIBNEARFULL 0x00000400 //
|
|
|
|
#define IMR_SOFTINT 0x00000200 //
|
|
|
|
#define IMR_FETALERR 0x00000100 //
|
|
|
|
#define IMR_WATCHDOG 0x00000080 //
|
|
|
|
#define IMR_SOFTTIMER 0x00000040 //
|
|
|
|
#define IMR_GPIO 0x00000020 //
|
|
|
|
#define IMR_TBTT 0x00000010 //
|
|
|
|
#define IMR_RXDMA0 0x00000008 //
|
|
|
|
#define IMR_BNTX 0x00000004 //
|
|
|
|
#define IMR_AC0DMA 0x00000002 //
|
|
|
|
#define IMR_TXDMA0 0x00000001 //
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the ISR register
|
|
|
|
//
|
|
|
|
|
|
|
|
#define ISR_MEASURESTART 0x80000000 //
|
|
|
|
#define ISR_QUIETSTART 0x20000000 //
|
|
|
|
#define ISR_RADARDETECT 0x10000000 //
|
|
|
|
#define ISR_MEASUREEND 0x08000000 //
|
|
|
|
#define ISR_SOFTTIMER1 0x00200000 //
|
|
|
|
//#define ISR_SYNCFLUSHOK 0x00100000 //0001 0000 0000 0000 0000 0000
|
|
|
|
//#define ISR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000
|
|
|
|
//#define ISR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000
|
|
|
|
//#define ISR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000
|
|
|
|
//#define ISR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000
|
|
|
|
//#define ISR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000
|
|
|
|
//#define ISR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000
|
|
|
|
//#define ISR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000
|
|
|
|
#define ISR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
|
|
|
|
#define ISR_RXNOBUF 0x00000800 //0000 0000 0000 1000 0000 0000
|
|
|
|
#define ISR_MIBNEARFULL 0x00000400 //0000 0000 0000 0100 0000 0000
|
|
|
|
#define ISR_SOFTINT 0x00000200 //
|
|
|
|
#define ISR_FETALERR 0x00000100 //
|
|
|
|
#define ISR_WATCHDOG 0x00000080 //
|
|
|
|
#define ISR_SOFTTIMER 0x00000040 //
|
|
|
|
#define ISR_GPIO 0x00000020 //
|
|
|
|
#define ISR_TBTT 0x00000010 //
|
|
|
|
#define ISR_RXDMA0 0x00000008 //
|
|
|
|
#define ISR_BNTX 0x00000004 //
|
|
|
|
#define ISR_AC0DMA 0x00000002 //
|
|
|
|
#define ISR_TXDMA0 0x00000001 //
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the PSCFG register
|
|
|
|
//
|
|
|
|
#define PSCFG_PHILIPMD 0x40 //
|
|
|
|
#define PSCFG_WAKECALEN 0x20 //
|
|
|
|
#define PSCFG_WAKETMREN 0x10 //
|
|
|
|
#define PSCFG_BBPSPROG 0x08 //
|
|
|
|
#define PSCFG_WAKESYN 0x04 //
|
|
|
|
#define PSCFG_SLEEPSYN 0x02 //
|
|
|
|
#define PSCFG_AUTOSLEEP 0x01 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the PSCTL register
|
|
|
|
//
|
|
|
|
#define PSCTL_WAKEDONE 0x20 //
|
|
|
|
#define PSCTL_PS 0x10 //
|
|
|
|
#define PSCTL_GO2DOZE 0x08 //
|
|
|
|
#define PSCTL_LNBCN 0x04 //
|
|
|
|
#define PSCTL_ALBCN 0x02 //
|
|
|
|
#define PSCTL_PSEN 0x01 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the PSPWSIG register
|
|
|
|
//
|
|
|
|
#define PSSIG_WPE3 0x80 //
|
|
|
|
#define PSSIG_WPE2 0x40 //
|
|
|
|
#define PSSIG_WPE1 0x20 //
|
|
|
|
#define PSSIG_WRADIOPE 0x10 //
|
|
|
|
#define PSSIG_SPE3 0x08 //
|
|
|
|
#define PSSIG_SPE2 0x04 //
|
|
|
|
#define PSSIG_SPE1 0x02 //
|
|
|
|
#define PSSIG_SRADIOPE 0x01 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the BBREGCTL register
|
|
|
|
//
|
|
|
|
#define BBREGCTL_DONE 0x04 //
|
|
|
|
#define BBREGCTL_REGR 0x02 //
|
|
|
|
#define BBREGCTL_REGW 0x01 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the IFREGCTL register
|
|
|
|
//
|
|
|
|
#define IFREGCTL_DONE 0x04 //
|
|
|
|
#define IFREGCTL_IFRF 0x02 //
|
|
|
|
#define IFREGCTL_REGW 0x01 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the SOFTPWRCTL register
|
|
|
|
//
|
|
|
|
#define SOFTPWRCTL_RFLEOPT 0x0800 //
|
|
|
|
#define SOFTPWRCTL_TXPEINV 0x0200 //
|
|
|
|
#define SOFTPWRCTL_SWPECTI 0x0100 //
|
|
|
|
#define SOFTPWRCTL_SWPAPE 0x0020 //
|
|
|
|
#define SOFTPWRCTL_SWCALEN 0x0010 //
|
|
|
|
#define SOFTPWRCTL_SWRADIO_PE 0x0008 //
|
|
|
|
#define SOFTPWRCTL_SWPE2 0x0004 //
|
|
|
|
#define SOFTPWRCTL_SWPE1 0x0002 //
|
|
|
|
#define SOFTPWRCTL_SWPE3 0x0001 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the GPIOCTL1 register
|
|
|
|
//
|
|
|
|
#define GPIO1_DATA1 0x20 //
|
|
|
|
#define GPIO1_MD1 0x10 //
|
|
|
|
#define GPIO1_DATA0 0x02 //
|
|
|
|
#define GPIO1_MD0 0x01 //
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the DMACTL register
|
|
|
|
//
|
|
|
|
#define DMACTL_CLRRUN 0x00080000 //
|
|
|
|
#define DMACTL_RUN 0x00000008 //
|
|
|
|
#define DMACTL_WAKE 0x00000004 //
|
|
|
|
#define DMACTL_DEAD 0x00000002 //
|
|
|
|
#define DMACTL_ACTIVE 0x00000001 //
|
|
|
|
//
|
|
|
|
// Bits in the RXDMACTL0 register
|
|
|
|
//
|
|
|
|
#define RX_PERPKT 0x00000100 //
|
|
|
|
#define RX_PERPKTCLR 0x01000000 //
|
|
|
|
//
|
|
|
|
// Bits in the BCNDMACTL register
|
|
|
|
//
|
|
|
|
#define BEACON_READY 0x01 //
|
|
|
|
//
|
|
|
|
// Bits in the MISCFFCTL register
|
|
|
|
//
|
|
|
|
#define MISCFFCTL_WRITE 0x0001 //
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in WAKEUPEN0
|
|
|
|
//
|
|
|
|
#define WAKEUPEN0_DIRPKT 0x10
|
|
|
|
#define WAKEUPEN0_LINKOFF 0x08
|
|
|
|
#define WAKEUPEN0_ATIMEN 0x04
|
|
|
|
#define WAKEUPEN0_TIMEN 0x02
|
|
|
|
#define WAKEUPEN0_MAGICEN 0x01
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in WAKEUPEN1
|
|
|
|
//
|
|
|
|
#define WAKEUPEN1_128_3 0x08
|
|
|
|
#define WAKEUPEN1_128_2 0x04
|
|
|
|
#define WAKEUPEN1_128_1 0x02
|
|
|
|
#define WAKEUPEN1_128_0 0x01
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in WAKEUPSR0
|
|
|
|
//
|
|
|
|
#define WAKEUPSR0_DIRPKT 0x10
|
|
|
|
#define WAKEUPSR0_LINKOFF 0x08
|
|
|
|
#define WAKEUPSR0_ATIMEN 0x04
|
|
|
|
#define WAKEUPSR0_TIMEN 0x02
|
|
|
|
#define WAKEUPSR0_MAGICEN 0x01
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in WAKEUPSR1
|
|
|
|
//
|
|
|
|
#define WAKEUPSR1_128_3 0x08
|
|
|
|
#define WAKEUPSR1_128_2 0x04
|
|
|
|
#define WAKEUPSR1_128_1 0x02
|
|
|
|
#define WAKEUPSR1_128_0 0x01
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the MAC_REG_GPIOCTL register
|
|
|
|
//
|
|
|
|
#define GPIO0_MD 0x01 //
|
|
|
|
#define GPIO0_DATA 0x02 //
|
|
|
|
#define GPIO0_INTMD 0x04 //
|
|
|
|
#define GPIO1_MD 0x10 //
|
|
|
|
#define GPIO1_DATA 0x20 //
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
// Bits in the MSRCTL register
|
|
|
|
//
|
|
|
|
#define MSRCTL_FINISH 0x80
|
|
|
|
#define MSRCTL_READY 0x40
|
|
|
|
#define MSRCTL_RADARDETECT 0x20
|
|
|
|
#define MSRCTL_EN 0x10
|
|
|
|
#define MSRCTL_QUIETTXCHK 0x08
|
|
|
|
#define MSRCTL_QUIETRPT 0x04
|
|
|
|
#define MSRCTL_QUIETINT 0x02
|
|
|
|
#define MSRCTL_QUIETEN 0x01
|
|
|
|
//
|
|
|
|
// Bits in the MSRCTL1 register
|
|
|
|
//
|
|
|
|
#define MSRCTL1_TXPWR 0x08
|
|
|
|
#define MSRCTL1_CSAPAREN 0x04
|
|
|
|
#define MSRCTL1_TXPAUSE 0x01
|
|
|
|
|
|
|
|
|
|
|
|
// Loopback mode
|
|
|
|
#define MAC_LB_EXT 0x02 //
|
|
|
|
#define MAC_LB_INTERNAL 0x01 //
|
|
|
|
#define MAC_LB_NONE 0x00 //
|
|
|
|
|
|
|
|
// Ethernet address filter type
|
|
|
|
#define PKT_TYPE_NONE 0x00 // turn off receiver
|
|
|
|
#define PKT_TYPE_ALL_MULTICAST 0x80
|
|
|
|
#define PKT_TYPE_PROMISCUOUS 0x40
|
|
|
|
#define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted
|
|
|
|
#define PKT_TYPE_BROADCAST 0x10
|
|
|
|
#define PKT_TYPE_MULTICAST 0x08
|
|
|
|
#define PKT_TYPE_ERROR_WPA 0x04
|
|
|
|
#define PKT_TYPE_ERROR_CRC 0x02
|
|
|
|
#define PKT_TYPE_BSSID 0x01
|
|
|
|
|
|
|
|
#define Default_BI 0x200
|
|
|
|
|
|
|
|
|
|
|
|
// MiscFIFO Offset
|
|
|
|
#define MISCFIFO_KEYETRY0 32
|
|
|
|
#define MISCFIFO_KEYENTRYSIZE 22
|
|
|
|
#define MISCFIFO_SYNINFO_IDX 10
|
|
|
|
#define MISCFIFO_SYNDATA_IDX 11
|
|
|
|
#define MISCFIFO_SYNDATASIZE 21
|
|
|
|
|
|
|
|
// enabled mask value of irq
|
|
|
|
#define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
|
|
|
|
IMR_RXDMA1 | \
|
|
|
|
IMR_RXNOBUF | \
|
|
|
|
IMR_MIBNEARFULL | \
|
|
|
|
IMR_SOFTINT | \
|
|
|
|
IMR_FETALERR | \
|
|
|
|
IMR_WATCHDOG | \
|
|
|
|
IMR_SOFTTIMER | \
|
|
|
|
IMR_GPIO | \
|
|
|
|
IMR_TBTT | \
|
|
|
|
IMR_RXDMA0 | \
|
|
|
|
IMR_BNTX | \
|
|
|
|
IMR_AC0DMA | \
|
|
|
|
IMR_TXDMA0)
|
|
|
|
|
|
|
|
// max time out delay time
|
|
|
|
#define W_MAX_TIMEOUT 0xFFF0U //
|
|
|
|
|
|
|
|
// wait time within loop
|
|
|
|
#define CB_DELAY_LOOP_WAIT 10 // 10ms
|
|
|
|
|
|
|
|
//
|
|
|
|
// revision id
|
|
|
|
//
|
|
|
|
#define REV_ID_VT3253_A0 0x00
|
|
|
|
#define REV_ID_VT3253_A1 0x01
|
|
|
|
#define REV_ID_VT3253_B0 0x08
|
|
|
|
#define REV_ID_VT3253_B1 0x09
|
|
|
|
|
|
|
|
/*--------------------- Export Types ------------------------------*/
|
|
|
|
|
|
|
|
/*--------------------- Export Macros ------------------------------*/
|
|
|
|
|
|
|
|
#define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \
|
|
|
|
{ \
|
|
|
|
BYTE byData; \
|
|
|
|
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
|
|
|
VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \
|
|
|
|
{ \
|
|
|
|
WORD wData; \
|
|
|
|
VNSvInPortW(dwIoBase + byRegOfs, &wData); \
|
|
|
|
VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \
|
|
|
|
{ \
|
2010-06-24 12:02:25 -06:00
|
|
|
unsigned long dwData; \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
|
|
|
|
VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \
|
|
|
|
{ \
|
|
|
|
BYTE byData; \
|
|
|
|
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
|
|
|
byData &= byMask; \
|
|
|
|
VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \
|
|
|
|
{ \
|
|
|
|
BYTE byData; \
|
|
|
|
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
|
|
|
VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \
|
|
|
|
{ \
|
|
|
|
WORD wData; \
|
|
|
|
VNSvInPortW(dwIoBase + byRegOfs, &wData); \
|
|
|
|
VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \
|
|
|
|
{ \
|
2010-06-24 12:02:25 -06:00
|
|
|
unsigned long dwData; \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
|
|
|
|
VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \
|
2010-06-05 16:13:49 -06:00
|
|
|
(unsigned long *)pdwCurrDescAddr); \
|
2009-04-25 08:30:44 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \
|
2010-06-05 16:13:49 -06:00
|
|
|
(unsigned long *)pdwCurrDescAddr); \
|
2009-04-25 08:30:44 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \
|
2010-06-05 16:13:49 -06:00
|
|
|
(unsigned long *)pdwCurrDescAddr); \
|
2009-04-25 08:30:44 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \
|
2010-06-05 16:13:49 -06:00
|
|
|
(unsigned long *)pdwCurrDescAddr); \
|
2009-04-25 08:30:44 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \
|
2010-06-05 16:13:49 -06:00
|
|
|
(unsigned long *)pdwCurrDescAddr); \
|
2009-04-25 08:30:44 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
|
2010-06-05 16:13:49 -06:00
|
|
|
(unsigned long *)pdwCurrDescAddr); \
|
2009-04-25 08:30:44 -06:00
|
|
|
} \
|
|
|
|
|
|
|
|
// set the chip with current BCN tx descriptor address
|
|
|
|
#define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
|
|
|
|
dwCurrDescAddr); \
|
|
|
|
}
|
|
|
|
|
|
|
|
// set the chip with current BCN length
|
|
|
|
#define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
|
|
|
|
wCurrBCNLength); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \
|
2010-06-05 16:13:47 -06:00
|
|
|
(unsigned char *)pbyEtherAddr); \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
|
|
|
|
pbyEtherAddr + 1); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
|
|
|
|
pbyEtherAddr + 2); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
|
|
|
|
pbyEtherAddr + 3); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
|
|
|
|
pbyEtherAddr + 4); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
|
|
|
|
pbyEtherAddr + 5); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \
|
|
|
|
*(pbyEtherAddr)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
|
|
|
|
*(pbyEtherAddr + 1)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
|
|
|
|
*(pbyEtherAddr + 2)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
|
|
|
|
*(pbyEtherAddr + 3)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
|
|
|
|
*(pbyEtherAddr + 4)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
|
|
|
|
*(pbyEtherAddr + 5)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_PAR0, \
|
2010-06-05 16:13:47 -06:00
|
|
|
(unsigned char *)pbyEtherAddr); \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \
|
|
|
|
pbyEtherAddr + 1); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \
|
|
|
|
pbyEtherAddr + 2); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \
|
|
|
|
pbyEtherAddr + 3); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \
|
|
|
|
pbyEtherAddr + 4); \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \
|
|
|
|
pbyEtherAddr + 5); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \
|
|
|
|
*pbyEtherAddr); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \
|
|
|
|
*(pbyEtherAddr + 1)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \
|
|
|
|
*(pbyEtherAddr + 2)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \
|
|
|
|
*(pbyEtherAddr + 3)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \
|
|
|
|
*(pbyEtherAddr + 4)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \
|
|
|
|
*(pbyEtherAddr + 5)); \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#define MACvClearISR(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvStart(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \
|
|
|
|
(HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvRx0PerPktMode(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvRx0BufferFillMode(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvRx1PerPktMode(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvRx1BufferFillMode(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvRxOn(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvReceive0(dwIoBase) \
|
|
|
|
{ \
|
2010-06-24 12:02:25 -06:00
|
|
|
unsigned long dwData; \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \
|
|
|
|
if (dwData & DMACTL_RUN) { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE);\
|
|
|
|
} \
|
|
|
|
else { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
|
|
|
|
} \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvReceive1(dwIoBase) \
|
|
|
|
{ \
|
2010-06-24 12:02:25 -06:00
|
|
|
unsigned long dwData; \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \
|
|
|
|
if (dwData & DMACTL_RUN) { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE);\
|
|
|
|
} \
|
|
|
|
else { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
|
|
|
|
} \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvTxOn(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvTransmit0(dwIoBase) \
|
|
|
|
{ \
|
2010-06-24 12:02:25 -06:00
|
|
|
unsigned long dwData; \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \
|
|
|
|
if (dwData & DMACTL_RUN) { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE);\
|
|
|
|
} \
|
|
|
|
else { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
|
|
|
|
} \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvTransmitAC0(dwIoBase) \
|
|
|
|
{ \
|
2010-06-24 12:02:25 -06:00
|
|
|
unsigned long dwData; \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \
|
|
|
|
if (dwData & DMACTL_RUN) { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE);\
|
|
|
|
} \
|
|
|
|
else { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
|
|
|
|
} \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvTransmitSYNC(dwIoBase) \
|
|
|
|
{ \
|
2010-06-24 12:02:25 -06:00
|
|
|
unsigned long dwData; \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \
|
|
|
|
if (dwData & DMACTL_RUN) { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE);\
|
|
|
|
} \
|
|
|
|
else { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
|
|
|
|
} \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvTransmitATIM(dwIoBase) \
|
|
|
|
{ \
|
2010-06-24 12:02:25 -06:00
|
|
|
unsigned long dwData; \
|
2009-04-25 08:30:44 -06:00
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \
|
|
|
|
if (dwData & DMACTL_RUN) { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE);\
|
|
|
|
} \
|
|
|
|
else { \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
|
|
|
|
} \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvTransmitBCN(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvClearStckDS(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
BYTE byOrgValue; \
|
|
|
|
VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \
|
|
|
|
byOrgValue = byOrgValue & 0xFC; \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvReadISR(dwIoBase, pdwValue) \
|
|
|
|
{ \
|
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvWriteISR(dwIoBase, dwValue) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvIntEnable(dwIoBase, dwMask) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvIntDisable(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvSelectPage0(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
|
|
|
}
|
|
|
|
#define MACvSelectPage1(dwIoBase) \
|
|
|
|
{ \
|
|
|
|
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvReadMIBCounter(dwIoBase, pdwCounter) \
|
|
|
|
{ \
|
|
|
|
VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MACvPwrEvntDisable(dwIoBase) \
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{ \
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VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000); \
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}
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#define MACvEnableProtectMD(dwIoBase) \
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{ \
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2010-06-24 12:02:25 -06:00
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unsigned long dwOrgValue; \
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2009-04-25 08:30:44 -06:00
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VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
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dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
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VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
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}
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#define MACvDisableProtectMD(dwIoBase) \
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{ \
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2010-06-24 12:02:25 -06:00
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unsigned long dwOrgValue; \
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2009-04-25 08:30:44 -06:00
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VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
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dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
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VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
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}
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#define MACvEnableBarkerPreambleMd(dwIoBase) \
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{ \
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2010-06-24 12:02:25 -06:00
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unsigned long dwOrgValue; \
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2009-04-25 08:30:44 -06:00
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VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
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dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
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VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
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}
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#define MACvDisableBarkerPreambleMd(dwIoBase) \
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{ \
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2010-06-24 12:02:25 -06:00
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unsigned long dwOrgValue; \
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2009-04-25 08:30:44 -06:00
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VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
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dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
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VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
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}
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#define MACvSetBBType(dwIoBase, byTyp) \
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{ \
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2010-06-24 12:02:25 -06:00
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unsigned long dwOrgValue; \
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2009-04-25 08:30:44 -06:00
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VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
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dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
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2010-06-24 12:02:25 -06:00
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dwOrgValue = dwOrgValue | (unsigned long) byTyp; \
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2009-04-25 08:30:44 -06:00
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VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
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}
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#define MACvReadATIMW(dwIoBase, pwCounter) \
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{ \
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VNSvInPortW(dwIoBase + MAC_REG_AIDATIM , pwCounter); \
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}
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#define MACvWriteATIMW(dwIoBase, wCounter) \
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{ \
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VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM , wCounter); \
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}
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#define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \
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{ \
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VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
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VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \
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VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
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}
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#define MACvGPIOIn(dwIoBase, pbyValue) \
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{ \
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VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue); \
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}
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#define MACvSetRFLE_LatchBase(dwIoBase) \
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{ \
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MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT); \
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}
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/*--------------------- Export Classes ----------------------------*/
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/*--------------------- Export Variables --------------------------*/
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/*--------------------- Export Functions --------------------------*/
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extern WORD TxRate_iwconfig;//2008-5-8 <add> by chester
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2010-06-22 09:54:42 -06:00
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void MACvReadAllRegs(unsigned long dwIoBase, unsigned char *pbyMacRegs);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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BOOL MACbIsRegBitsOn(unsigned long dwIoBase, BYTE byRegOfs, BYTE byTestBits);
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BOOL MACbIsRegBitsOff(unsigned long dwIoBase, BYTE byRegOfs, BYTE byTestBits);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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BOOL MACbIsIntDisable(unsigned long dwIoBase);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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BYTE MACbyReadMultiAddr(unsigned long dwIoBase, unsigned int uByteIdx);
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void MACvWriteMultiAddr(unsigned long dwIoBase, unsigned int uByteIdx, BYTE byData);
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void MACvSetMultiAddrByHash(unsigned long dwIoBase, BYTE byHashIdx);
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void MACvResetMultiAddrByHash(unsigned long dwIoBase, BYTE byHashIdx);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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void MACvSetRxThreshold(unsigned long dwIoBase, BYTE byThreshold);
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void MACvGetRxThreshold(unsigned long dwIoBase, unsigned char *pbyThreshold);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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void MACvSetTxThreshold(unsigned long dwIoBase, BYTE byThreshold);
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void MACvGetTxThreshold(unsigned long dwIoBase, unsigned char *pbyThreshold);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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void MACvSetDmaLength(unsigned long dwIoBase, BYTE byDmaLength);
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void MACvGetDmaLength(unsigned long dwIoBase, unsigned char *pbyDmaLength);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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void MACvSetShortRetryLimit(unsigned long dwIoBase, BYTE byRetryLimit);
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void MACvGetShortRetryLimit(unsigned long dwIoBase, unsigned char *pbyRetryLimit);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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void MACvSetLongRetryLimit(unsigned long dwIoBase, BYTE byRetryLimit);
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void MACvGetLongRetryLimit(unsigned long dwIoBase, unsigned char *pbyRetryLimit);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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void MACvSetLoopbackMode(unsigned long dwIoBase, BYTE byLoopbackMode);
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BOOL MACbIsInLoopbackMode(unsigned long dwIoBase);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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void MACvSetPacketFilter(unsigned long dwIoBase, WORD wFilterType);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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void MACvSaveContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
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void MACvRestoreContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
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BOOL MACbCompareContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
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2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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BOOL MACbSoftwareReset(unsigned long dwIoBase);
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BOOL MACbSafeSoftwareReset(unsigned long dwIoBase);
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BOOL MACbSafeRxOff(unsigned long dwIoBase);
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BOOL MACbSafeTxOff(unsigned long dwIoBase);
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BOOL MACbSafeStop(unsigned long dwIoBase);
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BOOL MACbShutdown(unsigned long dwIoBase);
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void MACvInitialize(unsigned long dwIoBase);
|
2010-06-24 12:02:25 -06:00
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void MACvSetCurrRx0DescAddr(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
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void MACvSetCurrRx1DescAddr(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
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void MACvSetCurrTXDescAddr(int iTxType, unsigned long dwIoBase, unsigned long dwCurrDescAddr);
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void MACvSetCurrTx0DescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
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void MACvSetCurrAC0DescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
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void MACvSetCurrSyncDescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
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void MACvSetCurrATIMDescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
|
2010-06-22 09:54:42 -06:00
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void MACvTimer0MicroSDelay(unsigned long dwIoBase, unsigned int uDelay);
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void MACvOneShotTimer0MicroSec(unsigned long dwIoBase, unsigned int uDelayTime);
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void MACvOneShotTimer1MicroSec(unsigned long dwIoBase, unsigned int uDelayTime);
|
2009-04-25 08:30:44 -06:00
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2010-06-24 12:02:25 -06:00
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void MACvSetMISCFifo(unsigned long dwIoBase, WORD wOffset, unsigned long dwData);
|
2009-04-25 08:30:44 -06:00
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2010-06-22 09:54:42 -06:00
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BOOL MACbTxDMAOff (unsigned long dwIoBase, unsigned int idx);
|
2009-04-25 08:30:44 -06:00
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|
2010-06-22 09:54:42 -06:00
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|
void MACvClearBusSusInd(unsigned long dwIoBase);
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void MACvEnableBusSusEn(unsigned long dwIoBase);
|
2009-04-25 08:30:44 -06:00
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|
2010-06-22 09:54:42 -06:00
|
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|
BOOL MACbFlushSYNCFifo(unsigned long dwIoBase);
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BOOL MACbPSWakeup(unsigned long dwIoBase);
|
2009-04-25 08:30:44 -06:00
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|
2010-06-22 09:54:42 -06:00
|
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void MACvSetKeyEntry(unsigned long dwIoBase, WORD wKeyCtl, unsigned int uEntryIdx,
|
2010-06-05 16:13:49 -06:00
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unsigned int uKeyIdx, unsigned char *pbyAddr, unsigned long *pdwKey, BYTE byLocalID);
|
2010-06-22 09:54:42 -06:00
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void MACvDisableKeyEntry(unsigned long dwIoBase, unsigned int uEntryIdx);
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void MACvSetDefaultKeyEntry(unsigned long dwIoBase, unsigned int uKeyLen,
|
2010-06-05 16:13:49 -06:00
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unsigned int uKeyIdx, unsigned long *pdwKey, BYTE byLocalID);
|
2010-06-22 09:54:42 -06:00
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|
//void MACvEnableDefaultKey(unsigned long dwIoBase, BYTE byLocalID);
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|
void MACvDisableDefaultKey(unsigned long dwIoBase);
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|
void MACvSetDefaultTKIPKeyEntry(unsigned long dwIoBase, unsigned int uKeyLen,
|
2010-06-05 16:13:49 -06:00
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|
unsigned int uKeyIdx, unsigned long *pdwKey, BYTE byLocalID);
|
2010-06-22 09:54:42 -06:00
|
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void MACvSetDefaultKeyCtl(unsigned long dwIoBase, WORD wKeyCtl, unsigned int uEntryIdx, BYTE byLocalID);
|
2009-04-25 08:30:44 -06:00
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|
#endif // __MAC_H__
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