powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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/*
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* MPC8572 DS Core1 Device Tree Source in CAMP mode.
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*
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* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
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* can be shared, all the other devices must be assigned to one core only.
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* This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
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*
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* Please note to add "-b 1" for core1's dts compiling.
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*
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2009-02-09 20:33:06 -07:00
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* Copyright 2007-2009 Freescale Semiconductor Inc.
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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2011-11-03 00:07:56 -06:00
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/include/ "mpc8572ds.dts"
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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/ {
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model = "fsl,MPC8572DS";
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compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
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cpus {
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2011-11-03 00:07:56 -06:00
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PowerPC,8572@0 {
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status = "disabled";
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};
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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PowerPC,8572@1 {
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};
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};
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2011-11-03 00:07:56 -06:00
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localbus@ffe05000 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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soc8572@ffe00000 {
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2011-11-03 00:07:56 -06:00
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ecm-law@0 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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2011-11-03 00:07:56 -06:00
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ecm@1000 {
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status = "disabled";
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};
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memory-controller@2000 {
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status = "disabled";
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};
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memory-controller@6000 {
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status = "disabled";
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};
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i2c@3000 {
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status = "disabled";
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};
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i2c@3100 {
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status = "disabled";
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};
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serial@4500 {
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status = "disabled";
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};
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gpio-controller@f000 {
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status = "disabled";
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};
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l2-cache-controller@20000 {
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cache-size = <0x80000>; // L2, 512K
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};
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dma@21300 {
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status = "disabled";
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};
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ethernet@24000 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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2011-11-03 00:07:56 -06:00
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ptp_clock@24e00 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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2011-11-03 00:07:56 -06:00
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ethernet@25000 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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2011-11-03 00:07:56 -06:00
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mdio@25520 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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2011-11-03 00:07:56 -06:00
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crypto@30000 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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2011-11-03 00:07:56 -06:00
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pic@40000 {
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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protected-sources = <
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18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
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29 30 34 35 36 40 /* enet0 enet1 */
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2009-02-26 11:15:16 -07:00
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24 25 20 21 22 23 /* pci0 pci1 dma1 */
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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43 /* i2c */
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0x1 0x2 0x3 0x4 /* pci slot */
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0x9 0xa 0xb 0xc /* usb */
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0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
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2010-04-22 02:31:38 -06:00
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0xe0 0xe1 0xe2 0xe3 /* msi */
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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>;
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};
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2011-11-03 00:07:56 -06:00
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timer@41100 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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2011-11-03 00:07:56 -06:00
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msi@41600 {
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msi-available-ranges = <0x80 0x80>;
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interrupts = <
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2012-07-10 00:08:26 -06:00
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0xe4 0 0 0
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0xe5 0 0 0
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0xe6 0 0 0
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0xe7 0 0 0>;
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2011-11-03 00:07:56 -06:00
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};
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global-utilities@e0000 {
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status = "disabled";
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};
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};
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pcie@ffe08000 {
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status = "disabled";
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};
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pcie@ffe09000 {
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status = "disabled";
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powerpc/85xx: Create dts for each core in CAMP mode for MPC8572DS
This patch creates the dts files for each core and splits the devices
between the two cores for MPC8572DS.
core0 has memory, L2, i2c, dma1, global-util, eth0, eth1, crypto, pci0, pci1.
core1 has L2, dma2, eth2, eth3, pci2, msi.
MPIC is shared between two cores but each core will protect its interrupts
from other core by using "protected-sources" of mpic.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03 12:03:09 -07:00
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};
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};
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