2008-10-08 04:03:33 -06:00
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/*
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* Description: Instruction SRAM accessor functions for the Blackfin
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*
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* Copyright 2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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2009-08-26 19:46:48 -06:00
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#define pr_fmt(fmt) "isram: " fmt
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2008-10-08 04:03:33 -06:00
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <asm/blackfin.h>
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2009-08-26 19:46:48 -06:00
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#include <asm/dma.h>
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2008-10-08 04:03:33 -06:00
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/*
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* IMPORTANT WARNING ABOUT THESE FUNCTIONS
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*
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* The emulator will not function correctly if a write command is left in
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* ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
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* the emulator. To avoid such problems, ensure that both ITEST_COMMAND
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* and DTEST_COMMAND are zero when exiting these functions.
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*/
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/*
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* On the Blackfin, L1 instruction sram (which operates at core speeds) can not
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* be accessed by a normal core load, so we need to go through a few hoops to
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* read/write it.
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* To try to make it easier - we export a memcpy interface, where either src or
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* dest can be in this special L1 memory area.
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* The low level read/write functions should not be exposed to the rest of the
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* kernel, since they operate on 64-bit data, and need specific address alignment
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*/
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static DEFINE_SPINLOCK(dtest_lock);
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/* Takes a void pointer */
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#define IADDR2DTEST(x) \
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({ unsigned long __addr = (unsigned long)(x); \
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(__addr & 0x47F8) | /* address bits 14 & 10:3 */ \
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2009-08-27 08:39:31 -06:00
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(__addr & 0x8000) << 23 | /* Bank A/B */ \
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2008-10-08 04:03:33 -06:00
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(__addr & 0x0800) << 15 | /* address bit 11 */ \
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2009-08-27 08:39:31 -06:00
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(__addr & 0x3000) << 4 | /* address bits 13:12 */ \
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(__addr & 0x8000) << 8 | /* address bit 15 */ \
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(0x1000000) | /* instruction access = 1 */ \
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(0x4); /* data array = 1 */ \
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2008-10-08 04:03:33 -06:00
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})
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/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
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#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
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/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
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#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
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static void isram_write(const void *addr, uint64_t data)
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{
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uint32_t cmd;
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unsigned long flags;
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if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH))
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return;
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2009-08-27 08:39:31 -06:00
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cmd = IADDR2DTEST(addr) | 2; /* write */
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2008-10-08 04:03:33 -06:00
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/*
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* Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
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* While in exception context - atomicity is guaranteed or double fault
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*/
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spin_lock_irqsave(&dtest_lock, flags);
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bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
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bfin_write_DTEST_DATA1(data >> 32);
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/* use the builtin, since interrupts are already turned off */
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__builtin_bfin_csync();
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bfin_write_DTEST_COMMAND(cmd);
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__builtin_bfin_csync();
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bfin_write_DTEST_COMMAND(0);
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__builtin_bfin_csync();
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spin_unlock_irqrestore(&dtest_lock, flags);
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}
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static uint64_t isram_read(const void *addr)
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{
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uint32_t cmd;
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unsigned long flags;
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uint64_t ret;
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if (addr > (void *)(L1_CODE_START + L1_CODE_LENGTH))
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return 0;
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cmd = IADDR2DTEST(addr) | 0; /* read */
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/*
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* Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
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* While in exception context - atomicity is guaranteed or double fault
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*/
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spin_lock_irqsave(&dtest_lock, flags);
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/* use the builtin, since interrupts are already turned off */
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__builtin_bfin_csync();
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bfin_write_DTEST_COMMAND(cmd);
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__builtin_bfin_csync();
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ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
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bfin_write_DTEST_COMMAND(0);
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__builtin_bfin_csync();
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spin_unlock_irqrestore(&dtest_lock, flags);
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return ret;
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}
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static bool isram_check_addr(const void *addr, size_t n)
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{
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if ((addr >= (void *)L1_CODE_START) &&
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(addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
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2009-04-20 03:20:58 -06:00
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if ((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH)) {
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2008-10-08 04:03:33 -06:00
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show_stack(NULL, NULL);
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2009-08-26 19:46:48 -06:00
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pr_err("copy involving %p length (%zu) too long\n", addr, n);
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2008-10-08 04:03:33 -06:00
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}
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return true;
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}
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return false;
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}
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/*
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* The isram_memcpy() function copies n bytes from memory area src to memory area dest.
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* The isram_memcpy() function returns a pointer to dest.
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* Either dest or src can be in L1 instruction sram.
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*/
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void *isram_memcpy(void *dest, const void *src, size_t n)
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{
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uint64_t data_in = 0, data_out = 0;
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size_t count;
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bool dest_in_l1, src_in_l1, need_data, put_data;
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unsigned char byte, *src_byte, *dest_byte;
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src_byte = (unsigned char *)src;
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dest_byte = (unsigned char *)dest;
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dest_in_l1 = isram_check_addr(dest, n);
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src_in_l1 = isram_check_addr(src, n);
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need_data = true;
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put_data = true;
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for (count = 0; count < n; count++) {
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if (src_in_l1) {
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if (need_data) {
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data_in = isram_read(src + count);
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need_data = false;
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}
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if (ADDR2LAST(src + count))
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need_data = true;
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byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
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} else {
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/* src is in L2 or L3 - so just dereference*/
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byte = src_byte[count];
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}
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if (dest_in_l1) {
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if (put_data) {
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data_out = isram_read(dest + count);
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put_data = false;
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}
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data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
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data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));
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if (ADDR2LAST(dest + count)) {
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put_data = true;
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isram_write(dest + count, data_out);
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}
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} else {
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/* dest in L2 or L3 - so just dereference */
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dest_byte[count] = byte;
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}
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}
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/* make sure we dump the last byte if necessary */
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if (dest_in_l1 && !put_data)
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isram_write(dest + count, data_out);
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return dest;
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}
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EXPORT_SYMBOL(isram_memcpy);
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2009-08-26 19:46:48 -06:00
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#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
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#define TEST_LEN 0x100
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static __init void hex_dump(unsigned char *buf, int len)
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{
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while (len--)
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pr_cont("%02x", *buf++);
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}
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static __init int isram_read_test(char *sdram, void *l1inst)
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{
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int i, ret = 0;
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uint64_t data1, data2;
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pr_info("INFO: running isram_read tests\n");
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/* setup some different data to play with */
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for (i = 0; i < TEST_LEN; ++i)
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sdram[i] = i;
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dma_memcpy(l1inst, sdram, TEST_LEN);
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/* make sure we can read the L1 inst */
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for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) {
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data1 = isram_read(l1inst + i);
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memcpy(&data2, sdram + i, sizeof(data2));
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if (memcmp(&data1, &data2, sizeof(uint64_t))) {
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pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
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l1inst + i, data1, data2);
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++ret;
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}
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}
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return ret;
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}
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static __init int isram_write_test(char *sdram, void *l1inst)
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{
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int i, ret = 0;
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uint64_t data1, data2;
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pr_info("INFO: running isram_write tests\n");
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/* setup some different data to play with */
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memset(sdram, 0, TEST_LEN * 2);
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dma_memcpy(l1inst, sdram, TEST_LEN);
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for (i = 0; i < TEST_LEN; ++i)
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sdram[i] = i;
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/* make sure we can write the L1 inst */
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for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) {
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memcpy(&data1, sdram + i, sizeof(data1));
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isram_write(l1inst + i, data1);
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data2 = isram_read(l1inst + i);
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if (memcmp(&data1, &data2, sizeof(uint64_t))) {
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pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
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l1inst + i, data1, data2);
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++ret;
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}
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}
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dma_memcpy(sdram + TEST_LEN, l1inst, TEST_LEN);
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if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) {
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pr_err("FAIL: isram_write() did not work properly\n");
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++ret;
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}
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return ret;
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}
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static __init int
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_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
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void *(*fmemcpy)(void *, const void *, size_t))
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{
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memset(sdram, pattern, TEST_LEN);
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fmemcpy(l1inst, sdram, TEST_LEN);
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fmemcpy(sdram + TEST_LEN, l1inst, TEST_LEN);
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if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) {
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pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
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smemcpy, l1inst, sdram, TEST_LEN, pattern);
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return 1;
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}
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return 0;
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}
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#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)
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static __init int isram_memcpy_test(char *sdram, void *l1inst)
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{
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int i, j, thisret, ret = 0;
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/* check broad isram_memcpy() */
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pr_info("INFO: running broad isram_memcpy tests\n");
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for (i = 0xf; i >= 0; --i)
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ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);
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/* check read of small, unaligned, and hardware 64bit limits */
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pr_info("INFO: running isram_memcpy (read) tests\n");
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for (i = 0; i < TEST_LEN; ++i)
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sdram[i] = i;
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dma_memcpy(l1inst, sdram, TEST_LEN);
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thisret = 0;
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for (i = 0; i < TEST_LEN - 32; ++i) {
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unsigned char cmp[32];
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for (j = 1; j <= 32; ++j) {
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memset(cmp, 0, sizeof(cmp));
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isram_memcpy(cmp, l1inst + i, j);
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if (memcmp(cmp, sdram + i, j)) {
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pr_err("FAIL: %p:", l1inst + 1);
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hex_dump(cmp, j);
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pr_cont(" SDRAM:");
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hex_dump(sdram + i, j);
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pr_cont("\n");
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if (++thisret > 20) {
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pr_err("FAIL: skipping remaining series\n");
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i = TEST_LEN;
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break;
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}
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}
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}
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}
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ret += thisret;
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/* check write of small, unaligned, and hardware 64bit limits */
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pr_info("INFO: running isram_memcpy (write) tests\n");
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memset(sdram + TEST_LEN, 0, TEST_LEN);
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dma_memcpy(l1inst, sdram + TEST_LEN, TEST_LEN);
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thisret = 0;
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for (i = 0; i < TEST_LEN - 32; ++i) {
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unsigned char cmp[32];
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for (j = 1; j <= 32; ++j) {
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isram_memcpy(l1inst + i, sdram + i, j);
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dma_memcpy(cmp, l1inst + i, j);
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if (memcmp(cmp, sdram + i, j)) {
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pr_err("FAIL: %p:", l1inst + i);
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hex_dump(cmp, j);
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pr_cont(" SDRAM:");
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hex_dump(sdram + i, j);
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pr_cont("\n");
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if (++thisret > 20) {
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pr_err("FAIL: skipping remaining series\n");
|
|
|
|
i = TEST_LEN;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ret += thisret;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __init int isram_test_init(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
char *sdram;
|
|
|
|
void *l1inst;
|
|
|
|
|
|
|
|
sdram = kmalloc(TEST_LEN * 2, GFP_KERNEL);
|
|
|
|
if (!sdram) {
|
|
|
|
pr_warning("SKIP: could not allocate sdram\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
l1inst = l1_inst_sram_alloc(TEST_LEN);
|
|
|
|
if (!l1inst) {
|
|
|
|
kfree(sdram);
|
|
|
|
pr_warning("SKIP: could not allocate L1 inst\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* sanity check initial L1 inst state */
|
|
|
|
ret = 1;
|
|
|
|
pr_info("INFO: running initial dma_memcpy checks\n");
|
|
|
|
if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
|
|
|
|
goto abort;
|
|
|
|
if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
|
|
|
|
goto abort;
|
|
|
|
|
|
|
|
ret = 0;
|
|
|
|
ret += isram_read_test(sdram, l1inst);
|
|
|
|
ret += isram_write_test(sdram, l1inst);
|
|
|
|
ret += isram_memcpy_test(sdram, l1inst);
|
|
|
|
|
|
|
|
abort:
|
|
|
|
sram_free(l1inst);
|
|
|
|
kfree(sdram);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
pr_info("PASS: all tests worked !\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
late_initcall(isram_test_init);
|
|
|
|
|
|
|
|
static __exit void isram_test_exit(void)
|
|
|
|
{
|
|
|
|
/* stub to allow unloading */
|
|
|
|
}
|
|
|
|
module_exit(isram_test_exit);
|
|
|
|
|
|
|
|
#endif
|