drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "msm_drv.h"
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2013-07-19 10:59:32 -06:00
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#include "msm_gpu.h"
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2013-11-30 14:12:10 -07:00
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#include "msm_kms.h"
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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static void msm_fb_output_poll_changed(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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if (priv->fbdev)
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drm_fb_helper_hotplug_event(priv->fbdev);
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}
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static const struct drm_mode_config_funcs mode_config_funcs = {
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.fb_create = msm_framebuffer_create,
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.output_poll_changed = msm_fb_output_poll_changed,
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};
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2013-11-16 10:56:06 -07:00
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int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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{
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struct msm_drm_private *priv = dev->dev_private;
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2013-11-16 10:56:06 -07:00
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int idx = priv->num_mmus++;
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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2013-11-16 10:56:06 -07:00
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if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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return -EINVAL;
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2013-11-16 10:56:06 -07:00
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priv->mmus[idx] = mmu;
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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return idx;
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}
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#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
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static bool reglog = false;
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MODULE_PARM_DESC(reglog, "Enable register read/write logging");
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module_param(reglog, bool, 0600);
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#else
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#define reglog 0
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#endif
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2013-11-16 10:56:06 -07:00
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static char *vram;
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MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
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module_param(vram, charp, 0);
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2014-03-03 12:19:12 -07:00
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/*
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* Util/helpers:
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*/
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
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const char *dbgname)
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{
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struct resource *res;
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unsigned long size;
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void __iomem *ptr;
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if (name)
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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else
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
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return ERR_PTR(-EINVAL);
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}
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size = resource_size(res);
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ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
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if (!ptr) {
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dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
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return ERR_PTR(-ENOMEM);
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}
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if (reglog)
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printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
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return ptr;
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}
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void msm_writel(u32 data, void __iomem *addr)
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{
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if (reglog)
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printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
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writel(data, addr);
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}
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u32 msm_readl(const void __iomem *addr)
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{
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u32 val = readl(addr);
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if (reglog)
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printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
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return val;
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}
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/*
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* DRM operations:
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*/
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static int msm_unload(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_kms *kms = priv->kms;
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2013-07-19 10:59:32 -06:00
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struct msm_gpu *gpu = priv->gpu;
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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drm_kms_helper_poll_fini(dev);
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drm_mode_config_cleanup(dev);
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drm_vblank_cleanup(dev);
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pm_runtime_get_sync(dev->dev);
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drm_irq_uninstall(dev);
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pm_runtime_put_sync(dev->dev);
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flush_workqueue(priv->wq);
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destroy_workqueue(priv->wq);
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if (kms) {
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pm_runtime_disable(dev->dev);
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kms->funcs->destroy(kms);
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}
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2013-07-19 10:59:32 -06:00
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if (gpu) {
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mutex_lock(&dev->struct_mutex);
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gpu->funcs->pm_suspend(gpu);
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gpu->funcs->destroy(gpu);
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mutex_unlock(&dev->struct_mutex);
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}
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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2013-11-16 10:56:06 -07:00
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if (priv->vram.paddr) {
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DEFINE_DMA_ATTRS(attrs);
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dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
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drm_mm_takedown(&priv->vram.mm);
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dma_free_attrs(dev->dev, priv->vram.size, NULL,
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priv->vram.paddr, &attrs);
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}
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2014-03-03 12:19:12 -07:00
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component_unbind_all(dev->dev, dev);
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
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dev->dev_private = NULL;
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kfree(priv);
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return 0;
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}
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drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 15:51:47 -07:00
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static int get_mdp_ver(struct platform_device *pdev)
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{
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#ifdef CONFIG_OF
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2014-06-05 11:30:58 -06:00
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static const struct of_device_id match_types[] = { {
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drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 15:51:47 -07:00
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.compatible = "qcom,mdss_mdp",
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.data = (void *)5,
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}, {
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/* end node */
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} };
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struct device *dev = &pdev->dev;
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const struct of_device_id *match;
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match = of_match_node(match_types, dev->of_node);
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if (match)
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return (int)match->data;
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#endif
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return 4;
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}
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|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
static int msm_load(struct drm_device *dev, unsigned long flags)
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{
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struct platform_device *pdev = dev->platformdev;
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|
|
struct msm_drm_private *priv;
|
|
|
|
struct msm_kms *kms;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv) {
|
|
|
|
dev_err(dev->dev, "failed to allocate private data\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->dev_private = priv;
|
|
|
|
|
|
|
|
priv->wq = alloc_ordered_workqueue("msm", 0);
|
2013-07-19 10:59:32 -06:00
|
|
|
init_waitqueue_head(&priv->fence_event);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
|
|
|
|
INIT_LIST_HEAD(&priv->inactive_list);
|
2013-09-14 12:01:55 -06:00
|
|
|
INIT_LIST_HEAD(&priv->fence_cbs);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
|
|
|
|
drm_mode_config_init(dev);
|
|
|
|
|
2013-11-16 10:56:06 -07:00
|
|
|
/* if we have no IOMMU, then we need to use carveout allocator.
|
|
|
|
* Grab the entire CMA chunk carved out in early startup in
|
|
|
|
* mach-msm:
|
|
|
|
*/
|
|
|
|
if (!iommu_present(&platform_bus_type)) {
|
|
|
|
DEFINE_DMA_ATTRS(attrs);
|
|
|
|
unsigned long size;
|
|
|
|
void *p;
|
|
|
|
|
|
|
|
DBG("using %s VRAM carveout", vram);
|
|
|
|
size = memparse(vram, NULL);
|
|
|
|
priv->vram.size = size;
|
|
|
|
|
|
|
|
drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
|
|
|
|
|
|
|
|
dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
|
|
|
|
dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
|
|
|
|
|
|
|
|
/* note that for no-kernel-mapping, the vaddr returned
|
|
|
|
* is bogus, but non-null if allocation succeeded:
|
|
|
|
*/
|
|
|
|
p = dma_alloc_attrs(dev->dev, size,
|
2014-06-02 05:25:56 -06:00
|
|
|
&priv->vram.paddr, GFP_KERNEL, &attrs);
|
2013-11-16 10:56:06 -07:00
|
|
|
if (!p) {
|
|
|
|
dev_err(dev->dev, "failed to allocate VRAM\n");
|
|
|
|
priv->vram.paddr = 0;
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_info(dev->dev, "VRAM: %08x->%08x\n",
|
|
|
|
(uint32_t)priv->vram.paddr,
|
|
|
|
(uint32_t)(priv->vram.paddr + size));
|
|
|
|
}
|
|
|
|
|
2014-03-03 12:19:12 -07:00
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
|
|
|
|
/* Bind all our sub-components: */
|
|
|
|
ret = component_bind_all(dev->dev, dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 15:51:47 -07:00
|
|
|
switch (get_mdp_ver(pdev)) {
|
|
|
|
case 4:
|
|
|
|
kms = mdp4_kms_init(dev);
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
kms = mdp5_kms_init(dev);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
kms = ERR_PTR(-ENODEV);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
if (IS_ERR(kms)) {
|
|
|
|
/*
|
|
|
|
* NOTE: once we have GPU support, having no kms should not
|
|
|
|
* be considered fatal.. ideally we would still support gpu
|
|
|
|
* and (for example) use dmabuf/prime to share buffers with
|
|
|
|
* imx drm driver on iMX5
|
|
|
|
*/
|
|
|
|
dev_err(dev->dev, "failed to load kms\n");
|
2013-09-16 15:19:54 -06:00
|
|
|
ret = PTR_ERR(kms);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->kms = kms;
|
|
|
|
|
|
|
|
if (kms) {
|
|
|
|
pm_runtime_enable(dev->dev);
|
|
|
|
ret = kms->funcs->hw_init(kms);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev->dev, "kms hw init failed: %d\n", ret);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->mode_config.min_width = 0;
|
|
|
|
dev->mode_config.min_height = 0;
|
|
|
|
dev->mode_config.max_width = 2048;
|
|
|
|
dev->mode_config.max_height = 2048;
|
|
|
|
dev->mode_config.funcs = &mode_config_funcs;
|
|
|
|
|
|
|
|
ret = drm_vblank_init(dev, 1);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev->dev, "failed to initialize vblank\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_get_sync(dev->dev);
|
2013-11-03 13:09:27 -07:00
|
|
|
ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
pm_runtime_put_sync(dev->dev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev->dev, "failed to install IRQ handler\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_DRM_MSM_FBDEV
|
|
|
|
priv->fbdev = msm_fbdev_init(dev);
|
|
|
|
#endif
|
|
|
|
|
2014-05-30 12:47:38 -06:00
|
|
|
ret = msm_debugfs_late_init(dev);
|
|
|
|
if (ret)
|
|
|
|
goto fail;
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
drm_kms_helper_poll_init(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail:
|
|
|
|
msm_unload(dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-07-19 10:59:32 -06:00
|
|
|
static void load_gpu(struct drm_device *dev)
|
|
|
|
{
|
2014-07-11 09:59:22 -06:00
|
|
|
static DEFINE_MUTEX(init_lock);
|
2013-07-19 10:59:32 -06:00
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_gpu *gpu;
|
|
|
|
|
2014-07-11 09:59:22 -06:00
|
|
|
mutex_lock(&init_lock);
|
|
|
|
|
2013-07-19 10:59:32 -06:00
|
|
|
if (priv->gpu)
|
2014-07-11 09:59:22 -06:00
|
|
|
goto out;
|
2013-07-19 10:59:32 -06:00
|
|
|
|
|
|
|
gpu = a3xx_gpu_init(dev);
|
|
|
|
if (IS_ERR(gpu)) {
|
|
|
|
dev_warn(dev->dev, "failed to load a3xx gpu\n");
|
|
|
|
gpu = NULL;
|
|
|
|
/* not fatal */
|
|
|
|
}
|
|
|
|
|
|
|
|
if (gpu) {
|
|
|
|
int ret;
|
2014-07-11 09:59:22 -06:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2013-07-19 10:59:32 -06:00
|
|
|
gpu->funcs->pm_resume(gpu);
|
2014-07-11 09:59:22 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2013-07-19 10:59:32 -06:00
|
|
|
ret = gpu->funcs->hw_init(gpu);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
|
|
|
|
gpu->funcs->destroy(gpu);
|
|
|
|
gpu = NULL;
|
2014-01-11 14:25:08 -07:00
|
|
|
} else {
|
|
|
|
/* give inactive pm a chance to kick in: */
|
|
|
|
msm_gpu_retire(gpu);
|
2013-07-19 10:59:32 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->gpu = gpu;
|
2014-01-11 14:25:08 -07:00
|
|
|
|
2014-07-11 09:59:22 -06:00
|
|
|
out:
|
|
|
|
mutex_unlock(&init_lock);
|
2013-07-19 10:59:32 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_open(struct drm_device *dev, struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct msm_file_private *ctx;
|
|
|
|
|
|
|
|
/* For now, load gpu on open.. to avoid the requirement of having
|
|
|
|
* firmware in the initrd.
|
|
|
|
*/
|
|
|
|
load_gpu(dev);
|
|
|
|
|
|
|
|
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
|
|
|
|
if (!ctx)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
file->driver_priv = ctx;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
static void msm_preclose(struct drm_device *dev, struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
2013-07-19 10:59:32 -06:00
|
|
|
struct msm_file_private *ctx = file->driver_priv;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
struct msm_kms *kms = priv->kms;
|
2013-07-19 10:59:32 -06:00
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
if (kms)
|
|
|
|
kms->funcs->preclose(kms, file);
|
2013-07-19 10:59:32 -06:00
|
|
|
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
if (ctx == priv->lastctx)
|
|
|
|
priv->lastctx = NULL;
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
kfree(ctx);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_lastclose(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
2014-05-30 10:29:48 -06:00
|
|
|
if (priv->fbdev)
|
|
|
|
drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
}
|
|
|
|
|
2013-12-11 03:34:42 -07:00
|
|
|
static irqreturn_t msm_irq(int irq, void *arg)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
{
|
|
|
|
struct drm_device *dev = arg;
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
BUG_ON(!kms);
|
|
|
|
return kms->funcs->irq(kms);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_irq_preinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
BUG_ON(!kms);
|
|
|
|
kms->funcs->irq_preinstall(kms);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
BUG_ON(!kms);
|
|
|
|
return kms->funcs->irq_postinstall(kms);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_irq_uninstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
BUG_ON(!kms);
|
|
|
|
kms->funcs->irq_uninstall(kms);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_enable_vblank(struct drm_device *dev, int crtc_id)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
if (!kms)
|
|
|
|
return -ENXIO;
|
|
|
|
DBG("dev=%p, crtc=%d", dev, crtc_id);
|
|
|
|
return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_disable_vblank(struct drm_device *dev, int crtc_id)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
if (!kms)
|
|
|
|
return;
|
|
|
|
DBG("dev=%p, crtc=%d", dev, crtc_id);
|
|
|
|
kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DRM debugfs:
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
2013-07-19 10:59:32 -06:00
|
|
|
static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_gpu *gpu = priv->gpu;
|
|
|
|
|
|
|
|
if (gpu) {
|
|
|
|
seq_printf(m, "%s Status:\n", gpu->name);
|
|
|
|
gpu->funcs->show(gpu, m);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
2013-07-19 10:59:32 -06:00
|
|
|
struct msm_gpu *gpu = priv->gpu;
|
|
|
|
|
|
|
|
if (gpu) {
|
|
|
|
seq_printf(m, "Active Objects (%s):\n", gpu->name);
|
|
|
|
msm_gem_describe_objects(&gpu->active_list, m);
|
|
|
|
}
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
|
2013-07-19 10:59:32 -06:00
|
|
|
seq_printf(m, "Inactive Objects:\n");
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
msm_gem_describe_objects(&priv->inactive_list, m);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
|
|
|
|
{
|
2013-12-11 06:24:46 -07:00
|
|
|
return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct drm_framebuffer *fb, *fbdev_fb = NULL;
|
|
|
|
|
|
|
|
if (priv->fbdev) {
|
|
|
|
seq_printf(m, "fbcon ");
|
|
|
|
fbdev_fb = priv->fbdev->fb;
|
|
|
|
msm_framebuffer_describe(fbdev_fb, m);
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_lock(&dev->mode_config.fb_lock);
|
|
|
|
list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
|
|
|
|
if (fb == fbdev_fb)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
seq_printf(m, "user ");
|
|
|
|
msm_framebuffer_describe(fb, m);
|
|
|
|
}
|
|
|
|
mutex_unlock(&dev->mode_config.fb_lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int show_locked(struct seq_file *m, void *arg)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
int (*show)(struct drm_device *dev, struct seq_file *m) =
|
|
|
|
node->info_ent->data;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = show(dev, m);
|
|
|
|
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct drm_info_list msm_debugfs_list[] = {
|
2013-07-19 10:59:32 -06:00
|
|
|
{"gpu", show_locked, 0, msm_gpu_show},
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
{"gem", show_locked, 0, msm_gem_show},
|
|
|
|
{ "mm", show_locked, 0, msm_mm_show },
|
|
|
|
{ "fb", show_locked, 0, msm_fb_show },
|
|
|
|
};
|
|
|
|
|
2014-05-30 12:47:38 -06:00
|
|
|
static int late_init_minor(struct drm_minor *minor)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!minor)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = msm_rd_debugfs_init(minor);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(minor->dev->dev, "could not install rd debugfs\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-05-30 12:49:43 -06:00
|
|
|
ret = msm_perf_debugfs_init(minor);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(minor->dev->dev, "could not install perf debugfs\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-05-30 12:47:38 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int msm_debugfs_late_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = late_init_minor(dev->primary);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
ret = late_init_minor(dev->render);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
ret = late_init_minor(dev->control);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
static int msm_debugfs_init(struct drm_minor *minor)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = minor->dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = drm_debugfs_create_files(msm_debugfs_list,
|
|
|
|
ARRAY_SIZE(msm_debugfs_list),
|
|
|
|
minor->debugfs_root, minor);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev->dev, "could not install msm_debugfs_list\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-05-30 12:47:38 -06:00
|
|
|
return 0;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_debugfs_cleanup(struct drm_minor *minor)
|
|
|
|
{
|
|
|
|
drm_debugfs_remove_files(msm_debugfs_list,
|
|
|
|
ARRAY_SIZE(msm_debugfs_list), minor);
|
2014-05-30 12:47:38 -06:00
|
|
|
if (!minor->dev->dev_private)
|
|
|
|
return;
|
|
|
|
msm_rd_debugfs_cleanup(minor);
|
2014-05-30 12:49:43 -06:00
|
|
|
msm_perf_debugfs_cleanup(minor);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-07-19 10:59:32 -06:00
|
|
|
/*
|
|
|
|
* Fences:
|
|
|
|
*/
|
|
|
|
|
|
|
|
int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
|
|
|
|
struct timespec *timeout)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
2013-09-11 15:34:07 -06:00
|
|
|
if (!priv->gpu)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (fence > priv->gpu->submitted_fence) {
|
|
|
|
DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
|
|
|
|
fence, priv->gpu->submitted_fence);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!timeout) {
|
|
|
|
/* no-wait: */
|
|
|
|
ret = fence_completed(dev, fence) ? 0 : -EBUSY;
|
|
|
|
} else {
|
|
|
|
unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
|
|
|
|
unsigned long start_jiffies = jiffies;
|
|
|
|
unsigned long remaining_jiffies;
|
|
|
|
|
|
|
|
if (time_after(start_jiffies, timeout_jiffies))
|
|
|
|
remaining_jiffies = 0;
|
|
|
|
else
|
|
|
|
remaining_jiffies = timeout_jiffies - start_jiffies;
|
|
|
|
|
|
|
|
ret = wait_event_interruptible_timeout(priv->fence_event,
|
|
|
|
fence_completed(dev, fence),
|
|
|
|
remaining_jiffies);
|
|
|
|
|
|
|
|
if (ret == 0) {
|
|
|
|
DBG("timeout waiting for fence: %u (completed: %u)",
|
|
|
|
fence, priv->completed_fence);
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
} else if (ret != -ERESTARTSYS) {
|
|
|
|
ret = 0;
|
|
|
|
}
|
2013-07-19 10:59:32 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-09-14 12:01:55 -06:00
|
|
|
/* called from workqueue */
|
2013-07-19 10:59:32 -06:00
|
|
|
void msm_update_fence(struct drm_device *dev, uint32_t fence)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
|
2013-09-14 12:01:55 -06:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
priv->completed_fence = max(fence, priv->completed_fence);
|
|
|
|
|
|
|
|
while (!list_empty(&priv->fence_cbs)) {
|
|
|
|
struct msm_fence_cb *cb;
|
|
|
|
|
|
|
|
cb = list_first_entry(&priv->fence_cbs,
|
|
|
|
struct msm_fence_cb, work.entry);
|
|
|
|
|
|
|
|
if (cb->fence > priv->completed_fence)
|
|
|
|
break;
|
|
|
|
|
|
|
|
list_del_init(&cb->work.entry);
|
|
|
|
queue_work(priv->wq, &cb->work);
|
2013-07-19 10:59:32 -06:00
|
|
|
}
|
2013-09-14 12:01:55 -06:00
|
|
|
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
wake_up_all(&priv->fence_event);
|
|
|
|
}
|
|
|
|
|
|
|
|
void __msm_fence_worker(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
|
|
|
|
cb->func(cb);
|
2013-07-19 10:59:32 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DRM ioctls:
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int msm_ioctl_get_param(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct drm_msm_param *args = data;
|
|
|
|
struct msm_gpu *gpu;
|
|
|
|
|
|
|
|
/* for now, we just have 3d pipe.. eventually this would need to
|
|
|
|
* be more clever to dispatch to appropriate gpu module:
|
|
|
|
*/
|
|
|
|
if (args->pipe != MSM_PIPE_3D0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
gpu = priv->gpu;
|
|
|
|
|
|
|
|
if (!gpu)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
return gpu->funcs->get_param(gpu, args->param, &args->value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_new *args = data;
|
2014-03-03 07:42:33 -07:00
|
|
|
|
|
|
|
if (args->flags & ~MSM_BO_FLAGS) {
|
|
|
|
DRM_ERROR("invalid flags: %08x\n", args->flags);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-07-19 10:59:32 -06:00
|
|
|
return msm_gem_new_handle(dev, file, args->size,
|
|
|
|
args->flags, &args->handle);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec })
|
|
|
|
|
|
|
|
static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_cpu_prep *args = data;
|
|
|
|
struct drm_gem_object *obj;
|
|
|
|
int ret;
|
|
|
|
|
2014-03-03 07:42:33 -07:00
|
|
|
if (args->op & ~MSM_PREP_FLAGS) {
|
|
|
|
DRM_ERROR("invalid op: %08x\n", args->op);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-07-19 10:59:32 -06:00
|
|
|
obj = drm_gem_object_lookup(dev, file, args->handle);
|
|
|
|
if (!obj)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout));
|
|
|
|
|
|
|
|
drm_gem_object_unreference_unlocked(obj);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_cpu_fini *args = data;
|
|
|
|
struct drm_gem_object *obj;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
obj = drm_gem_object_lookup(dev, file, args->handle);
|
|
|
|
if (!obj)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
ret = msm_gem_cpu_fini(obj);
|
|
|
|
|
|
|
|
drm_gem_object_unreference_unlocked(obj);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_info *args = data;
|
|
|
|
struct drm_gem_object *obj;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (args->pad)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
obj = drm_gem_object_lookup(dev, file, args->handle);
|
|
|
|
if (!obj)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
args->offset = msm_gem_mmap_offset(obj);
|
|
|
|
|
|
|
|
drm_gem_object_unreference_unlocked(obj);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_wait_fence *args = data;
|
2014-03-03 07:42:33 -07:00
|
|
|
|
|
|
|
if (args->pad) {
|
|
|
|
DRM_ERROR("invalid pad: %08x\n", args->pad);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return msm_wait_fence_interruptable(dev, args->fence,
|
|
|
|
&TS(args->timeout));
|
2013-07-19 10:59:32 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_ioctl_desc msm_ioctls[] = {
|
2013-09-28 10:01:25 -06:00
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
|
2013-07-19 10:59:32 -06:00
|
|
|
};
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
static const struct vm_operations_struct vm_ops = {
|
|
|
|
.fault = msm_gem_fault,
|
|
|
|
.open = drm_gem_vm_open,
|
|
|
|
.close = drm_gem_vm_close,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct file_operations fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = drm_open,
|
|
|
|
.release = drm_release,
|
|
|
|
.unlocked_ioctl = drm_ioctl,
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
|
|
.compat_ioctl = drm_compat_ioctl,
|
|
|
|
#endif
|
|
|
|
.poll = drm_poll,
|
|
|
|
.read = drm_read,
|
|
|
|
.llseek = no_llseek,
|
|
|
|
.mmap = msm_gem_mmap,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct drm_driver msm_driver = {
|
2013-09-28 09:28:35 -06:00
|
|
|
.driver_features = DRIVER_HAVE_IRQ |
|
|
|
|
DRIVER_GEM |
|
|
|
|
DRIVER_PRIME |
|
2013-09-28 10:01:25 -06:00
|
|
|
DRIVER_RENDER |
|
2013-09-28 09:28:35 -06:00
|
|
|
DRIVER_MODESET,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
.load = msm_load,
|
|
|
|
.unload = msm_unload,
|
2013-07-19 10:59:32 -06:00
|
|
|
.open = msm_open,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
.preclose = msm_preclose,
|
|
|
|
.lastclose = msm_lastclose,
|
|
|
|
.irq_handler = msm_irq,
|
|
|
|
.irq_preinstall = msm_irq_preinstall,
|
|
|
|
.irq_postinstall = msm_irq_postinstall,
|
|
|
|
.irq_uninstall = msm_irq_uninstall,
|
|
|
|
.get_vblank_counter = drm_vblank_count,
|
|
|
|
.enable_vblank = msm_enable_vblank,
|
|
|
|
.disable_vblank = msm_disable_vblank,
|
|
|
|
.gem_free_object = msm_gem_free_object,
|
|
|
|
.gem_vm_ops = &vm_ops,
|
|
|
|
.dumb_create = msm_gem_dumb_create,
|
|
|
|
.dumb_map_offset = msm_gem_dumb_map_offset,
|
2013-09-28 08:13:04 -06:00
|
|
|
.dumb_destroy = drm_gem_dumb_destroy,
|
2013-09-28 09:28:35 -06:00
|
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
|
|
.gem_prime_export = drm_gem_prime_export,
|
|
|
|
.gem_prime_import = drm_gem_prime_import,
|
|
|
|
.gem_prime_pin = msm_gem_prime_pin,
|
|
|
|
.gem_prime_unpin = msm_gem_prime_unpin,
|
|
|
|
.gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
|
|
|
|
.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
|
|
|
|
.gem_prime_vmap = msm_gem_prime_vmap,
|
|
|
|
.gem_prime_vunmap = msm_gem_prime_vunmap,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
.debugfs_init = msm_debugfs_init,
|
|
|
|
.debugfs_cleanup = msm_debugfs_cleanup,
|
|
|
|
#endif
|
2013-07-19 10:59:32 -06:00
|
|
|
.ioctls = msm_ioctls,
|
|
|
|
.num_ioctls = DRM_MSM_NUM_IOCTLS,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
.fops = &fops,
|
|
|
|
.name = "msm",
|
|
|
|
.desc = "MSM Snapdragon DRM",
|
|
|
|
.date = "20130625",
|
|
|
|
.major = 1,
|
|
|
|
.minor = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int msm_pm_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
drm_kms_helper_poll_disable(ddev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_pm_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
drm_kms_helper_poll_enable(ddev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct dev_pm_ops msm_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
|
|
|
|
};
|
|
|
|
|
2014-03-03 12:19:12 -07:00
|
|
|
/*
|
|
|
|
* Componentized driver support:
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_OF
|
|
|
|
/* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx
|
|
|
|
* (or probably any other).. so probably some room for some helpers
|
|
|
|
*/
|
|
|
|
static int compare_of(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
return dev->of_node == data;
|
|
|
|
}
|
2013-12-15 14:23:05 -07:00
|
|
|
|
|
|
|
static int add_components(struct device *dev, struct component_match **matchptr,
|
|
|
|
const char *name)
|
|
|
|
{
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = 0; ; i++) {
|
|
|
|
struct device_node *node;
|
|
|
|
|
|
|
|
node = of_parse_phandle(np, name, i);
|
|
|
|
if (!node)
|
|
|
|
break;
|
|
|
|
|
|
|
|
component_match_add(dev, matchptr, compare_of, node);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2014-04-19 04:20:42 -06:00
|
|
|
#else
|
|
|
|
static int compare_dev(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
return dev == data;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int msm_drm_bind(struct device *dev)
|
|
|
|
{
|
|
|
|
return drm_platform_init(&msm_driver, to_platform_device(dev));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_drm_unbind(struct device *dev)
|
|
|
|
{
|
|
|
|
drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct component_master_ops msm_drm_ops = {
|
|
|
|
.bind = msm_drm_bind,
|
|
|
|
.unbind = msm_drm_unbind,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Platform driver:
|
|
|
|
*/
|
2014-03-03 12:19:12 -07:00
|
|
|
|
2014-04-19 04:20:42 -06:00
|
|
|
static int msm_pdev_probe(struct platform_device *pdev)
|
2014-03-03 12:19:12 -07:00
|
|
|
{
|
2014-04-19 04:20:42 -06:00
|
|
|
struct component_match *match = NULL;
|
|
|
|
#ifdef CONFIG_OF
|
2013-12-15 14:23:05 -07:00
|
|
|
add_components(&pdev->dev, &match, "connectors");
|
|
|
|
add_components(&pdev->dev, &match, "gpus");
|
2014-03-03 12:19:12 -07:00
|
|
|
#else
|
|
|
|
/* For non-DT case, it kinda sucks. We don't actually have a way
|
|
|
|
* to know whether or not we are waiting for certain devices (or if
|
|
|
|
* they are simply not present). But for non-DT we only need to
|
|
|
|
* care about apq8064/apq8060/etc (all mdp4/a3xx):
|
|
|
|
*/
|
|
|
|
static const char *devnames[] = {
|
|
|
|
"hdmi_msm.0", "kgsl-3d0.0",
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
DBG("Adding components..");
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(devnames); i++) {
|
|
|
|
struct device *dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dev = bus_find_device_by_name(&platform_bus_type,
|
|
|
|
NULL, devnames[i]);
|
|
|
|
if (!dev) {
|
|
|
|
dev_info(master, "still waiting for %s\n", devnames[i]);
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
}
|
|
|
|
|
2014-04-19 04:20:42 -06:00
|
|
|
component_match_add(&pdev->dev, &match, compare_dev, dev);
|
2014-03-03 12:19:12 -07:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-11-16 10:56:06 -07:00
|
|
|
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
|
2014-04-19 04:20:42 -06:00
|
|
|
return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_pdev_remove(struct platform_device *pdev)
|
|
|
|
{
|
2014-03-03 12:19:12 -07:00
|
|
|
component_master_del(&pdev->dev, &msm_drm_ops);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct platform_device_id msm_id[] = {
|
|
|
|
{ "mdp", 0 },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 15:51:47 -07:00
|
|
|
static const struct of_device_id dt_match[] = {
|
2013-12-15 14:23:05 -07:00
|
|
|
{ .compatible = "qcom,mdp" }, /* mdp4 */
|
|
|
|
{ .compatible = "qcom,mdss_mdp" }, /* mdp5 */
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 15:51:47 -07:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, dt_match);
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
static struct platform_driver msm_platform_driver = {
|
|
|
|
.probe = msm_pdev_probe,
|
|
|
|
.remove = msm_pdev_remove,
|
|
|
|
.driver = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.name = "msm",
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 15:51:47 -07:00
|
|
|
.of_match_table = dt_match,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
.pm = &msm_pm_ops,
|
|
|
|
},
|
|
|
|
.id_table = msm_id,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init msm_drm_register(void)
|
|
|
|
{
|
|
|
|
DBG("init");
|
|
|
|
hdmi_register();
|
2013-07-19 10:59:32 -06:00
|
|
|
a3xx_register();
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
return platform_driver_register(&msm_platform_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit msm_drm_unregister(void)
|
|
|
|
{
|
|
|
|
DBG("fini");
|
|
|
|
platform_driver_unregister(&msm_platform_driver);
|
|
|
|
hdmi_unregister();
|
2013-07-19 10:59:32 -06:00
|
|
|
a3xx_unregister();
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 10:44:06 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
module_init(msm_drm_register);
|
|
|
|
module_exit(msm_drm_unregister);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
|
|
|
|
MODULE_DESCRIPTION("MSM DRM Driver");
|
|
|
|
MODULE_LICENSE("GPL");
|