2006-08-29 16:12:40 -06:00
|
|
|
/*
|
|
|
|
* pata_sis.c - SiS ATA driver
|
|
|
|
*
|
2008-10-27 09:09:10 -06:00
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* (C) 2005 Red Hat
|
2009-12-03 12:32:13 -07:00
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* (C) 2007,2009 Bartlomiej Zolnierkiewicz
|
2006-08-29 16:12:40 -06:00
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*
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* Based upon linux/drivers/ide/pci/sis5513.c
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* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
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* Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
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* SiS Taiwan : for direct support and hardware.
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* Daniela Engert : for initial ATA100 advices and numerous others.
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* John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
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|
* for checking code correctness, providing patches.
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* Original tests and design on the SiS620 chipset.
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* ATA100 tests and design on the SiS735 chipset.
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* ATA16/33 support from specs
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* ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
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*
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*
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* TODO
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* Check MWDMA on drives that don't support MWDMA speed pio cycles ?
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* More Testing
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|
|
|
*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/ata.h>
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2007-02-16 02:40:04 -07:00
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#include "sis.h"
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2006-08-29 16:12:40 -06:00
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#define DRV_NAME "pata_sis"
|
2007-07-31 14:02:41 -06:00
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#define DRV_VERSION "0.5.2"
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2006-08-29 16:12:40 -06:00
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struct sis_chipset {
|
2007-05-04 04:43:58 -06:00
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u16 device; /* PCI host ID */
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const struct ata_port_info *info; /* Info block */
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2006-08-29 16:12:40 -06:00
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/* Probably add family, cable detect type etc here to clean
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|
up code later */
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};
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2007-01-08 17:01:19 -07:00
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struct sis_laptop {
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u16 device;
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u16 subvendor;
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|
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u16 subdevice;
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|
};
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static const struct sis_laptop sis_laptop[] = {
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/* devid, subvendor, subdev */
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{ 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
|
2007-08-22 15:56:43 -06:00
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{ 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
|
2011-09-07 10:23:22 -06:00
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{ 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
|
2007-01-08 17:01:19 -07:00
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/* end marker */
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|
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{ 0, }
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|
};
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static int sis_short_ata40(struct pci_dev *dev)
|
|
|
|
{
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|
const struct sis_laptop *lap = &sis_laptop[0];
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|
while (lap->device) {
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if (lap->device == dev->device &&
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lap->subvendor == dev->subsystem_vendor &&
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lap->subdevice == dev->subsystem_device)
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|
return 1;
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lap++;
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|
|
}
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return 0;
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|
|
|
}
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2006-08-29 16:12:40 -06:00
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|
|
/**
|
2011-09-07 10:23:22 -06:00
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* sis_old_port_base - return PCI configuration base for dev
|
2006-08-29 16:12:40 -06:00
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* @adev: device
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*
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* Returns the base of the PCI configuration registers for this port
|
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* number.
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|
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|
*/
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|
2007-05-21 08:00:53 -06:00
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static int sis_old_port_base(struct ata_device *adev)
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
2011-09-07 10:23:22 -06:00
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|
return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno);
|
2006-08-29 16:12:40 -06:00
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|
}
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|
2011-09-07 10:23:18 -06:00
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|
|
/**
|
2011-09-07 10:23:22 -06:00
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|
* sis_port_base - return PCI configuration base for dev
|
2011-09-07 10:23:18 -06:00
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* @adev: device
|
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|
*
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|
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* Returns the base of the PCI configuration registers for this port
|
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|
* number.
|
|
|
|
*/
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static int sis_port_base(struct ata_device *adev)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = adev->link->ap;
|
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
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|
|
int port = 0x40;
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|
|
u32 reg54;
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|
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/* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */
|
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|
|
pci_read_config_dword(pdev, 0x54, ®54);
|
|
|
|
if (reg54 & 0x40000000)
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|
|
port = 0x70;
|
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|
return port + (8 * ap->port_no) + (4 * adev->devno);
|
|
|
|
}
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|
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|
2006-08-29 16:12:40 -06:00
|
|
|
/**
|
2011-09-07 10:23:22 -06:00
|
|
|
* sis_133_cable_detect - check for 40/80 pin
|
2006-08-29 16:12:40 -06:00
|
|
|
* @ap: Port
|
libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 00:50:52 -07:00
|
|
|
* @deadline: deadline jiffies for the operation
|
2006-08-29 16:12:40 -06:00
|
|
|
*
|
|
|
|
* Perform cable detection for the later UDMA133 capable
|
|
|
|
* SiS chipset.
|
|
|
|
*/
|
|
|
|
|
2007-03-07 09:54:24 -07:00
|
|
|
static int sis_133_cable_detect(struct ata_port *ap)
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
|
|
u16 tmp;
|
|
|
|
|
|
|
|
/* The top bit of this register is the cable detect bit */
|
|
|
|
pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
|
2007-01-08 17:01:19 -07:00
|
|
|
if ((tmp & 0x8000) && !sis_short_ata40(pdev))
|
2007-03-07 09:54:24 -07:00
|
|
|
return ATA_CBL_PATA40;
|
|
|
|
return ATA_CBL_PATA80;
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2011-09-07 10:23:22 -06:00
|
|
|
* sis_66_cable_detect - check for 40/80 pin
|
2006-08-29 16:12:40 -06:00
|
|
|
* @ap: Port
|
|
|
|
*
|
|
|
|
* Perform cable detection on the UDMA66, UDMA100 and early UDMA133
|
|
|
|
* SiS IDE controllers.
|
|
|
|
*/
|
|
|
|
|
2007-03-07 09:54:24 -07:00
|
|
|
static int sis_66_cable_detect(struct ata_port *ap)
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
|
|
u8 tmp;
|
|
|
|
|
|
|
|
/* Older chips keep cable detect in bits 4/5 of reg 0x48 */
|
|
|
|
pci_read_config_byte(pdev, 0x48, &tmp);
|
|
|
|
tmp >>= ap->port_no;
|
2007-01-08 17:01:19 -07:00
|
|
|
if ((tmp & 0x10) && !sis_short_ata40(pdev))
|
2007-03-07 09:54:24 -07:00
|
|
|
return ATA_CBL_PATA40;
|
|
|
|
return ATA_CBL_PATA80;
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
2011-09-07 10:23:22 -06:00
|
|
|
* sis_pre_reset - probe begin
|
2007-08-06 03:36:23 -06:00
|
|
|
* @link: ATA link
|
libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 00:50:52 -07:00
|
|
|
* @deadline: deadline jiffies for the operation
|
2006-08-29 16:12:40 -06:00
|
|
|
*
|
|
|
|
* Set up cable type and use generic probe init
|
|
|
|
*/
|
|
|
|
|
2007-08-06 03:36:23 -06:00
|
|
|
static int sis_pre_reset(struct ata_link *link, unsigned long deadline)
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
|
|
|
static const struct pci_bits sis_enable_bits[] = {
|
|
|
|
{ 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
|
|
|
|
{ 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
|
|
|
|
};
|
2006-08-30 22:03:49 -06:00
|
|
|
|
2007-08-06 03:36:23 -06:00
|
|
|
struct ata_port *ap = link->ap;
|
2006-08-29 16:12:40 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
|
|
|
2007-03-07 09:54:24 -07:00
|
|
|
if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
|
|
|
|
return -ENOENT;
|
libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 00:50:52 -07:00
|
|
|
|
2007-05-25 13:50:24 -06:00
|
|
|
/* Clear the FIFO settings. We can't enable the FIFO until
|
|
|
|
we know we are poking at a disk */
|
|
|
|
pci_write_config_byte(pdev, 0x4B, 0);
|
2008-04-07 07:47:16 -06:00
|
|
|
return ata_sff_prereset(link, deadline);
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
2011-09-07 10:23:22 -06:00
|
|
|
* sis_set_fifo - Set RWP fifo bits for this device
|
2006-08-29 16:12:40 -06:00
|
|
|
* @ap: Port
|
|
|
|
* @adev: Device
|
|
|
|
*
|
|
|
|
* SIS chipsets implement prefetch/postwrite bits for each device
|
|
|
|
* on both channels. This functionality is not ATAPI compatible and
|
|
|
|
* must be configured according to the class of device present
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
|
|
u8 fifoctrl;
|
|
|
|
u8 mask = 0x11;
|
|
|
|
|
|
|
|
mask <<= (2 * ap->port_no);
|
|
|
|
mask <<= adev->devno;
|
|
|
|
|
|
|
|
/* This holds various bits including the FIFO control */
|
|
|
|
pci_read_config_byte(pdev, 0x4B, &fifoctrl);
|
|
|
|
fifoctrl &= ~mask;
|
|
|
|
|
|
|
|
/* Enable for ATA (disk) only */
|
|
|
|
if (adev->class == ATA_DEV_ATA)
|
|
|
|
fifoctrl |= mask;
|
|
|
|
pci_write_config_byte(pdev, 0x4B, fifoctrl);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sis_old_set_piomode - Initialize host controller PATA PIO timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Device we are configuring for.
|
|
|
|
*
|
|
|
|
* Set PIO mode for device, in host controller PCI config space. This
|
|
|
|
* function handles PIO set up for all chips that are pre ATA100 and
|
|
|
|
* also early ATA100 devices.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
2011-09-07 10:23:22 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2007-05-21 08:00:53 -06:00
|
|
|
int port = sis_old_port_base(adev);
|
2006-08-29 16:12:40 -06:00
|
|
|
u8 t1, t2;
|
|
|
|
int speed = adev->pio_mode - XFER_PIO_0;
|
|
|
|
|
2011-09-07 10:23:21 -06:00
|
|
|
static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
|
|
|
|
static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
sis_set_fifo(ap, adev);
|
|
|
|
|
|
|
|
pci_read_config_byte(pdev, port, &t1);
|
|
|
|
pci_read_config_byte(pdev, port + 1, &t2);
|
|
|
|
|
|
|
|
t1 &= ~0x0F; /* Clear active/recovery timings */
|
|
|
|
t2 &= ~0x07;
|
|
|
|
|
|
|
|
t1 |= active[speed];
|
|
|
|
t2 |= recovery[speed];
|
|
|
|
|
|
|
|
pci_write_config_byte(pdev, port, t1);
|
|
|
|
pci_write_config_byte(pdev, port + 1, t2);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2007-07-31 14:02:41 -06:00
|
|
|
* sis_100_set_piomode - Initialize host controller PATA PIO timings
|
2006-08-29 16:12:40 -06:00
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Device we are configuring for.
|
|
|
|
*
|
|
|
|
* Set PIO mode for device, in host controller PCI config space. This
|
|
|
|
* function handles PIO set up for ATA100 devices and early ATA133.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
2011-09-07 10:23:22 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2007-05-21 08:00:53 -06:00
|
|
|
int port = sis_old_port_base(adev);
|
2006-08-29 16:12:40 -06:00
|
|
|
int speed = adev->pio_mode - XFER_PIO_0;
|
|
|
|
|
2011-09-07 10:23:21 -06:00
|
|
|
static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
sis_set_fifo(ap, adev);
|
|
|
|
|
|
|
|
pci_write_config_byte(pdev, port, actrec[speed]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2009-12-07 09:41:25 -07:00
|
|
|
* sis_133_set_piomode - Initialize host controller PATA PIO timings
|
2006-08-29 16:12:40 -06:00
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Device we are configuring for.
|
|
|
|
*
|
|
|
|
* Set PIO mode for device, in host controller PCI config space. This
|
2009-12-07 09:41:25 -07:00
|
|
|
* function handles PIO set up for the later ATA133 devices.
|
2006-08-29 16:12:40 -06:00
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
2009-12-07 09:41:25 -07:00
|
|
|
static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
2011-09-07 10:23:22 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2011-09-07 10:23:18 -06:00
|
|
|
int port;
|
2006-08-29 16:12:40 -06:00
|
|
|
u32 t1;
|
2009-12-07 09:41:25 -07:00
|
|
|
int speed = adev->pio_mode - XFER_PIO_0;
|
2006-08-29 16:12:40 -06:00
|
|
|
|
2011-09-07 10:23:21 -06:00
|
|
|
static const u32 timing133[] = {
|
2006-08-29 16:12:40 -06:00
|
|
|
0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
|
|
|
|
0x0C266000,
|
|
|
|
0x04263000,
|
|
|
|
0x0C0A3000,
|
|
|
|
0x05093000
|
|
|
|
};
|
2011-09-07 10:23:21 -06:00
|
|
|
static const u32 timing100[] = {
|
2006-08-29 16:12:40 -06:00
|
|
|
0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
|
|
|
|
0x091C4000,
|
|
|
|
0x031C2000,
|
|
|
|
0x09072000,
|
|
|
|
0x04062000
|
|
|
|
};
|
|
|
|
|
|
|
|
sis_set_fifo(ap, adev);
|
|
|
|
|
2011-09-07 10:23:18 -06:00
|
|
|
port = sis_port_base(adev);
|
2006-08-29 16:12:40 -06:00
|
|
|
pci_read_config_dword(pdev, port, &t1);
|
|
|
|
t1 &= 0xC0C00FFF; /* Mask out timing */
|
|
|
|
|
|
|
|
if (t1 & 0x08) /* 100 or 133 ? */
|
|
|
|
t1 |= timing133[speed];
|
|
|
|
else
|
|
|
|
t1 |= timing100[speed];
|
|
|
|
pci_write_config_byte(pdev, port, t1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sis_old_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Device to program
|
|
|
|
*
|
|
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
|
|
|
* Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
|
|
|
|
* the old ide/pci driver.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
2011-09-07 10:23:22 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2006-08-29 16:12:40 -06:00
|
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
2007-05-21 08:00:53 -06:00
|
|
|
int drive_pci = sis_old_port_base(adev);
|
2006-08-29 16:12:40 -06:00
|
|
|
u16 timing;
|
|
|
|
|
2011-09-07 10:23:21 -06:00
|
|
|
static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
|
|
|
|
static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
pci_read_config_word(pdev, drive_pci, &timing);
|
|
|
|
|
|
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
|
|
|
/* bits 3-0 hold recovery timing bits 8-10 active timing and
|
2011-03-30 19:57:33 -06:00
|
|
|
the higher bits are dependent on the device */
|
2007-07-31 14:02:41 -06:00
|
|
|
timing &= ~0x870F;
|
2006-08-29 16:12:40 -06:00
|
|
|
timing |= mwdma_bits[speed];
|
|
|
|
} else {
|
|
|
|
/* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
|
|
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
|
|
|
timing &= ~0x6000;
|
|
|
|
timing |= udma_bits[speed];
|
|
|
|
}
|
2007-07-31 14:02:41 -06:00
|
|
|
pci_write_config_word(pdev, drive_pci, timing);
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sis_66_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Device to program
|
|
|
|
*
|
|
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
|
|
|
* Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
|
|
|
|
* the old ide/pci driver.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
2011-09-07 10:23:22 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2006-08-29 16:12:40 -06:00
|
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
2007-05-21 08:00:53 -06:00
|
|
|
int drive_pci = sis_old_port_base(adev);
|
2006-08-29 16:12:40 -06:00
|
|
|
u16 timing;
|
|
|
|
|
2007-09-21 01:29:05 -06:00
|
|
|
/* MWDMA 0-2 and UDMA 0-5 */
|
2011-09-07 10:23:21 -06:00
|
|
|
static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
|
|
|
|
static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
pci_read_config_word(pdev, drive_pci, &timing);
|
|
|
|
|
|
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
|
|
|
/* bits 3-0 hold recovery timing bits 8-10 active timing and
|
2011-03-30 19:57:33 -06:00
|
|
|
the higher bits are dependent on the device, bit 15 udma */
|
2007-05-21 08:00:53 -06:00
|
|
|
timing &= ~0x870F;
|
2006-08-29 16:12:40 -06:00
|
|
|
timing |= mwdma_bits[speed];
|
|
|
|
} else {
|
|
|
|
/* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
|
|
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
2007-05-21 08:00:53 -06:00
|
|
|
timing &= ~0xF000;
|
2006-08-29 16:12:40 -06:00
|
|
|
timing |= udma_bits[speed];
|
|
|
|
}
|
|
|
|
pci_write_config_word(pdev, drive_pci, timing);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sis_100_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Device to program
|
|
|
|
*
|
|
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
2009-12-07 09:41:25 -07:00
|
|
|
* Handles UDMA66 and early UDMA100 devices.
|
2006-08-29 16:12:40 -06:00
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
2011-09-07 10:23:22 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2006-08-29 16:12:40 -06:00
|
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
2007-05-21 08:00:53 -06:00
|
|
|
int drive_pci = sis_old_port_base(adev);
|
2009-12-07 09:41:25 -07:00
|
|
|
u8 timing;
|
2006-08-29 16:12:40 -06:00
|
|
|
|
2011-09-07 10:23:21 -06:00
|
|
|
static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
|
2006-08-29 16:12:40 -06:00
|
|
|
|
2009-12-07 09:41:25 -07:00
|
|
|
pci_read_config_byte(pdev, drive_pci + 1, &timing);
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
2009-12-07 09:41:25 -07:00
|
|
|
/* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
|
2006-08-29 16:12:40 -06:00
|
|
|
} else {
|
2007-05-21 08:00:53 -06:00
|
|
|
/* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
|
2006-08-29 16:12:40 -06:00
|
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
2009-12-07 09:41:25 -07:00
|
|
|
timing &= ~0x8F;
|
2006-08-29 16:12:40 -06:00
|
|
|
timing |= udma_bits[speed];
|
|
|
|
}
|
2009-12-07 09:41:25 -07:00
|
|
|
pci_write_config_byte(pdev, drive_pci + 1, timing);
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Device to program
|
|
|
|
*
|
|
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
2007-07-31 14:02:41 -06:00
|
|
|
* Handles early SiS 961 bridges.
|
2006-08-29 16:12:40 -06:00
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
2011-09-07 10:23:22 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2006-08-29 16:12:40 -06:00
|
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
2007-05-21 08:00:53 -06:00
|
|
|
int drive_pci = sis_old_port_base(adev);
|
2009-12-07 09:41:25 -07:00
|
|
|
u8 timing;
|
|
|
|
/* Low 4 bits are timing */
|
|
|
|
static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
|
2006-08-29 16:12:40 -06:00
|
|
|
|
2009-12-07 09:41:25 -07:00
|
|
|
pci_read_config_byte(pdev, drive_pci + 1, &timing);
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
2009-12-07 09:41:25 -07:00
|
|
|
/* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
|
2006-08-29 16:12:40 -06:00
|
|
|
} else {
|
2007-05-21 08:00:53 -06:00
|
|
|
/* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
|
2006-08-29 16:12:40 -06:00
|
|
|
speed = adev->dma_mode - XFER_UDMA_0;
|
2009-12-07 09:41:25 -07:00
|
|
|
timing &= ~0x8F;
|
2006-08-29 16:12:40 -06:00
|
|
|
timing |= udma_bits[speed];
|
|
|
|
}
|
2009-12-07 09:41:25 -07:00
|
|
|
pci_write_config_byte(pdev, drive_pci + 1, timing);
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sis_133_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Device to program
|
|
|
|
*
|
|
|
|
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
2011-09-07 10:23:22 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2011-09-07 10:23:18 -06:00
|
|
|
int port;
|
2006-08-29 16:12:40 -06:00
|
|
|
u32 t1;
|
|
|
|
|
2011-09-07 10:23:18 -06:00
|
|
|
port = sis_port_base(adev);
|
2006-08-29 16:12:40 -06:00
|
|
|
pci_read_config_dword(pdev, port, &t1);
|
|
|
|
|
|
|
|
if (adev->dma_mode < XFER_UDMA_0) {
|
2011-09-07 10:23:20 -06:00
|
|
|
/* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */
|
|
|
|
static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 };
|
|
|
|
static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 };
|
|
|
|
int speed = adev->dma_mode - XFER_MW_DMA_0;
|
|
|
|
|
|
|
|
t1 &= 0xC0C00FFF;
|
|
|
|
/* disable UDMA */
|
2009-12-07 09:41:25 -07:00
|
|
|
t1 &= ~0x00000004;
|
2011-09-07 10:23:20 -06:00
|
|
|
if (t1 & 0x08)
|
|
|
|
t1 |= timing_u133[speed];
|
|
|
|
else
|
|
|
|
t1 |= timing_u100[speed];
|
2006-08-29 16:12:40 -06:00
|
|
|
} else {
|
2011-09-07 10:23:20 -06:00
|
|
|
/* bits 4- cycle time 8 - cvs time */
|
|
|
|
static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
|
|
|
|
static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
|
2011-09-07 10:23:18 -06:00
|
|
|
int speed = adev->dma_mode - XFER_UDMA_0;
|
2011-09-07 10:23:20 -06:00
|
|
|
|
2006-08-29 16:12:40 -06:00
|
|
|
t1 &= ~0x00000FF0;
|
2011-09-07 10:23:20 -06:00
|
|
|
/* enable UDMA */
|
2006-08-29 16:12:40 -06:00
|
|
|
t1 |= 0x00000004;
|
|
|
|
if (t1 & 0x08)
|
|
|
|
t1 |= timing_u133[speed];
|
|
|
|
else
|
|
|
|
t1 |= timing_u100[speed];
|
|
|
|
}
|
|
|
|
pci_write_config_dword(pdev, port, t1);
|
|
|
|
}
|
|
|
|
|
2011-09-07 10:23:19 -06:00
|
|
|
/**
|
|
|
|
* sis_133_mode_filter - mode selection filter
|
|
|
|
* @adev: ATA device
|
|
|
|
*
|
|
|
|
* Block UDMA6 on devices that do not support it.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = adev->link->ap;
|
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
|
|
int port = sis_port_base(adev);
|
|
|
|
u32 t1;
|
|
|
|
|
|
|
|
pci_read_config_dword(pdev, port, &t1);
|
|
|
|
/* if ATA133 is disabled, mask it out */
|
|
|
|
if (!(t1 & 0x08))
|
|
|
|
mask &= ~(0xC0 << ATA_SHIFT_UDMA);
|
|
|
|
return mask;
|
|
|
|
}
|
|
|
|
|
2006-08-29 16:12:40 -06:00
|
|
|
static struct scsi_host_template sis_sht = {
|
2008-03-24 21:22:49 -06:00
|
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
static struct ata_port_operations sis_133_for_sata_ops = {
|
|
|
|
.inherits = &ata_bmdma_port_ops,
|
2006-08-29 16:12:40 -06:00
|
|
|
.set_piomode = sis_133_set_piomode,
|
|
|
|
.set_dmamode = sis_133_set_dmamode,
|
2007-03-07 09:54:24 -07:00
|
|
|
.cable_detect = sis_133_cable_detect,
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
};
|
2006-08-29 16:12:40 -06:00
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
static struct ata_port_operations sis_base_ops = {
|
|
|
|
.inherits = &ata_bmdma_port_ops,
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:50 -06:00
|
|
|
.prereset = sis_pre_reset,
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
static struct ata_port_operations sis_133_ops = {
|
|
|
|
.inherits = &sis_base_ops,
|
2007-06-14 15:40:43 -06:00
|
|
|
.set_piomode = sis_133_set_piomode,
|
|
|
|
.set_dmamode = sis_133_set_dmamode,
|
|
|
|
.cable_detect = sis_133_cable_detect,
|
2011-09-07 10:23:19 -06:00
|
|
|
.mode_filter = sis_133_mode_filter,
|
2007-06-14 15:40:43 -06:00
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
static struct ata_port_operations sis_133_early_ops = {
|
|
|
|
.inherits = &sis_base_ops,
|
2006-08-29 16:12:40 -06:00
|
|
|
.set_piomode = sis_100_set_piomode,
|
|
|
|
.set_dmamode = sis_133_early_set_dmamode,
|
2007-03-07 09:54:24 -07:00
|
|
|
.cable_detect = sis_66_cable_detect,
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
static struct ata_port_operations sis_100_ops = {
|
|
|
|
.inherits = &sis_base_ops,
|
2006-08-29 16:12:40 -06:00
|
|
|
.set_piomode = sis_100_set_piomode,
|
|
|
|
.set_dmamode = sis_100_set_dmamode,
|
2007-03-07 09:54:24 -07:00
|
|
|
.cable_detect = sis_66_cable_detect,
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
static struct ata_port_operations sis_66_ops = {
|
|
|
|
.inherits = &sis_base_ops,
|
2006-08-29 16:12:40 -06:00
|
|
|
.set_piomode = sis_old_set_piomode,
|
|
|
|
.set_dmamode = sis_66_set_dmamode,
|
2007-03-07 09:54:24 -07:00
|
|
|
.cable_detect = sis_66_cable_detect,
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
static struct ata_port_operations sis_old_ops = {
|
|
|
|
.inherits = &sis_base_ops,
|
2006-08-29 16:12:40 -06:00
|
|
|
.set_piomode = sis_old_set_piomode,
|
|
|
|
.set_dmamode = sis_old_set_dmamode,
|
2007-03-07 09:54:24 -07:00
|
|
|
.cable_detect = ata_cable_40wire,
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
2007-05-04 04:43:58 -06:00
|
|
|
static const struct ata_port_info sis_info = {
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
|
|
/* No UDMA */
|
2006-08-29 16:12:40 -06:00
|
|
|
.port_ops = &sis_old_ops,
|
|
|
|
};
|
2007-05-04 04:43:58 -06:00
|
|
|
static const struct ata_port_info sis_info33 = {
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
|
|
.udma_mask = ATA_UDMA2,
|
2006-08-29 16:12:40 -06:00
|
|
|
.port_ops = &sis_old_ops,
|
|
|
|
};
|
2007-05-04 04:43:58 -06:00
|
|
|
static const struct ata_port_info sis_info66 = {
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
/* No MWDMA */
|
|
|
|
.udma_mask = ATA_UDMA4,
|
2006-08-29 16:12:40 -06:00
|
|
|
.port_ops = &sis_66_ops,
|
|
|
|
};
|
2007-05-04 04:43:58 -06:00
|
|
|
static const struct ata_port_info sis_info100 = {
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
/* No MWDMA */
|
2006-08-29 16:12:40 -06:00
|
|
|
.udma_mask = ATA_UDMA5,
|
|
|
|
.port_ops = &sis_100_ops,
|
|
|
|
};
|
2007-05-04 04:43:58 -06:00
|
|
|
static const struct ata_port_info sis_info100_early = {
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
/* No MWDMA */
|
2006-08-29 16:12:40 -06:00
|
|
|
.udma_mask = ATA_UDMA5,
|
|
|
|
.port_ops = &sis_66_ops,
|
|
|
|
};
|
2007-06-14 15:40:43 -06:00
|
|
|
static const struct ata_port_info sis_info133 = {
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
2011-09-07 10:23:20 -06:00
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2006-08-29 16:12:40 -06:00
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &sis_133_ops,
|
|
|
|
};
|
2007-06-14 15:40:43 -06:00
|
|
|
const struct ata_port_info sis_info133_for_sata = {
|
2011-02-04 12:03:34 -07:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
/* No MWDMA */
|
2007-06-14 15:40:43 -06:00
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &sis_133_for_sata_ops,
|
|
|
|
};
|
2007-05-04 04:43:58 -06:00
|
|
|
static const struct ata_port_info sis_info133_early = {
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
/* No MWDMA */
|
2006-08-29 16:12:40 -06:00
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &sis_133_early_ops,
|
|
|
|
};
|
|
|
|
|
2007-01-08 09:11:07 -07:00
|
|
|
/* Privately shared with the SiS180 SATA driver, not for use elsewhere */
|
2007-06-14 15:40:43 -06:00
|
|
|
EXPORT_SYMBOL_GPL(sis_info133_for_sata);
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
|
|
|
|
{
|
|
|
|
u16 regw;
|
|
|
|
u8 reg;
|
|
|
|
|
|
|
|
if (sis->info == &sis_info133) {
|
|
|
|
pci_read_config_word(pdev, 0x50, ®w);
|
|
|
|
if (regw & 0x08)
|
|
|
|
pci_write_config_word(pdev, 0x50, regw & ~0x08);
|
|
|
|
pci_read_config_word(pdev, 0x52, ®w);
|
|
|
|
if (regw & 0x08)
|
|
|
|
pci_write_config_word(pdev, 0x52, regw & ~0x08);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
|
|
|
|
/* Fix up latency */
|
|
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
|
|
|
|
/* Set compatibility bit */
|
|
|
|
pci_read_config_byte(pdev, 0x49, ®);
|
|
|
|
if (!(reg & 0x01))
|
|
|
|
pci_write_config_byte(pdev, 0x49, reg | 0x01);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
|
|
|
|
/* Fix up latency */
|
|
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
|
|
|
|
/* Set compatibility bit */
|
|
|
|
pci_read_config_byte(pdev, 0x52, ®);
|
|
|
|
if (!(reg & 0x04))
|
|
|
|
pci_write_config_byte(pdev, 0x52, reg | 0x04);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sis->info == &sis_info33) {
|
|
|
|
pci_read_config_byte(pdev, PCI_CLASS_PROG, ®);
|
|
|
|
if (( reg & 0x0F ) != 0x00)
|
|
|
|
pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
|
|
|
|
/* Fall through to ATA16 fixup below */
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sis->info == &sis_info || sis->info == &sis_info33) {
|
|
|
|
/* force per drive recovery and active timings
|
|
|
|
needed on ATA_33 and below chips */
|
|
|
|
pci_read_config_byte(pdev, 0x52, ®);
|
|
|
|
if (!(reg & 0x08))
|
|
|
|
pci_write_config_byte(pdev, 0x52, reg|0x08);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sis_init_one - Register SiS ATA PCI device with kernel services
|
|
|
|
* @pdev: PCI device to register
|
|
|
|
* @ent: Entry in sis_pci_tbl matching with @pdev
|
|
|
|
*
|
2011-09-07 10:23:22 -06:00
|
|
|
* Called from kernel PCI layer. We probe for combined mode (sigh),
|
2006-08-29 16:12:40 -06:00
|
|
|
* and then hand over control to libata, for it to do the rest.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* Inherited from PCI layer (may sleep).
|
|
|
|
*
|
|
|
|
* RETURNS:
|
|
|
|
* Zero on success, or -ERRNO value.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
|
2008-03-24 21:22:49 -06:00
|
|
|
const struct ata_port_info *ppi[] = { NULL, NULL };
|
2006-08-29 16:12:40 -06:00
|
|
|
struct pci_dev *host = NULL;
|
|
|
|
struct sis_chipset *chipset = NULL;
|
2007-04-19 04:09:52 -06:00
|
|
|
struct sis_chipset *sets;
|
2008-03-24 21:22:47 -06:00
|
|
|
int rc;
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
static struct sis_chipset sis_chipsets[] = {
|
2006-12-11 09:14:06 -07:00
|
|
|
|
2006-09-12 10:15:12 -06:00
|
|
|
{ 0x0968, &sis_info133 },
|
|
|
|
{ 0x0966, &sis_info133 },
|
|
|
|
{ 0x0965, &sis_info133 },
|
2006-08-29 16:12:40 -06:00
|
|
|
{ 0x0745, &sis_info100 },
|
|
|
|
{ 0x0735, &sis_info100 },
|
|
|
|
{ 0x0733, &sis_info100 },
|
|
|
|
{ 0x0635, &sis_info100 },
|
|
|
|
{ 0x0633, &sis_info100 },
|
|
|
|
|
|
|
|
{ 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
|
|
|
|
{ 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
|
|
|
|
|
|
|
|
{ 0x0640, &sis_info66 },
|
|
|
|
{ 0x0630, &sis_info66 },
|
|
|
|
{ 0x0620, &sis_info66 },
|
|
|
|
{ 0x0540, &sis_info66 },
|
|
|
|
{ 0x0530, &sis_info66 },
|
|
|
|
|
|
|
|
{ 0x5600, &sis_info33 },
|
|
|
|
{ 0x5598, &sis_info33 },
|
|
|
|
{ 0x5597, &sis_info33 },
|
|
|
|
{ 0x5591, &sis_info33 },
|
|
|
|
{ 0x5582, &sis_info33 },
|
|
|
|
{ 0x5581, &sis_info33 },
|
|
|
|
|
|
|
|
{ 0x5596, &sis_info },
|
|
|
|
{ 0x5571, &sis_info },
|
|
|
|
{ 0x5517, &sis_info },
|
|
|
|
{ 0x5511, &sis_info },
|
|
|
|
|
|
|
|
{0}
|
|
|
|
};
|
|
|
|
static struct sis_chipset sis133_early = {
|
|
|
|
0x0, &sis_info133_early
|
|
|
|
};
|
|
|
|
static struct sis_chipset sis133 = {
|
|
|
|
0x0, &sis_info133
|
|
|
|
};
|
|
|
|
static struct sis_chipset sis100_early = {
|
|
|
|
0x0, &sis_info100_early
|
|
|
|
};
|
|
|
|
static struct sis_chipset sis100 = {
|
|
|
|
0x0, &sis_info100
|
|
|
|
};
|
|
|
|
|
2011-04-15 16:52:00 -06:00
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
2006-08-29 16:12:40 -06:00
|
|
|
|
2008-03-24 21:22:47 -06:00
|
|
|
rc = pcim_enable_device(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2006-08-29 16:12:40 -06:00
|
|
|
|
2008-03-24 21:22:47 -06:00
|
|
|
/* We have to find the bridge first */
|
2007-04-19 04:09:52 -06:00
|
|
|
for (sets = &sis_chipsets[0]; sets->device; sets++) {
|
|
|
|
host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
|
2006-08-29 16:12:40 -06:00
|
|
|
if (host != NULL) {
|
2007-04-19 04:09:52 -06:00
|
|
|
chipset = sets; /* Match found */
|
|
|
|
if (sets->device == 0x630) { /* SIS630 */
|
2007-06-08 16:46:36 -06:00
|
|
|
if (host->revision >= 0x30) /* 630 ET */
|
2006-08-29 16:12:40 -06:00
|
|
|
chipset = &sis100_early;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Look for concealed bridges */
|
2007-04-19 04:09:52 -06:00
|
|
|
if (chipset == NULL) {
|
2006-08-29 16:12:40 -06:00
|
|
|
/* Second check */
|
|
|
|
u32 idemisc;
|
|
|
|
u16 trueid;
|
|
|
|
|
|
|
|
/* Disable ID masking and register remapping then
|
|
|
|
see what the real ID is */
|
|
|
|
|
|
|
|
pci_read_config_dword(pdev, 0x54, &idemisc);
|
|
|
|
pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
|
|
|
|
pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
|
|
|
|
pci_write_config_dword(pdev, 0x54, idemisc);
|
|
|
|
|
|
|
|
switch(trueid) {
|
|
|
|
case 0x5518: /* SIS 962/963 */
|
2011-09-07 10:23:19 -06:00
|
|
|
dev_info(&pdev->dev,
|
|
|
|
"SiS 962/963 MuTIOL IDE UDMA133 controller\n");
|
2006-08-29 16:12:40 -06:00
|
|
|
chipset = &sis133;
|
|
|
|
if ((idemisc & 0x40000000) == 0) {
|
|
|
|
pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
|
2011-09-07 10:23:19 -06:00
|
|
|
dev_info(&pdev->dev,
|
|
|
|
"Switching to 5513 register mapping\n");
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x0180: /* SIS 965/965L */
|
2011-09-07 10:23:22 -06:00
|
|
|
chipset = &sis133;
|
2006-08-29 16:12:40 -06:00
|
|
|
break;
|
|
|
|
case 0x1180: /* SIS 966/966L */
|
2011-09-07 10:23:22 -06:00
|
|
|
chipset = &sis133;
|
2006-08-29 16:12:40 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Further check */
|
|
|
|
if (chipset == NULL) {
|
|
|
|
struct pci_dev *lpc_bridge;
|
|
|
|
u16 trueid;
|
|
|
|
u8 prefctl;
|
|
|
|
u8 idecfg;
|
|
|
|
|
|
|
|
/* Try the second unmasking technique */
|
|
|
|
pci_read_config_byte(pdev, 0x4a, &idecfg);
|
|
|
|
pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
|
|
|
|
pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
|
|
|
|
pci_write_config_byte(pdev, 0x4a, idecfg);
|
|
|
|
|
|
|
|
switch(trueid) {
|
|
|
|
case 0x5517:
|
|
|
|
lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
|
|
|
|
if (lpc_bridge == NULL)
|
|
|
|
break;
|
|
|
|
pci_read_config_byte(pdev, 0x49, &prefctl);
|
|
|
|
pci_dev_put(lpc_bridge);
|
|
|
|
|
2007-06-08 16:46:36 -06:00
|
|
|
if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
|
2006-08-29 16:12:40 -06:00
|
|
|
chipset = &sis133_early;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
chipset = &sis100;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
pci_dev_put(host);
|
|
|
|
|
|
|
|
/* No chipset info, no support */
|
|
|
|
if (chipset == NULL)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2008-03-24 21:22:49 -06:00
|
|
|
ppi[0] = chipset->info;
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
sis_fixup(pdev, chipset);
|
|
|
|
|
2010-05-19 14:10:22 -06:00
|
|
|
return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0);
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
|
2009-12-03 12:32:13 -07:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int sis_reinit_one(struct pci_dev *pdev)
|
|
|
|
{
|
2013-06-02 23:05:36 -06:00
|
|
|
struct ata_host *host = pci_get_drvdata(pdev);
|
2009-12-03 12:32:13 -07:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
sis_fixup(pdev, host->private_data);
|
|
|
|
|
|
|
|
ata_host_resume(host);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2006-08-29 16:12:40 -06:00
|
|
|
static const struct pci_device_id sis_pci_tbl[] = {
|
2006-09-28 18:21:59 -06:00
|
|
|
{ PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
|
|
|
|
{ PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
|
2007-06-14 15:40:43 -06:00
|
|
|
{ PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
|
2006-09-28 18:21:59 -06:00
|
|
|
|
2006-08-29 16:12:40 -06:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver sis_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = sis_pci_tbl,
|
|
|
|
.probe = sis_init_one,
|
|
|
|
.remove = ata_pci_remove_one,
|
2007-03-02 01:31:26 -07:00
|
|
|
#ifdef CONFIG_PM
|
2006-11-27 09:27:20 -07:00
|
|
|
.suspend = ata_pci_device_suspend,
|
2009-12-03 12:32:13 -07:00
|
|
|
.resume = sis_reinit_one,
|
2007-03-02 01:31:26 -07:00
|
|
|
#endif
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
2012-04-18 23:43:05 -06:00
|
|
|
module_pci_driver(sis_pci_driver);
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
|
|
MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|