2014-08-27 18:04:56 -06:00
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/*
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* Broadcom Starfighter 2 DSA switch driver
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*
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* Copyright (C) 2014, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/phy_fixed.h>
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#include <linux/mii.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <net/dsa.h>
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#include "bcm_sf2.h"
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#include "bcm_sf2_regs.h"
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/* String, offset, and register size in bytes if different from 4 bytes */
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static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
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{ "TxOctets", 0x000, 8 },
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{ "TxDropPkts", 0x020 },
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{ "TxQPKTQ0", 0x030 },
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{ "TxBroadcastPkts", 0x040 },
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{ "TxMulticastPkts", 0x050 },
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{ "TxUnicastPKts", 0x060 },
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{ "TxCollisions", 0x070 },
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{ "TxSingleCollision", 0x080 },
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{ "TxMultipleCollision", 0x090 },
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{ "TxDeferredCollision", 0x0a0 },
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{ "TxLateCollision", 0x0b0 },
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{ "TxExcessiveCollision", 0x0c0 },
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{ "TxFrameInDisc", 0x0d0 },
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{ "TxPausePkts", 0x0e0 },
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{ "TxQPKTQ1", 0x0f0 },
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{ "TxQPKTQ2", 0x100 },
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{ "TxQPKTQ3", 0x110 },
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{ "TxQPKTQ4", 0x120 },
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{ "TxQPKTQ5", 0x130 },
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{ "RxOctets", 0x140, 8 },
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{ "RxUndersizePkts", 0x160 },
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{ "RxPausePkts", 0x170 },
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{ "RxPkts64Octets", 0x180 },
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{ "RxPkts65to127Octets", 0x190 },
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{ "RxPkts128to255Octets", 0x1a0 },
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{ "RxPkts256to511Octets", 0x1b0 },
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{ "RxPkts512to1023Octets", 0x1c0 },
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{ "RxPkts1024toMaxPktsOctets", 0x1d0 },
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{ "RxOversizePkts", 0x1e0 },
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{ "RxJabbers", 0x1f0 },
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{ "RxAlignmentErrors", 0x200 },
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{ "RxFCSErrors", 0x210 },
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{ "RxGoodOctets", 0x220, 8 },
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{ "RxDropPkts", 0x240 },
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{ "RxUnicastPkts", 0x250 },
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{ "RxMulticastPkts", 0x260 },
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{ "RxBroadcastPkts", 0x270 },
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{ "RxSAChanges", 0x280 },
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{ "RxFragments", 0x290 },
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{ "RxJumboPkt", 0x2a0 },
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{ "RxSymblErr", 0x2b0 },
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{ "InRangeErrCount", 0x2c0 },
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{ "OutRangeErrCount", 0x2d0 },
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{ "EEELpiEvent", 0x2e0 },
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{ "EEELpiDuration", 0x2f0 },
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{ "RxDiscard", 0x300, 8 },
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{ "TxQPKTQ6", 0x320 },
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{ "TxQPKTQ7", 0x330 },
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{ "TxPkts64Octets", 0x340 },
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{ "TxPkts65to127Octets", 0x350 },
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{ "TxPkts128to255Octets", 0x360 },
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{ "TxPkts256to511Ocets", 0x370 },
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{ "TxPkts512to1023Ocets", 0x380 },
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{ "TxPkts1024toMaxPktOcets", 0x390 },
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};
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#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
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static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
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int port, uint8_t *data)
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{
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unsigned int i;
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for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
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memcpy(data + i * ETH_GSTRING_LEN,
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bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
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}
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static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
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int port, uint64_t *data)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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const struct bcm_sf2_hw_stats *s;
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unsigned int i;
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u64 val = 0;
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u32 offset;
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mutex_lock(&priv->stats_mutex);
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/* Now fetch the per-port counters */
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for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
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s = &bcm_sf2_mib[i];
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/* Do a latched 64-bit read if needed */
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offset = s->reg + CORE_P_MIB_OFFSET(port);
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if (s->sizeof_stat == 8)
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val = core_readq(priv, offset);
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else
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val = core_readl(priv, offset);
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data[i] = (u64)val;
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}
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mutex_unlock(&priv->stats_mutex);
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}
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static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
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{
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return BCM_SF2_STATS_SIZE;
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}
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2014-09-15 11:00:27 -06:00
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static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
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2014-08-27 18:04:56 -06:00
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{
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return "Broadcom Starfighter 2";
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}
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static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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unsigned int i;
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u32 reg, val;
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/* Enable the port memories */
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reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
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reg &= ~P_TXQ_PSM_VDD(port);
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core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
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/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
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reg = core_readl(priv, CORE_IMP_CTL);
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reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
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reg &= ~(RX_DIS | TX_DIS);
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core_writel(priv, reg, CORE_IMP_CTL);
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/* Enable forwarding */
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core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
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/* Enable IMP port in dumb mode */
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reg = core_readl(priv, CORE_SWITCH_CTRL);
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reg |= MII_DUMB_FWDG_EN;
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core_writel(priv, reg, CORE_SWITCH_CTRL);
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/* Resolve which bit controls the Broadcom tag */
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switch (port) {
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case 8:
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val = BRCM_HDR_EN_P8;
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break;
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case 7:
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val = BRCM_HDR_EN_P7;
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break;
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case 5:
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val = BRCM_HDR_EN_P5;
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break;
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default:
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val = 0;
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break;
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}
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/* Enable Broadcom tags for IMP port */
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reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
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reg |= val;
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core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
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/* Enable reception Broadcom tag for CPU TX (switch RX) to
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* allow us to tag outgoing frames
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*/
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reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
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reg &= ~(1 << port);
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core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
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/* Enable transmission of Broadcom tags from the switch (CPU RX) to
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* allow delivering frames to the per-port net_devices
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*/
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reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
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reg &= ~(1 << port);
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core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
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/* Force link status for IMP port */
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reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
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reg |= (MII_SW_OR | LINK_STS);
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core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
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/* Enable the IMP Port to be in the same VLAN as the other ports
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* on a per-port basis such that we only have Port i and IMP in
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* the same VLAN.
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*/
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for (i = 0; i < priv->hw_params.num_ports; i++) {
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if (!((1 << i) & ds->phys_port_mask))
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continue;
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reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
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reg |= (1 << port);
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core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
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}
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}
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static void bcm_sf2_port_setup(struct dsa_switch *ds, int port)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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u32 reg;
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/* Clear the memory power down */
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reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
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reg &= ~P_TXQ_PSM_VDD(port);
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core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
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/* Clear the Rx and Tx disable bits and set to no spanning tree */
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core_writel(priv, 0, CORE_G_PCTL_PORT(port));
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/* Enable port 7 interrupts to get notified */
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if (port == 7)
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intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
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/* Set this port, and only this one to be in the default VLAN */
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reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
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reg &= ~PORT_VLAN_CTRL_MASK;
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reg |= (1 << port);
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core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
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}
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static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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u32 off, reg;
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if (dsa_is_cpu_port(ds, port))
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off = CORE_IMP_CTL;
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else
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off = CORE_G_PCTL_PORT(port);
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reg = core_readl(priv, off);
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reg |= RX_DIS | TX_DIS;
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core_writel(priv, reg, off);
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/* Power down the port memory */
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reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
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reg |= P_TXQ_PSM_VDD(port);
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core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
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}
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static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
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{
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struct bcm_sf2_priv *priv = dev_id;
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priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
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~priv->irq0_mask;
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intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
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return IRQ_HANDLED;
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}
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static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
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{
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struct bcm_sf2_priv *priv = dev_id;
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priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
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~priv->irq1_mask;
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intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
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if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
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priv->port_sts[7].link = 1;
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if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
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priv->port_sts[7].link = 0;
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return IRQ_HANDLED;
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}
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static int bcm_sf2_sw_setup(struct dsa_switch *ds)
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{
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const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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struct device_node *dn;
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void __iomem **base;
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unsigned int port;
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unsigned int i;
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u32 reg, rev;
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int ret;
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spin_lock_init(&priv->indir_lock);
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mutex_init(&priv->stats_mutex);
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/* All the interesting properties are at the parent device_node
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* level
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*/
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dn = ds->pd->of_node->parent;
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priv->irq0 = irq_of_parse_and_map(dn, 0);
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priv->irq1 = irq_of_parse_and_map(dn, 1);
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base = &priv->core;
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for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
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*base = of_iomap(dn, i);
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if (*base == NULL) {
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pr_err("unable to find register: %s\n", reg_names[i]);
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return -ENODEV;
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}
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base++;
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}
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/* Disable all interrupts and request them */
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intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
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intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
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intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
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intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
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intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
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intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
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ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
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"switch_0", priv);
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if (ret < 0) {
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pr_err("failed to request switch_0 IRQ\n");
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goto out_unmap;
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}
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ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
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"switch_1", priv);
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if (ret < 0) {
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pr_err("failed to request switch_1 IRQ\n");
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|
|
goto out_free_irq0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reset the MIB counters */
|
|
|
|
reg = core_readl(priv, CORE_GMNCFGCFG);
|
|
|
|
reg |= RST_MIB_CNT;
|
|
|
|
core_writel(priv, reg, CORE_GMNCFGCFG);
|
|
|
|
reg &= ~RST_MIB_CNT;
|
|
|
|
core_writel(priv, reg, CORE_GMNCFGCFG);
|
|
|
|
|
|
|
|
/* Get the maximum number of ports for this switch */
|
|
|
|
priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
|
|
|
|
if (priv->hw_params.num_ports > DSA_MAX_PORTS)
|
|
|
|
priv->hw_params.num_ports = DSA_MAX_PORTS;
|
|
|
|
|
|
|
|
/* Assume a single GPHY setup if we can't read that property */
|
|
|
|
if (of_property_read_u32(dn, "brcm,num-gphy",
|
|
|
|
&priv->hw_params.num_gphy))
|
|
|
|
priv->hw_params.num_gphy = 1;
|
|
|
|
|
|
|
|
/* Enable all valid ports and disable those unused */
|
|
|
|
for (port = 0; port < priv->hw_params.num_ports; port++) {
|
|
|
|
/* IMP port receives special treatment */
|
|
|
|
if ((1 << port) & ds->phys_port_mask)
|
|
|
|
bcm_sf2_port_setup(ds, port);
|
|
|
|
else if (dsa_is_cpu_port(ds, port))
|
|
|
|
bcm_sf2_imp_setup(ds, port);
|
|
|
|
else
|
|
|
|
bcm_sf2_port_disable(ds, port);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Include the pseudo-PHY address and the broadcast PHY address to
|
|
|
|
* divert reads towards our workaround
|
|
|
|
*/
|
|
|
|
ds->phys_mii_mask |= ((1 << 30) | (1 << 0));
|
|
|
|
|
|
|
|
rev = reg_readl(priv, REG_SWITCH_REVISION);
|
|
|
|
priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
|
|
|
|
SWITCH_TOP_REV_MASK;
|
|
|
|
priv->hw_params.core_rev = (rev & SF2_REV_MASK);
|
|
|
|
|
2014-09-19 14:07:55 -06:00
|
|
|
rev = reg_readl(priv, REG_PHY_REVISION);
|
|
|
|
priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
|
|
|
|
|
2014-08-27 18:04:56 -06:00
|
|
|
pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
|
|
|
|
priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
|
|
|
|
priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
|
|
|
|
priv->core, priv->irq0, priv->irq1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_free_irq0:
|
|
|
|
free_irq(priv->irq0, priv);
|
|
|
|
out_unmap:
|
|
|
|
base = &priv->core;
|
|
|
|
for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
|
|
|
|
iounmap(*base);
|
|
|
|
base++;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-19 14:07:55 -06:00
|
|
|
static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
|
|
|
|
{
|
|
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
|
|
|
|
/* The BCM7xxx PHY driver expects to find the integrated PHY revision
|
|
|
|
* in bits 15:8 and the patch level in bits 7:0 which is exactly what
|
|
|
|
* the REG_PHY_REVISION register layout is.
|
|
|
|
*/
|
|
|
|
|
|
|
|
return priv->hw_params.gphy_rev;
|
|
|
|
}
|
|
|
|
|
2014-08-27 18:04:56 -06:00
|
|
|
static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
|
|
|
|
int regnum, u16 val)
|
|
|
|
{
|
|
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
int ret = 0;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = reg_readl(priv, REG_SWITCH_CNTRL);
|
|
|
|
reg |= MDIO_MASTER_SEL;
|
|
|
|
reg_writel(priv, reg, REG_SWITCH_CNTRL);
|
|
|
|
|
|
|
|
/* Page << 8 | offset */
|
|
|
|
reg = 0x70;
|
|
|
|
reg <<= 2;
|
|
|
|
core_writel(priv, addr, reg);
|
|
|
|
|
|
|
|
/* Page << 8 | offset */
|
|
|
|
reg = 0x80 << 8 | regnum << 1;
|
|
|
|
reg <<= 2;
|
|
|
|
|
|
|
|
if (op)
|
|
|
|
ret = core_readl(priv, reg);
|
|
|
|
else
|
|
|
|
core_writel(priv, val, reg);
|
|
|
|
|
|
|
|
reg = reg_readl(priv, REG_SWITCH_CNTRL);
|
|
|
|
reg &= ~MDIO_MASTER_SEL;
|
|
|
|
reg_writel(priv, reg, REG_SWITCH_CNTRL);
|
|
|
|
|
|
|
|
return ret & 0xffff;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
|
|
|
|
{
|
|
|
|
/* Intercept reads from the MDIO broadcast address or Broadcom
|
|
|
|
* pseudo-PHY address
|
|
|
|
*/
|
|
|
|
switch (addr) {
|
|
|
|
case 0:
|
|
|
|
case 30:
|
|
|
|
return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
|
|
|
|
default:
|
|
|
|
return 0xffff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
|
|
|
|
u16 val)
|
|
|
|
{
|
|
|
|
/* Intercept writes to the MDIO broadcast address or Broadcom
|
|
|
|
* pseudo-PHY address
|
|
|
|
*/
|
|
|
|
switch (addr) {
|
|
|
|
case 0:
|
|
|
|
case 30:
|
|
|
|
bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
|
|
|
|
struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
u32 id_mode_dis = 0, port_mode;
|
|
|
|
const char *str = NULL;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
switch (phydev->interface) {
|
|
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
|
|
str = "RGMII (no delay)";
|
|
|
|
id_mode_dis = 1;
|
|
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
|
|
if (!str)
|
|
|
|
str = "RGMII (TX delay)";
|
|
|
|
port_mode = EXT_GPHY;
|
|
|
|
break;
|
|
|
|
case PHY_INTERFACE_MODE_MII:
|
|
|
|
str = "MII";
|
|
|
|
port_mode = EXT_EPHY;
|
|
|
|
break;
|
|
|
|
case PHY_INTERFACE_MODE_REVMII:
|
|
|
|
str = "Reverse MII";
|
|
|
|
port_mode = EXT_REVMII;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
goto force_link;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clear id_mode_dis bit, and the existing port mode, but
|
|
|
|
* make sure we enable the RGMII block for data to pass
|
|
|
|
*/
|
|
|
|
reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
|
|
|
|
reg &= ~ID_MODE_DIS;
|
|
|
|
reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
|
|
|
|
reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
|
|
|
|
|
|
|
|
reg |= port_mode | RGMII_MODE_EN;
|
|
|
|
if (id_mode_dis)
|
|
|
|
reg |= ID_MODE_DIS;
|
|
|
|
|
|
|
|
if (phydev->pause) {
|
|
|
|
if (phydev->asym_pause)
|
|
|
|
reg |= TX_PAUSE_EN;
|
|
|
|
reg |= RX_PAUSE_EN;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
|
|
|
|
|
|
|
|
pr_info("Port %d configured for %s\n", port, str);
|
|
|
|
|
|
|
|
force_link:
|
|
|
|
/* Force link settings detected from the PHY */
|
|
|
|
reg = SW_OVERRIDE;
|
|
|
|
switch (phydev->speed) {
|
|
|
|
case SPEED_1000:
|
|
|
|
reg |= SPDSTS_1000 << SPEED_SHIFT;
|
|
|
|
break;
|
|
|
|
case SPEED_100:
|
|
|
|
reg |= SPDSTS_100 << SPEED_SHIFT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (phydev->link)
|
|
|
|
reg |= LINK_STS;
|
|
|
|
if (phydev->duplex == DUPLEX_FULL)
|
|
|
|
reg |= DUPLX_MODE;
|
|
|
|
|
|
|
|
core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
|
|
|
|
struct fixed_phy_status *status)
|
|
|
|
{
|
|
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
u32 link, duplex, pause, speed;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
link = core_readl(priv, CORE_LNKSTS);
|
|
|
|
duplex = core_readl(priv, CORE_DUPSTS);
|
|
|
|
pause = core_readl(priv, CORE_PAUSESTS);
|
|
|
|
speed = core_readl(priv, CORE_SPDSTS);
|
|
|
|
|
|
|
|
speed >>= (port * SPDSTS_SHIFT);
|
|
|
|
speed &= SPDSTS_MASK;
|
|
|
|
|
|
|
|
status->link = 0;
|
|
|
|
|
|
|
|
/* Port 7 is special as we do not get link status from CORE_LNKSTS,
|
|
|
|
* which means that we need to force the link at the port override
|
|
|
|
* level to get the data to flow. We do use what the interrupt handler
|
|
|
|
* did determine before.
|
|
|
|
*/
|
|
|
|
if (port == 7) {
|
|
|
|
status->link = priv->port_sts[port].link;
|
|
|
|
reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(7));
|
|
|
|
reg |= SW_OVERRIDE;
|
|
|
|
if (status->link)
|
|
|
|
reg |= LINK_STS;
|
|
|
|
else
|
|
|
|
reg &= ~LINK_STS;
|
|
|
|
core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(7));
|
|
|
|
status->duplex = 1;
|
|
|
|
} else {
|
|
|
|
status->link = !!(link & (1 << port));
|
|
|
|
status->duplex = !!(duplex & (1 << port));
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (speed) {
|
|
|
|
case SPDSTS_10:
|
|
|
|
status->speed = SPEED_10;
|
|
|
|
break;
|
|
|
|
case SPDSTS_100:
|
|
|
|
status->speed = SPEED_100;
|
|
|
|
break;
|
|
|
|
case SPDSTS_1000:
|
|
|
|
status->speed = SPEED_1000;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((pause & (1 << port)) &&
|
|
|
|
(pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
|
|
|
|
status->asym_pause = 1;
|
|
|
|
status->pause = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pause & (1 << port))
|
|
|
|
status->pause = 1;
|
|
|
|
}
|
|
|
|
|
2014-09-18 18:31:23 -06:00
|
|
|
static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
unsigned int port;
|
|
|
|
|
|
|
|
intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
|
|
|
|
intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
|
|
|
|
intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
|
|
|
|
intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
|
|
|
|
intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
|
|
|
|
intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
|
|
|
|
|
|
|
|
/* Disable all ports physically present including the IMP
|
|
|
|
* port, the other ones have already been disabled during
|
|
|
|
* bcm_sf2_sw_setup
|
|
|
|
*/
|
|
|
|
for (port = 0; port < DSA_MAX_PORTS; port++) {
|
|
|
|
if ((1 << port) & ds->phys_port_mask ||
|
|
|
|
dsa_is_cpu_port(ds, port))
|
|
|
|
bcm_sf2_port_disable(ds, port);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
|
|
|
|
{
|
|
|
|
unsigned int timeout = 1000;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = core_readl(priv, CORE_WATCHDOG_CTRL);
|
|
|
|
reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
|
|
|
|
core_writel(priv, reg, CORE_WATCHDOG_CTRL);
|
|
|
|
|
|
|
|
do {
|
|
|
|
reg = core_readl(priv, CORE_WATCHDOG_CTRL);
|
|
|
|
if (!(reg & SOFTWARE_RESET))
|
|
|
|
break;
|
|
|
|
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
} while (timeout-- > 0);
|
|
|
|
|
|
|
|
if (timeout == 0)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm_sf2_sw_resume(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
unsigned int port;
|
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = bcm_sf2_sw_rst(priv);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("%s: failed to software reset switch\n", __func__);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reinitialize the single GPHY */
|
|
|
|
if (priv->hw_params.num_gphy == 1) {
|
|
|
|
reg = reg_readl(priv, REG_SPHY_CNTRL);
|
|
|
|
reg |= PHY_RESET;
|
|
|
|
reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS);
|
|
|
|
reg_writel(priv, reg, REG_SPHY_CNTRL);
|
|
|
|
udelay(21);
|
|
|
|
reg = reg_readl(priv, REG_SPHY_CNTRL);
|
|
|
|
reg &= ~PHY_RESET;
|
|
|
|
reg_writel(priv, reg, REG_SPHY_CNTRL);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (port = 0; port < DSA_MAX_PORTS; port++) {
|
|
|
|
if ((1 << port) & ds->phys_port_mask)
|
|
|
|
bcm_sf2_port_setup(ds, port);
|
|
|
|
else if (dsa_is_cpu_port(ds, port))
|
|
|
|
bcm_sf2_imp_setup(ds, port);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-08-27 18:04:56 -06:00
|
|
|
static struct dsa_switch_driver bcm_sf2_switch_driver = {
|
2014-09-11 22:18:09 -06:00
|
|
|
.tag_protocol = DSA_TAG_PROTO_BRCM,
|
2014-08-27 18:04:56 -06:00
|
|
|
.priv_size = sizeof(struct bcm_sf2_priv),
|
|
|
|
.probe = bcm_sf2_sw_probe,
|
|
|
|
.setup = bcm_sf2_sw_setup,
|
|
|
|
.set_addr = bcm_sf2_sw_set_addr,
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2014-09-19 14:07:55 -06:00
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.get_phy_flags = bcm_sf2_sw_get_phy_flags,
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2014-08-27 18:04:56 -06:00
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.phy_read = bcm_sf2_sw_phy_read,
|
|
|
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.phy_write = bcm_sf2_sw_phy_write,
|
|
|
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.get_strings = bcm_sf2_sw_get_strings,
|
|
|
|
.get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
|
|
|
|
.get_sset_count = bcm_sf2_sw_get_sset_count,
|
|
|
|
.adjust_link = bcm_sf2_sw_adjust_link,
|
|
|
|
.fixed_link_update = bcm_sf2_sw_fixed_link_update,
|
2014-09-18 18:31:23 -06:00
|
|
|
.suspend = bcm_sf2_sw_suspend,
|
|
|
|
.resume = bcm_sf2_sw_resume,
|
2014-08-27 18:04:56 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init bcm_sf2_init(void)
|
|
|
|
{
|
|
|
|
register_switch_driver(&bcm_sf2_switch_driver);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
module_init(bcm_sf2_init);
|
|
|
|
|
|
|
|
static void __exit bcm_sf2_exit(void)
|
|
|
|
{
|
|
|
|
unregister_switch_driver(&bcm_sf2_switch_driver);
|
|
|
|
}
|
|
|
|
module_exit(bcm_sf2_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Broadcom Corporation");
|
|
|
|
MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_ALIAS("platform:brcm-sf2");
|