License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 08:07:57 -06:00
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// SPDX-License-Identifier: GPL-2.0
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2015-02-17 11:52:05 -07:00
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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2013-07-29 06:31:51 -06:00
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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2012-08-15 11:07:34 -06:00
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/ {
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2019-01-09 09:26:14 -07:00
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#address-cells = <1>;
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#size-cells = <1>;
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2012-08-15 11:07:34 -06:00
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compatible = "marvell,dove";
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model = "Marvell Armada 88AP510 SoC";
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2013-07-29 06:31:53 -06:00
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interrupt-parent = <&intc>;
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2012-08-15 11:07:34 -06:00
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2012-11-19 02:39:55 -07:00
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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2013-07-29 06:29:03 -06:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "marvell,pj4a", "marvell,sheeva-v7";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <0>;
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};
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};
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l2: l2-cache {
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compatible = "marvell,tauros2-cache";
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marvell,tauros2-cache-features = <0>;
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};
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2015-12-15 09:38:02 -07:00
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gpu-subsystem {
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compatible = "marvell,dove-gpu-subsystem";
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cores = <&gpu>;
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status = "disabled";
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};
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2015-05-04 14:08:47 -06:00
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i2c-mux {
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compatible = "i2c-mux-pinctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c>;
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pinctrl-names = "i2c0", "i2c1", "i2c2";
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pinctrl-0 = <&pmx_i2cmux_0>;
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pinctrl-1 = <&pmx_i2cmux_1>;
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pinctrl-2 = <&pmx_i2cmux_2>;
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i2c0: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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};
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i2c1: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Requires pmx_i2c1 on i2c controller node */
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status = "disabled";
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};
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i2c2: i2c@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Requires pmx_i2c2 on i2c controller node */
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status = "disabled";
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};
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};
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2013-07-29 06:31:52 -06:00
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mbus {
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compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
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pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
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MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
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MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
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MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
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MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
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2013-07-02 05:00:18 -06:00
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2017-07-26 15:09:37 -06:00
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pcie: pcie {
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2013-08-12 12:46:53 -06:00
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compatible = "marvell,dove-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&intc>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
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0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
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0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
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0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
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0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
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0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
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2017-07-26 15:09:37 -06:00
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pcie0: pcie@1 {
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2013-08-12 12:46:53 -06:00
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device_type = "pci";
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status = "disabled";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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clocks = <&gate_clk 4>;
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marvell,pcie-port = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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2017-07-26 15:09:37 -06:00
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bus-range = <0x00 0xff>;
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2013-08-12 12:46:53 -06:00
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc 16>;
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};
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2017-07-26 15:09:37 -06:00
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pcie1: pcie@2 {
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2013-08-12 12:46:53 -06:00
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device_type = "pci";
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status = "disabled";
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assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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clocks = <&gate_clk 5>;
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marvell,pcie-port = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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2017-07-26 15:09:37 -06:00
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bus-range = <0x00 0xff>;
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2013-08-12 12:46:53 -06:00
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc 18>;
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};
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};
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2013-07-29 06:31:53 -06:00
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internal-regs {
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compatible = "simple-bus";
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2013-07-02 05:00:18 -06:00
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#address-cells = <1>;
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2013-07-29 06:31:53 -06:00
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#size-cells = <1>;
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ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
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0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
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0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
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0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
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2018-09-13 12:12:31 -06:00
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spi0: spi@10600 {
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2013-12-11 13:29:13 -07:00
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <6>;
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reg = <0x10600 0x28>;
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2013-07-29 06:31:53 -06:00
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clocks = <&core_clk 0>;
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2013-12-11 13:29:13 -07:00
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pinctrl-0 = <&pmx_spi0>;
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pinctrl-names = "default";
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status = "disabled";
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2013-07-29 06:31:53 -06:00
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};
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2018-09-13 12:12:31 -06:00
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i2c: i2c@11000 {
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2013-12-11 13:29:13 -07:00
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <11>;
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clock-frequency = <400000>;
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timeout-ms = <1000>;
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2013-07-29 06:31:53 -06:00
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clocks = <&core_clk 0>;
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2015-05-04 14:08:47 -06:00
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status = "okay";
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2013-07-29 06:31:53 -06:00
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};
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uart0: serial@12000 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <7>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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uart1: serial@12100 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <8>;
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clocks = <&core_clk 0>;
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pinctrl-0 = <&pmx_uart1>;
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pinctrl-names = "default";
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status = "disabled";
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};
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uart2: serial@12200 {
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compatible = "ns16550a";
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2015-02-17 11:52:04 -07:00
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reg = <0x12200 0x100>;
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2013-07-29 06:31:53 -06:00
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reg-shift = <2>;
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interrupts = <9>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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uart3: serial@12300 {
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compatible = "ns16550a";
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2015-02-17 11:52:04 -07:00
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reg = <0x12300 0x100>;
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2013-07-29 06:31:53 -06:00
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reg-shift = <2>;
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interrupts = <10>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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2018-09-13 12:12:31 -06:00
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spi1: spi@14600 {
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2013-12-11 13:29:13 -07:00
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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|
|
interrupts = <5>;
|
|
|
|
|
reg = <0x14600 0x28>;
|
|
|
|
|
clocks = <&core_clk 0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mbusc: mbus-ctrl@20000 {
|
|
|
|
|
compatible = "marvell,mbus-controller";
|
|
|
|
|
reg = <0x20000 0x80>, <0x800100 0x8>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-27 14:28:02 -07:00
|
|
|
sysc: system-ctrl@20000 {
|
|
|
|
|
compatible = "marvell,orion-system-controller";
|
|
|
|
|
reg = <0x20000 0x110>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-11 13:29:13 -07:00
|
|
|
bridge_intc: bridge-interrupt-ctrl@20110 {
|
|
|
|
|
compatible = "marvell,orion-bridge-intc";
|
2013-07-29 06:31:53 -06:00
|
|
|
interrupt-controller;
|
2013-12-11 13:29:13 -07:00
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
reg = <0x20110 0x8>;
|
|
|
|
|
interrupts = <0>;
|
|
|
|
|
marvell,#interrupts = <5>;
|
2013-07-29 06:31:53 -06:00
|
|
|
};
|
|
|
|
|
|
2013-12-11 13:29:13 -07:00
|
|
|
intc: main-interrupt-ctrl@20200 {
|
|
|
|
|
compatible = "marvell,orion-intc";
|
2013-07-29 06:31:53 -06:00
|
|
|
interrupt-controller;
|
2013-12-11 13:29:13 -07:00
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
reg = <0x20200 0x10>, <0x20210 0x10>;
|
2013-07-29 06:31:53 -06:00
|
|
|
};
|
|
|
|
|
|
2013-12-11 13:29:13 -07:00
|
|
|
timer: timer@20300 {
|
|
|
|
|
compatible = "marvell,orion-timer";
|
|
|
|
|
reg = <0x20300 0x20>;
|
|
|
|
|
interrupt-parent = <&bridge_intc>;
|
|
|
|
|
interrupts = <1>, <2>;
|
|
|
|
|
clocks = <&core_clk 0>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-10 16:00:34 -07:00
|
|
|
watchdog@20300 {
|
|
|
|
|
compatible = "marvell,orion-wdt";
|
|
|
|
|
reg = <0x20300 0x28>, <0x20108 0x4>;
|
|
|
|
|
interrupt-parent = <&bridge_intc>;
|
|
|
|
|
interrupts = <3>;
|
|
|
|
|
clocks = <&core_clk 0>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-11 13:29:13 -07:00
|
|
|
crypto: crypto-engine@30000 {
|
2015-08-18 02:09:01 -06:00
|
|
|
compatible = "marvell,dove-crypto";
|
2015-08-18 02:09:00 -06:00
|
|
|
reg = <0x30000 0x10000>;
|
|
|
|
|
reg-names = "regs";
|
2013-12-11 13:29:13 -07:00
|
|
|
interrupts = <31>;
|
|
|
|
|
clocks = <&gate_clk 15>;
|
2015-08-18 02:09:00 -06:00
|
|
|
marvell,crypto-srams = <&crypto_sram>;
|
|
|
|
|
marvell,crypto-sram-size = <0x800>;
|
2013-12-11 13:29:13 -07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehci0: usb-host@50000 {
|
|
|
|
|
compatible = "marvell,orion-ehci";
|
|
|
|
|
reg = <0x50000 0x1000>;
|
|
|
|
|
interrupts = <24>;
|
|
|
|
|
clocks = <&gate_clk 0>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehci1: usb-host@51000 {
|
|
|
|
|
compatible = "marvell,orion-ehci";
|
|
|
|
|
reg = <0x51000 0x1000>;
|
|
|
|
|
interrupts = <25>;
|
|
|
|
|
clocks = <&gate_clk 1>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
xor0: dma-engine@60800 {
|
|
|
|
|
compatible = "marvell,orion-xor";
|
|
|
|
|
reg = <0x60800 0x100
|
|
|
|
|
0x60a00 0x100>;
|
|
|
|
|
clocks = <&gate_clk 23>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
channel0 {
|
|
|
|
|
interrupts = <39>;
|
|
|
|
|
dmacap,memcpy;
|
|
|
|
|
dmacap,xor;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
channel1 {
|
|
|
|
|
interrupts = <40>;
|
|
|
|
|
dmacap,memcpy;
|
|
|
|
|
dmacap,xor;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
xor1: dma-engine@60900 {
|
|
|
|
|
compatible = "marvell,orion-xor";
|
|
|
|
|
reg = <0x60900 0x100
|
|
|
|
|
0x60b00 0x100>;
|
|
|
|
|
clocks = <&gate_clk 24>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
channel0 {
|
|
|
|
|
interrupts = <42>;
|
|
|
|
|
dmacap,memcpy;
|
|
|
|
|
dmacap,xor;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
channel1 {
|
|
|
|
|
interrupts = <43>;
|
|
|
|
|
dmacap,memcpy;
|
|
|
|
|
dmacap,xor;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdio1: sdio-host@90000 {
|
|
|
|
|
compatible = "marvell,dove-sdhci";
|
|
|
|
|
reg = <0x90000 0x100>;
|
|
|
|
|
interrupts = <36>, <38>;
|
|
|
|
|
clocks = <&gate_clk 9>;
|
|
|
|
|
pinctrl-0 = <&pmx_sdio1>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
eth: ethernet-ctrl@72000 {
|
|
|
|
|
compatible = "marvell,orion-eth";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x72000 0x4000>;
|
|
|
|
|
clocks = <&gate_clk 2>;
|
|
|
|
|
marvell,tx-checksum-limit = <1600>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
ethernet-port@0 {
|
|
|
|
|
compatible = "marvell,orion-eth-port";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
interrupts = <29>;
|
|
|
|
|
/* overwrite MAC address in bootloader */
|
|
|
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
|
|
|
phy-handle = <ðphy>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mdio: mdio-bus@72004 {
|
|
|
|
|
compatible = "marvell,orion-mdio";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x72004 0x84>;
|
|
|
|
|
interrupts = <30>;
|
|
|
|
|
clocks = <&gate_clk 2>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
ethphy: ethernet-phy {
|
|
|
|
|
/* set phy address in board file */
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdio0: sdio-host@92000 {
|
|
|
|
|
compatible = "marvell,dove-sdhci";
|
|
|
|
|
reg = <0x92000 0x100>;
|
|
|
|
|
interrupts = <35>, <37>;
|
|
|
|
|
clocks = <&gate_clk 8>;
|
|
|
|
|
pinctrl-0 = <&pmx_sdio0>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sata0: sata-host@a0000 {
|
|
|
|
|
compatible = "marvell,orion-sata";
|
|
|
|
|
reg = <0xa0000 0x2400>;
|
|
|
|
|
interrupts = <62>;
|
|
|
|
|
clocks = <&gate_clk 3>;
|
2013-12-17 13:21:52 -07:00
|
|
|
phys = <&sata_phy0>;
|
|
|
|
|
phy-names = "port0";
|
2013-12-11 13:29:13 -07:00
|
|
|
nr-ports = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-17 13:21:52 -07:00
|
|
|
sata_phy0: sata-phy@a2000 {
|
|
|
|
|
compatible = "marvell,mvebu-sata-phy";
|
|
|
|
|
reg = <0xa2000 0x0334>;
|
|
|
|
|
clocks = <&gate_clk 3>;
|
|
|
|
|
clock-names = "sata";
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-11 13:29:13 -07:00
|
|
|
audio0: audio-controller@b0000 {
|
|
|
|
|
compatible = "marvell,dove-audio";
|
|
|
|
|
reg = <0xb0000 0x2210>;
|
|
|
|
|
interrupts = <19>, <20>;
|
|
|
|
|
clocks = <&gate_clk 12>;
|
|
|
|
|
clock-names = "internal";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
audio1: audio-controller@b4000 {
|
|
|
|
|
compatible = "marvell,dove-audio";
|
|
|
|
|
reg = <0xb4000 0x2210>;
|
|
|
|
|
interrupts = <21>, <22>;
|
|
|
|
|
clocks = <&gate_clk 13>;
|
|
|
|
|
clock-names = "internal";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2015-07-15 12:59:31 -06:00
|
|
|
pmu: power-management@d0000 {
|
|
|
|
|
compatible = "marvell,dove-pmu", "simple-bus";
|
|
|
|
|
reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
|
|
|
|
|
ranges = <0x00000000 0x000d0000 0x8000
|
|
|
|
|
0x00008000 0x000d8000 0x8000>;
|
|
|
|
|
interrupts = <33>;
|
2013-12-11 13:29:13 -07:00
|
|
|
interrupt-controller;
|
2015-07-15 12:59:31 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
|
|
|
|
|
domains {
|
2015-07-15 12:59:46 -06:00
|
|
|
vpu_domain: vpu-domain {
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
marvell,pmu_pwr_mask = <0x00000008>;
|
|
|
|
|
marvell,pmu_iso_mask = <0x00000001>;
|
|
|
|
|
resets = <&pmu 16>;
|
|
|
|
|
};
|
2015-07-15 12:59:52 -06:00
|
|
|
|
|
|
|
|
gpu_domain: gpu-domain {
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
marvell,pmu_pwr_mask = <0x00000004>;
|
|
|
|
|
marvell,pmu_iso_mask = <0x00000002>;
|
|
|
|
|
resets = <&pmu 18>;
|
|
|
|
|
};
|
2015-07-15 12:59:31 -06:00
|
|
|
};
|
|
|
|
|
|
2017-10-13 11:54:51 -06:00
|
|
|
thermal: thermal-diode@1c {
|
2015-07-15 12:59:31 -06:00
|
|
|
compatible = "marvell,dove-thermal";
|
|
|
|
|
reg = <0x001c 0x0c>, <0x005c 0x08>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-13 11:54:51 -06:00
|
|
|
gate_clk: clock-gating-ctrl@38 {
|
2015-07-15 12:59:31 -06:00
|
|
|
compatible = "marvell,dove-gating-clock";
|
|
|
|
|
reg = <0x0038 0x4>;
|
|
|
|
|
clocks = <&core_clk 0>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-13 11:54:51 -06:00
|
|
|
divider_clk: core-clock@64 {
|
2015-12-06 16:28:37 -07:00
|
|
|
compatible = "marvell,dove-divider-clock";
|
|
|
|
|
reg = <0x0064 0x8>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-13 11:54:51 -06:00
|
|
|
pinctrl: pin-ctrl@200 {
|
2015-07-15 12:59:31 -06:00
|
|
|
compatible = "marvell,dove-pinctrl";
|
|
|
|
|
reg = <0x0200 0x14>,
|
|
|
|
|
<0x0440 0x04>;
|
|
|
|
|
clocks = <&gate_clk 22>;
|
|
|
|
|
|
|
|
|
|
pmx_gpio_0: pmx-gpio-0 {
|
|
|
|
|
marvell,pins = "mpp0";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_1: pmx-gpio-1 {
|
|
|
|
|
marvell,pins = "mpp1";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_2: pmx-gpio-2 {
|
|
|
|
|
marvell,pins = "mpp2";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_3: pmx-gpio-3 {
|
|
|
|
|
marvell,pins = "mpp3";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_4: pmx-gpio-4 {
|
|
|
|
|
marvell,pins = "mpp4";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_5: pmx-gpio-5 {
|
|
|
|
|
marvell,pins = "mpp5";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_6: pmx-gpio-6 {
|
|
|
|
|
marvell,pins = "mpp6";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_7: pmx-gpio-7 {
|
|
|
|
|
marvell,pins = "mpp7";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_8: pmx-gpio-8 {
|
|
|
|
|
marvell,pins = "mpp8";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_9: pmx-gpio-9 {
|
|
|
|
|
marvell,pins = "mpp9";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_pcie1_clkreq: pmx-pcie1-clkreq {
|
|
|
|
|
marvell,pins = "mpp9";
|
|
|
|
|
marvell,function = "pex1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_10: pmx-gpio-10 {
|
|
|
|
|
marvell,pins = "mpp10";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_11: pmx-gpio-11 {
|
|
|
|
|
marvell,pins = "mpp11";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_pcie0_clkreq: pmx-pcie0-clkreq {
|
|
|
|
|
marvell,pins = "mpp11";
|
|
|
|
|
marvell,function = "pex0";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_12: pmx-gpio-12 {
|
|
|
|
|
marvell,pins = "mpp12";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_13: pmx-gpio-13 {
|
|
|
|
|
marvell,pins = "mpp13";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_audio1_extclk: pmx-audio1-extclk {
|
|
|
|
|
marvell,pins = "mpp13";
|
|
|
|
|
marvell,function = "audio1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_14: pmx-gpio-14 {
|
|
|
|
|
marvell,pins = "mpp14";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_15: pmx-gpio-15 {
|
|
|
|
|
marvell,pins = "mpp15";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_16: pmx-gpio-16 {
|
|
|
|
|
marvell,pins = "mpp16";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_17: pmx-gpio-17 {
|
|
|
|
|
marvell,pins = "mpp17";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_18: pmx-gpio-18 {
|
|
|
|
|
marvell,pins = "mpp18";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_19: pmx-gpio-19 {
|
|
|
|
|
marvell,pins = "mpp19";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_20: pmx-gpio-20 {
|
|
|
|
|
marvell,pins = "mpp20";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_gpio_21: pmx-gpio-21 {
|
|
|
|
|
marvell,pins = "mpp21";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_camera: pmx-camera {
|
|
|
|
|
marvell,pins = "mpp_camera";
|
|
|
|
|
marvell,function = "camera";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_camera_gpio: pmx-camera-gpio {
|
|
|
|
|
marvell,pins = "mpp_camera";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_sdio0: pmx-sdio0 {
|
|
|
|
|
marvell,pins = "mpp_sdio0";
|
|
|
|
|
marvell,function = "sdio0";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_sdio0_gpio: pmx-sdio0-gpio {
|
|
|
|
|
marvell,pins = "mpp_sdio0";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_sdio1: pmx-sdio1 {
|
|
|
|
|
marvell,pins = "mpp_sdio1";
|
|
|
|
|
marvell,function = "sdio1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_sdio1_gpio: pmx-sdio1-gpio {
|
|
|
|
|
marvell,pins = "mpp_sdio1";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_audio1_gpio: pmx-audio1-gpio {
|
|
|
|
|
marvell,pins = "mpp_audio1";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
|
|
|
|
|
marvell,pins = "mpp_audio1";
|
|
|
|
|
marvell,function = "i2s1/spdifo";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_spi0: pmx-spi0 {
|
|
|
|
|
marvell,pins = "mpp_spi0";
|
|
|
|
|
marvell,function = "spi0";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_spi0_gpio: pmx-spi0-gpio {
|
|
|
|
|
marvell,pins = "mpp_spi0";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_spi1_4_7: pmx-spi1-4-7 {
|
|
|
|
|
marvell,pins = "mpp4", "mpp5",
|
|
|
|
|
"mpp6", "mpp7";
|
|
|
|
|
marvell,function = "spi1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_spi1_20_23: pmx-spi1-20-23 {
|
|
|
|
|
marvell,pins = "mpp20", "mpp21",
|
|
|
|
|
"mpp22", "mpp23";
|
|
|
|
|
marvell,function = "spi1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_uart1: pmx-uart1 {
|
|
|
|
|
marvell,pins = "mpp_uart1";
|
|
|
|
|
marvell,function = "uart1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_uart1_gpio: pmx-uart1-gpio {
|
|
|
|
|
marvell,pins = "mpp_uart1";
|
|
|
|
|
marvell,function = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_nand: pmx-nand {
|
|
|
|
|
marvell,pins = "mpp_nand";
|
|
|
|
|
marvell,function = "nand";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_nand_gpo: pmx-nand-gpo {
|
|
|
|
|
marvell,pins = "mpp_nand";
|
|
|
|
|
marvell,function = "gpo";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_i2c1: pmx-i2c1 {
|
|
|
|
|
marvell,pins = "mpp17", "mpp19";
|
|
|
|
|
marvell,function = "twsi";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_i2c2: pmx-i2c2 {
|
|
|
|
|
marvell,pins = "mpp_audio1";
|
|
|
|
|
marvell,function = "twsi";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_ssp_i2c2: pmx-ssp-i2c2 {
|
|
|
|
|
marvell,pins = "mpp_audio1";
|
|
|
|
|
marvell,function = "ssp/twsi";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_i2cmux_0: pmx-i2cmux-0 {
|
|
|
|
|
marvell,pins = "twsi";
|
|
|
|
|
marvell,function = "twsi-opt1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_i2cmux_1: pmx-i2cmux-1 {
|
|
|
|
|
marvell,pins = "twsi";
|
|
|
|
|
marvell,function = "twsi-opt2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx_i2cmux_2: pmx-i2cmux-2 {
|
|
|
|
|
marvell,pins = "twsi";
|
|
|
|
|
marvell,function = "twsi-opt3";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-13 11:54:51 -06:00
|
|
|
core_clk: core-clocks@214 {
|
2015-07-15 12:59:31 -06:00
|
|
|
compatible = "marvell,dove-core-clock";
|
|
|
|
|
reg = <0x0214 0x4>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-13 11:54:51 -06:00
|
|
|
gpio0: gpio-ctrl@400 {
|
2015-07-15 12:59:31 -06:00
|
|
|
compatible = "marvell,orion-gpio";
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
reg = <0x0400 0x20>;
|
|
|
|
|
ngpios = <32>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
interrupts = <12>, <13>, <14>, <60>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-13 11:54:51 -06:00
|
|
|
gpio1: gpio-ctrl@420 {
|
2015-07-15 12:59:31 -06:00
|
|
|
compatible = "marvell,orion-gpio";
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
reg = <0x0420 0x20>;
|
|
|
|
|
ngpios = <32>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
interrupts = <61>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rtc: real-time-clock@8500 {
|
|
|
|
|
compatible = "marvell,orion-rtc";
|
|
|
|
|
reg = <0x8500 0x20>;
|
2015-07-15 12:59:41 -06:00
|
|
|
interrupts = <5>;
|
2015-07-15 12:59:31 -06:00
|
|
|
};
|
2013-07-29 06:31:53 -06:00
|
|
|
};
|
|
|
|
|
|
2014-02-24 01:42:56 -07:00
|
|
|
gconf: global-config@e802c {
|
|
|
|
|
compatible = "marvell,dove-global-config",
|
|
|
|
|
"syscon";
|
|
|
|
|
reg = <0xe802c 0x14>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-11 13:29:13 -07:00
|
|
|
gpio2: gpio-ctrl@e8400 {
|
|
|
|
|
compatible = "marvell,orion-gpio";
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
reg = <0xe8400 0x0c>;
|
|
|
|
|
ngpios = <8>;
|
2013-10-08 11:41:19 -06:00
|
|
|
};
|
2014-07-24 08:45:00 -06:00
|
|
|
|
|
|
|
|
lcd1: lcd-controller@810000 {
|
|
|
|
|
compatible = "marvell,dove-lcd";
|
|
|
|
|
reg = <0x810000 0x1000>;
|
|
|
|
|
interrupts = <46>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
lcd0: lcd-controller@820000 {
|
|
|
|
|
compatible = "marvell,dove-lcd";
|
|
|
|
|
reg = <0x820000 0x1000>;
|
|
|
|
|
interrupts = <47>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2015-08-18 02:09:00 -06:00
|
|
|
|
|
|
|
|
crypto_sram: sa-sram@ffffe000 {
|
|
|
|
|
compatible = "mmio-sram";
|
|
|
|
|
reg = <0xffffe000 0x800>;
|
|
|
|
|
clocks = <&gate_clk 15>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
};
|
2015-12-15 09:38:02 -07:00
|
|
|
|
|
|
|
|
gpu: gpu@840000 {
|
|
|
|
|
clocks = <÷r_clk 1>;
|
|
|
|
|
clock-names = "core";
|
|
|
|
|
compatible = "vivante,gc";
|
|
|
|
|
interrupts = <48>;
|
|
|
|
|
power-domains = <&gpu_domain>;
|
|
|
|
|
reg = <0x840000 0x4000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-07-02 05:00:18 -06:00
|
|
|
};
|
2012-08-15 11:07:34 -06:00
|
|
|
};
|
|
|
|
|
};
|