[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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/*
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* arch/arm/mach-mv78xx0/common.c
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*
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* Core functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/ata_platform.h>
|
2011-12-15 00:15:07 -07:00
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#include <linux/clk-provider.h>
|
2009-02-19 18:31:58 -07:00
|
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#include <linux/ethtool.h>
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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#include <asm/mach/map.h>
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|
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#include <asm/mach/time.h>
|
2008-08-05 09:14:15 -06:00
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#include <mach/mv78xx0.h>
|
2009-04-22 13:08:17 -06:00
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#include <mach/bridge-regs.h>
|
2008-08-09 05:44:58 -06:00
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#include <plat/cache-feroceon-l2.h>
|
2012-02-08 07:52:47 -07:00
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#include <plat/ehci-orion.h>
|
2008-08-09 05:44:58 -06:00
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#include <plat/orion_nand.h>
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#include <plat/time.h>
|
2011-05-15 05:32:41 -06:00
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#include <plat/common.h>
|
2011-12-07 13:48:06 -07:00
|
|
|
#include <plat/addr-map.h>
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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#include "common.h"
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|
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2011-05-15 05:32:41 -06:00
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static int get_tclk(void);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
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/*****************************************************************************
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* Common bits
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****************************************************************************/
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int mv78xx0_core_index(void)
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{
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u32 extra;
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/*
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* Read Extra Features register.
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*/
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__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
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return !!(extra & 0x00004000);
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}
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static int get_hclk(void)
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{
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int hclk;
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/*
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* HCLK tick rate is configured by DEV_D[7:5] pins.
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*/
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switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
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case 0:
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hclk = 166666667;
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break;
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case 1:
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hclk = 200000000;
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break;
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case 2:
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hclk = 266666667;
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break;
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case 3:
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hclk = 333333333;
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break;
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case 4:
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hclk = 400000000;
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break;
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default:
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panic("unknown HCLK PLL setting: %.8x\n",
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readl(SAMPLE_AT_RESET_LOW));
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}
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return hclk;
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}
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static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
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{
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u32 cfg;
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/*
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* Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
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* PCLK/L2CLK by bits [19:14].
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*/
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if (core_index == 0) {
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cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
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} else {
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cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
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}
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/*
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* Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
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* ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
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*/
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*pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
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/*
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* Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
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* ratio (1, 2, 3).
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*/
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*l2clk = *pclk / (((cfg >> 4) & 3) + 1);
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}
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static int get_tclk(void)
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|
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{
|
2011-12-15 00:15:07 -07:00
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int tclk_freq;
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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/*
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* TCLK tick rate is configured by DEV_A[2:0] strap pins.
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*/
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switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
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case 1:
|
2011-12-15 00:15:07 -07:00
|
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|
tclk_freq = 166666667;
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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|
break;
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|
case 3:
|
2011-12-15 00:15:07 -07:00
|
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|
tclk_freq = 200000000;
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
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|
break;
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|
|
default:
|
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|
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panic("unknown TCLK PLL setting: %.8x\n",
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|
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readl(SAMPLE_AT_RESET_HIGH));
|
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}
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|
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|
2011-12-15 00:15:07 -07:00
|
|
|
return tclk_freq;
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
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|
|
/*****************************************************************************
|
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|
|
* I/O Address Mapping
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|
|
****************************************************************************/
|
|
|
|
static struct map_desc mv78xx0_io_desc[] __initdata = {
|
|
|
|
{
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|
|
.virtual = MV78XX0_CORE_REGS_VIRT_BASE,
|
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|
|
.pfn = 0,
|
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|
|
.length = MV78XX0_CORE_REGS_SIZE,
|
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|
|
.type = MT_DEVICE,
|
|
|
|
}, {
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|
|
.virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
|
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|
|
.pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
|
|
|
|
.length = MV78XX0_PCIE_IO_SIZE * 8,
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|
|
.type = MT_DEVICE,
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|
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}, {
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|
|
.virtual = MV78XX0_REGS_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
|
|
|
|
.length = MV78XX0_REGS_SIZE,
|
|
|
|
.type = MT_DEVICE,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init mv78xx0_map_io(void)
|
|
|
|
{
|
|
|
|
unsigned long phys;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Map the right set of per-core registers depending on
|
|
|
|
* which core we are running on.
|
|
|
|
*/
|
|
|
|
if (mv78xx0_core_index() == 0) {
|
|
|
|
phys = MV78XX0_CORE0_REGS_PHYS_BASE;
|
|
|
|
} else {
|
|
|
|
phys = MV78XX0_CORE1_REGS_PHYS_BASE;
|
|
|
|
}
|
|
|
|
mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
|
|
|
|
|
|
|
|
iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-12-15 00:15:07 -07:00
|
|
|
/*****************************************************************************
|
|
|
|
* CLK tree
|
|
|
|
****************************************************************************/
|
|
|
|
static struct clk *tclk;
|
|
|
|
|
|
|
|
static void __init clk_init(void)
|
|
|
|
{
|
|
|
|
tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
|
|
|
|
get_tclk());
|
2012-04-06 09:17:26 -06:00
|
|
|
|
|
|
|
orion_clkdev_init(tclk);
|
2011-12-15 00:15:07 -07:00
|
|
|
}
|
|
|
|
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_ehci0_init(void)
|
|
|
|
{
|
2012-02-08 07:52:47 -07:00
|
|
|
orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI1
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_ehci1_init(void)
|
|
|
|
{
|
2011-12-07 13:48:08 -07:00
|
|
|
orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI2
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_ehci2_init(void)
|
|
|
|
{
|
2011-12-07 13:48:08 -07:00
|
|
|
orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* GE00
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
|
|
|
|
{
|
2011-12-07 13:48:08 -07:00
|
|
|
orion_ge00_init(eth_data,
|
2011-05-15 05:32:44 -06:00
|
|
|
GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
|
2011-12-23 17:24:24 -07:00
|
|
|
IRQ_MV78XX0_GE_ERR);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* GE01
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
|
|
|
|
{
|
2011-12-07 13:48:08 -07:00
|
|
|
orion_ge01_init(eth_data,
|
2011-05-15 05:32:44 -06:00
|
|
|
GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
|
2011-12-23 17:24:24 -07:00
|
|
|
NO_IRQ);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* GE10
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
|
|
|
|
{
|
2009-02-19 18:31:58 -07:00
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On the Z0, ge10 and ge11 are internally connected back
|
|
|
|
* to back, and not brought out.
|
|
|
|
*/
|
|
|
|
mv78xx0_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV78X00_Z0_DEV_ID) {
|
|
|
|
eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
|
|
|
|
eth_data->speed = SPEED_1000;
|
|
|
|
eth_data->duplex = DUPLEX_FULL;
|
|
|
|
}
|
|
|
|
|
2011-12-07 13:48:08 -07:00
|
|
|
orion_ge10_init(eth_data,
|
2011-05-15 05:32:44 -06:00
|
|
|
GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
|
2011-12-23 17:24:24 -07:00
|
|
|
NO_IRQ);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* GE11
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
|
|
|
|
{
|
2009-02-19 18:31:58 -07:00
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On the Z0, ge10 and ge11 are internally connected back
|
|
|
|
* to back, and not brought out.
|
|
|
|
*/
|
|
|
|
mv78xx0_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV78X00_Z0_DEV_ID) {
|
|
|
|
eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
|
|
|
|
eth_data->speed = SPEED_1000;
|
|
|
|
eth_data->duplex = DUPLEX_FULL;
|
|
|
|
}
|
|
|
|
|
2011-12-07 13:48:08 -07:00
|
|
|
orion_ge11_init(eth_data,
|
2011-05-15 05:32:44 -06:00
|
|
|
GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
|
2011-12-23 17:24:24 -07:00
|
|
|
NO_IRQ);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
2009-03-03 12:13:50 -07:00
|
|
|
/*****************************************************************************
|
2011-05-15 05:32:45 -06:00
|
|
|
* I2C
|
2009-03-03 12:13:50 -07:00
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_i2c_init(void)
|
|
|
|
{
|
2011-05-15 05:32:45 -06:00
|
|
|
orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
|
|
|
|
orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
|
2009-03-03 12:13:50 -07:00
|
|
|
}
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* SATA
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
|
|
|
|
{
|
2011-12-07 13:48:08 -07:00
|
|
|
orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* UART0
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_uart0_init(void)
|
|
|
|
{
|
2011-05-15 05:32:41 -06:00
|
|
|
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
|
2011-12-23 19:06:34 -07:00
|
|
|
IRQ_MV78XX0_UART_0, tclk);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* UART1
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_uart1_init(void)
|
|
|
|
{
|
2011-05-15 05:32:41 -06:00
|
|
|
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
|
2011-12-23 19:06:34 -07:00
|
|
|
IRQ_MV78XX0_UART_1, tclk);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* UART2
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_uart2_init(void)
|
|
|
|
{
|
2011-05-15 05:32:41 -06:00
|
|
|
orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
|
2011-12-23 19:06:34 -07:00
|
|
|
IRQ_MV78XX0_UART_2, tclk);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* UART3
|
|
|
|
****************************************************************************/
|
|
|
|
void __init mv78xx0_uart3_init(void)
|
|
|
|
{
|
2011-05-15 05:32:41 -06:00
|
|
|
orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
|
2011-12-23 19:06:34 -07:00
|
|
|
IRQ_MV78XX0_UART_3, tclk);
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* Time handling
|
|
|
|
****************************************************************************/
|
2010-10-15 08:50:26 -06:00
|
|
|
void __init mv78xx0_init_early(void)
|
|
|
|
{
|
|
|
|
orion_time_set_base(TIMER_VIRT_BASE);
|
|
|
|
}
|
|
|
|
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
static void mv78xx0_timer_init(void)
|
|
|
|
{
|
2010-10-15 08:50:26 -06:00
|
|
|
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
|
|
|
|
IRQ_MV78XX0_TIMER_1, get_tclk());
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
struct sys_timer mv78xx0_timer = {
|
|
|
|
.init = mv78xx0_timer_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* General
|
|
|
|
****************************************************************************/
|
2009-02-19 18:31:35 -07:00
|
|
|
static char * __init mv78xx0_id(void)
|
|
|
|
{
|
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
mv78xx0_pcie_id(&dev, &rev);
|
|
|
|
|
|
|
|
if (dev == MV78X00_Z0_DEV_ID) {
|
|
|
|
if (rev == MV78X00_REV_Z0)
|
|
|
|
return "MV78X00-Z0";
|
|
|
|
else
|
|
|
|
return "MV78X00-Rev-Unsupported";
|
|
|
|
} else if (dev == MV78100_DEV_ID) {
|
|
|
|
if (rev == MV78100_REV_A0)
|
|
|
|
return "MV78100-A0";
|
2009-09-30 14:02:42 -06:00
|
|
|
else if (rev == MV78100_REV_A1)
|
|
|
|
return "MV78100-A1";
|
2009-02-19 18:31:35 -07:00
|
|
|
else
|
|
|
|
return "MV78100-Rev-Unsupported";
|
|
|
|
} else if (dev == MV78200_DEV_ID) {
|
|
|
|
if (rev == MV78100_REV_A0)
|
|
|
|
return "MV78200-A0";
|
|
|
|
else
|
|
|
|
return "MV78200-Rev-Unsupported";
|
|
|
|
} else {
|
|
|
|
return "Device-Unknown";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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static int __init is_l2_writethrough(void)
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{
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return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
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}
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void __init mv78xx0_init(void)
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{
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int core_index;
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int hclk;
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int pclk;
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int l2clk;
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core_index = mv78xx0_core_index();
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hclk = get_hclk();
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get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
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2009-02-19 18:31:35 -07:00
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printk(KERN_INFO "%s ", mv78xx0_id());
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printk("core #%d, ", core_index);
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[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
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printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
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printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
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2011-12-15 00:15:07 -07:00
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printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
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[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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mv78xx0_setup_cpu_mbus();
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#ifdef CONFIG_CACHE_FEROCEON_L2
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feroceon_l2_init(is_l2_writethrough());
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#endif
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2011-12-15 00:15:07 -07:00
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/* Setup root of clk tree */
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clk_init();
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 14:45:10 -06:00
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}
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2011-11-05 04:09:15 -06:00
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void mv78xx0_restart(char mode, const char *cmd)
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{
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/*
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* Enable soft reset to assert RSTOUTn.
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*/
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writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
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/*
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* Assert soft reset.
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*/
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writel(SOFT_RESET, SYSTEM_SOFT_RESET);
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while (1)
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;
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}
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