2013-10-16 10:28:10 -06:00
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/*
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* Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2014-05-29 00:30:48 -06:00
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#include <linux/err.h>
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2013-10-16 10:28:10 -06:00
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#include <linux/io.h>
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#include <linux/kernel.h>
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2015-01-16 10:30:37 -07:00
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#include <linux/mfd/syscon/exynos4-pmu.h>
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2013-10-16 10:28:10 -06:00
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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#include <linux/mfd/syscon.h>
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2013-10-16 10:28:10 -06:00
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2015-01-16 10:30:37 -07:00
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/* MIPI_PHYn_CONTROL reg. offset (for base address from ioremap): n = 0..1 */
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2013-10-16 10:28:10 -06:00
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#define EXYNOS_MIPI_PHY_CONTROL(n) ((n) * 4)
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enum exynos_mipi_phy_id {
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EXYNOS_MIPI_PHY_ID_CSIS0,
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EXYNOS_MIPI_PHY_ID_DSIM0,
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EXYNOS_MIPI_PHY_ID_CSIS1,
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EXYNOS_MIPI_PHY_ID_DSIM1,
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EXYNOS_MIPI_PHYS_NUM
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};
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#define is_mipi_dsim_phy_id(id) \
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((id) == EXYNOS_MIPI_PHY_ID_DSIM0 || (id) == EXYNOS_MIPI_PHY_ID_DSIM1)
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struct exynos_mipi_video_phy {
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struct video_phy_desc {
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struct phy *phy;
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unsigned int index;
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} phys[EXYNOS_MIPI_PHYS_NUM];
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spinlock_t slock;
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void __iomem *regs;
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struct regmap *regmap;
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};
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static int __set_phy_state(struct exynos_mipi_video_phy *state,
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enum exynos_mipi_phy_id id, unsigned int on)
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{
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const unsigned int offset = EXYNOS4_MIPI_PHY_CONTROL(id / 2);
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void __iomem *addr;
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u32 val, reset;
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if (is_mipi_dsim_phy_id(id))
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reset = EXYNOS4_MIPI_PHY_MRESETN;
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else
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reset = EXYNOS4_MIPI_PHY_SRESETN;
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2015-02-26 20:50:57 -07:00
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spin_lock(&state->slock);
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2015-02-25 20:48:08 -07:00
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if (!IS_ERR(state->regmap)) {
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regmap_read(state->regmap, offset, &val);
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if (on)
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val |= reset;
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else
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val &= ~reset;
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regmap_write(state->regmap, offset, val);
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if (on)
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val |= EXYNOS4_MIPI_PHY_ENABLE;
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else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
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val &= ~EXYNOS4_MIPI_PHY_ENABLE;
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regmap_write(state->regmap, offset, val);
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} else {
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addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2);
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val = readl(addr);
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if (on)
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val |= reset;
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else
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val &= ~reset;
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writel(val, addr);
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/* Clear ENABLE bit only if MRESETN, SRESETN bits are not set */
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if (on)
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val |= EXYNOS4_MIPI_PHY_ENABLE;
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else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
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val &= ~EXYNOS4_MIPI_PHY_ENABLE;
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writel(val, addr);
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}
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2015-02-26 20:50:57 -07:00
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spin_unlock(&state->slock);
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return 0;
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}
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#define to_mipi_video_phy(desc) \
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container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index]);
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static int exynos_mipi_video_phy_power_on(struct phy *phy)
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{
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struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
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struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
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return __set_phy_state(state, phy_desc->index, 1);
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}
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static int exynos_mipi_video_phy_power_off(struct phy *phy)
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{
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struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
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struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
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2013-10-16 11:03:45 -06:00
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return __set_phy_state(state, phy_desc->index, 0);
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}
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static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
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2014-05-12 06:56:28 -06:00
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if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))
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return ERR_PTR(-ENODEV);
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return state->phys[args->args[0]].phy;
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}
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static struct phy_ops exynos_mipi_video_phy_ops = {
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.power_on = exynos_mipi_video_phy_power_on,
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.power_off = exynos_mipi_video_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
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{
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struct exynos_mipi_video_phy *state;
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struct device *dev = &pdev->dev;
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struct phy_provider *phy_provider;
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unsigned int i;
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state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
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if (!state)
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return -ENOMEM;
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2015-01-16 10:30:37 -07:00
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state->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
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if (IS_ERR(state->regmap)) {
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struct resource *res;
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dev_info(dev, "regmap lookup failed: %ld\n",
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PTR_ERR(state->regmap));
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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state->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(state->regs))
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return PTR_ERR(state->regs);
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}
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dev_set_drvdata(dev, state);
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spin_lock_init(&state->slock);
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for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {
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2014-07-14 04:25:02 -06:00
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struct phy *phy = devm_phy_create(dev, NULL,
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&exynos_mipi_video_phy_ops);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create PHY %d\n", i);
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return PTR_ERR(phy);
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}
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state->phys[i].phy = phy;
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state->phys[i].index = i;
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phy_set_drvdata(phy, &state->phys[i]);
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}
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2014-02-17 01:59:25 -07:00
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phy_provider = devm_of_phy_provider_register(dev,
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exynos_mipi_video_phy_xlate);
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2014-05-29 00:30:48 -06:00
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
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{ .compatible = "samsung,s5pv210-mipi-video-phy" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
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static struct platform_driver exynos_mipi_video_phy_driver = {
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.probe = exynos_mipi_video_phy_probe,
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.driver = {
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.of_match_table = exynos_mipi_video_phy_of_match,
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.name = "exynos-mipi-video-phy",
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}
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};
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module_platform_driver(exynos_mipi_video_phy_driver);
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MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
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MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
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MODULE_LICENSE("GPL v2");
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