2017-12-25 12:54:35 -07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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2011-10-02 18:46:13 -06:00
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* Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
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*
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* Inspired by pxafb.h
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*/
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#ifndef __ASM_PLAT_FB_S3C2410_H
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#define __ASM_PLAT_FB_S3C2410_H __FILE__
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2019-09-02 14:33:24 -06:00
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#include <linux/compiler_types.h>
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2011-10-02 18:46:13 -06:00
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struct s3c2410fb_hw {
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unsigned long lcdcon1;
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unsigned long lcdcon2;
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unsigned long lcdcon3;
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unsigned long lcdcon4;
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unsigned long lcdcon5;
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};
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/* LCD description */
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struct s3c2410fb_display {
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/* LCD type */
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unsigned type;
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#define S3C2410_LCDCON1_DSCAN4 (0<<5)
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#define S3C2410_LCDCON1_STN4 (1<<5)
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#define S3C2410_LCDCON1_STN8 (2<<5)
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#define S3C2410_LCDCON1_TFT (3<<5)
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#define S3C2410_LCDCON1_TFT1BPP (8<<1)
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#define S3C2410_LCDCON1_TFT2BPP (9<<1)
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#define S3C2410_LCDCON1_TFT4BPP (10<<1)
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#define S3C2410_LCDCON1_TFT8BPP (11<<1)
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#define S3C2410_LCDCON1_TFT16BPP (12<<1)
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#define S3C2410_LCDCON1_TFT24BPP (13<<1)
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2011-10-02 18:46:13 -06:00
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/* Screen size */
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unsigned short width;
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unsigned short height;
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/* Screen info */
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unsigned short xres;
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unsigned short yres;
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unsigned short bpp;
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unsigned pixclock; /* pixclock in picoseconds */
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unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
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unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
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unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
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unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */
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unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */
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unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */
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/* lcd configuration registers */
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unsigned long lcdcon5;
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#define S3C2410_LCDCON5_BPP24BL (1<<12)
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#define S3C2410_LCDCON5_FRM565 (1<<11)
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#define S3C2410_LCDCON5_INVVCLK (1<<10)
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#define S3C2410_LCDCON5_INVVLINE (1<<9)
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#define S3C2410_LCDCON5_INVVFRAME (1<<8)
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#define S3C2410_LCDCON5_INVVD (1<<7)
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#define S3C2410_LCDCON5_INVVDEN (1<<6)
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#define S3C2410_LCDCON5_INVPWREN (1<<5)
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#define S3C2410_LCDCON5_INVLEND (1<<4)
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#define S3C2410_LCDCON5_PWREN (1<<3)
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#define S3C2410_LCDCON5_ENLEND (1<<2)
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#define S3C2410_LCDCON5_BSWP (1<<1)
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#define S3C2410_LCDCON5_HWSWP (1<<0)
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};
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struct s3c2410fb_mach_info {
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2016-05-21 05:51:23 -06:00
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struct s3c2410fb_display *displays; /* attached displays info */
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unsigned num_displays; /* number of defined displays */
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unsigned default_display;
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/* GPIOs */
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unsigned long gpcup;
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unsigned long gpcup_mask;
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unsigned long gpccon;
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unsigned long gpccon_mask;
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unsigned long gpdup;
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unsigned long gpdup_mask;
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unsigned long gpdcon;
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unsigned long gpdcon_mask;
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2019-09-02 14:33:24 -06:00
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void __iomem * gpccon_reg;
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void __iomem * gpcup_reg;
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void __iomem * gpdcon_reg;
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void __iomem * gpdup_reg;
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2011-10-02 18:46:13 -06:00
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/* lpc3600 control register */
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unsigned long lpcsel;
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};
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2019-09-02 14:33:24 -06:00
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extern void s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
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2011-10-02 18:46:13 -06:00
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#endif /* __ASM_PLAT_FB_S3C2410_H */
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