2009-05-22 08:01:19 -06:00
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/*
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* wm9081.c -- WM9081 ALSA SoC Audio driver
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*
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* Author: Mark Brown
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*
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* Copyright 2009 Wolfson Microelectronics plc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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2011-03-01 13:05:23 -07:00
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#include <linux/device.h>
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2009-05-22 08:01:19 -06:00
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#include <linux/pm.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2009-05-22 08:01:19 -06:00
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <sound/wm9081.h>
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#include "wm9081.h"
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static u16 wm9081_reg_defaults[] = {
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0x0000, /* R0 - Software Reset */
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0x0000, /* R1 */
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0x00B9, /* R2 - Analogue Lineout */
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0x00B9, /* R3 - Analogue Speaker PGA */
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0x0001, /* R4 - VMID Control */
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0x0068, /* R5 - Bias Control 1 */
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0x0000, /* R6 */
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0x0000, /* R7 - Analogue Mixer */
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0x0000, /* R8 - Anti Pop Control */
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0x01DB, /* R9 - Analogue Speaker 1 */
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0x0018, /* R10 - Analogue Speaker 2 */
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0x0180, /* R11 - Power Management */
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0x0000, /* R12 - Clock Control 1 */
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0x0038, /* R13 - Clock Control 2 */
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0x4000, /* R14 - Clock Control 3 */
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0x0000, /* R15 */
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0x0000, /* R16 - FLL Control 1 */
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0x0200, /* R17 - FLL Control 2 */
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0x0000, /* R18 - FLL Control 3 */
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0x0204, /* R19 - FLL Control 4 */
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0x0000, /* R20 - FLL Control 5 */
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0x0000, /* R21 */
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0x0000, /* R22 - Audio Interface 1 */
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0x0002, /* R23 - Audio Interface 2 */
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0x0008, /* R24 - Audio Interface 3 */
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0x0022, /* R25 - Audio Interface 4 */
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0x0000, /* R26 - Interrupt Status */
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0x0006, /* R27 - Interrupt Status Mask */
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0x0000, /* R28 - Interrupt Polarity */
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0x0000, /* R29 - Interrupt Control */
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0x00C0, /* R30 - DAC Digital 1 */
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0x0008, /* R31 - DAC Digital 2 */
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0x09AF, /* R32 - DRC 1 */
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0x4201, /* R33 - DRC 2 */
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0x0000, /* R34 - DRC 3 */
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0x0000, /* R35 - DRC 4 */
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0x0000, /* R36 */
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0x0000, /* R37 */
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0x0000, /* R38 - Write Sequencer 1 */
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0x0000, /* R39 - Write Sequencer 2 */
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0x0002, /* R40 - MW Slave 1 */
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0x0000, /* R41 */
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0x0000, /* R42 - EQ 1 */
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0x0000, /* R43 - EQ 2 */
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0x0FCA, /* R44 - EQ 3 */
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0x0400, /* R45 - EQ 4 */
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0x00B8, /* R46 - EQ 5 */
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0x1EB5, /* R47 - EQ 6 */
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0xF145, /* R48 - EQ 7 */
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0x0B75, /* R49 - EQ 8 */
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0x01C5, /* R50 - EQ 9 */
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0x169E, /* R51 - EQ 10 */
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0xF829, /* R52 - EQ 11 */
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0x07AD, /* R53 - EQ 12 */
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0x1103, /* R54 - EQ 13 */
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0x1C58, /* R55 - EQ 14 */
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0xF373, /* R56 - EQ 15 */
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0x0A54, /* R57 - EQ 16 */
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0x0558, /* R58 - EQ 17 */
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0x0564, /* R59 - EQ 18 */
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0x0559, /* R60 - EQ 19 */
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0x4000, /* R61 - EQ 20 */
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};
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static struct {
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int ratio;
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int clk_sys_rate;
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} clk_sys_rates[] = {
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{ 64, 0 },
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{ 128, 1 },
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{ 192, 2 },
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{ 256, 3 },
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{ 384, 4 },
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{ 512, 5 },
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{ 768, 6 },
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{ 1024, 7 },
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{ 1408, 8 },
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{ 1536, 9 },
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};
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static struct {
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int rate;
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int sample_rate;
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} sample_rates[] = {
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{ 8000, 0 },
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{ 11025, 1 },
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{ 12000, 2 },
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{ 16000, 3 },
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{ 22050, 4 },
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{ 24000, 5 },
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{ 32000, 6 },
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{ 44100, 7 },
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{ 48000, 8 },
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{ 88200, 9 },
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{ 96000, 10 },
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};
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static struct {
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int div; /* *10 due to .5s */
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int bclk_div;
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} bclk_divs[] = {
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{ 10, 0 },
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{ 15, 1 },
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{ 20, 2 },
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{ 30, 3 },
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{ 40, 4 },
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{ 50, 5 },
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{ 55, 6 },
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{ 60, 7 },
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{ 80, 8 },
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{ 100, 9 },
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{ 110, 10 },
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{ 120, 11 },
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{ 160, 12 },
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{ 200, 13 },
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{ 220, 14 },
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{ 240, 15 },
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{ 250, 16 },
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{ 300, 17 },
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{ 320, 18 },
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{ 440, 19 },
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{ 480, 20 },
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};
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struct wm9081_priv {
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2010-03-17 14:15:21 -06:00
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enum snd_soc_control_type control_type;
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void *control_data;
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2009-05-22 08:01:19 -06:00
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int sysclk_source;
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int mclk_rate;
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int sysclk_rate;
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int fs;
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int bclk;
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int master;
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int fll_fref;
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int fll_fout;
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2009-08-11 09:28:39 -06:00
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int tdm_width;
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2011-03-01 13:10:46 -07:00
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struct wm9081_pdata pdata;
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2009-05-22 08:01:19 -06:00
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};
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2011-01-13 05:20:37 -07:00
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static int wm9081_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
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2009-05-22 08:01:19 -06:00
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{
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switch (reg) {
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2009-07-10 16:12:01 -06:00
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case WM9081_SOFTWARE_RESET:
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return 1;
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2009-05-22 08:01:19 -06:00
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default:
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return 0;
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}
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}
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static int wm9081_reset(struct snd_soc_codec *codec)
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{
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2009-07-10 16:12:01 -06:00
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return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
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2009-05-22 08:01:19 -06:00
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}
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static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
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static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
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static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
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static unsigned int drc_max_tlv[] = {
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TLV_DB_RANGE_HEAD(4),
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0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
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1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
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2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
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3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
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};
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static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
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static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
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static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
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static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
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static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
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static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
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static const char *drc_high_text[] = {
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"1",
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"1/2",
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"1/4",
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"1/8",
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"1/16",
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"0",
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};
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static const struct soc_enum drc_high =
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SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
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static const char *drc_low_text[] = {
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"1",
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"1/2",
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"1/4",
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"1/8",
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"0",
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};
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static const struct soc_enum drc_low =
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SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
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static const char *drc_atk_text[] = {
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"181us",
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"181us",
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"363us",
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"726us",
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"1.45ms",
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"2.9ms",
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"5.8ms",
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"11.6ms",
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"23.2ms",
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"46.4ms",
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"92.8ms",
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"185.6ms",
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};
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static const struct soc_enum drc_atk =
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SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
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static const char *drc_dcy_text[] = {
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"186ms",
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"372ms",
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"743ms",
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"1.49s",
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"2.97s",
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"5.94s",
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"11.89s",
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"23.78s",
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"47.56s",
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};
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static const struct soc_enum drc_dcy =
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SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
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static const char *drc_qr_dcy_text[] = {
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"0.725ms",
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"1.45ms",
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"5.8ms",
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};
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static const struct soc_enum drc_qr_dcy =
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SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
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static const char *dac_deemph_text[] = {
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"None",
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"32kHz",
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"44.1kHz",
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"48kHz",
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};
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static const struct soc_enum dac_deemph =
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SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
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static const char *speaker_mode_text[] = {
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"Class D",
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"Class AB",
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};
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static const struct soc_enum speaker_mode =
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SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
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static int speaker_mode_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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unsigned int reg;
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2009-07-10 16:12:01 -06:00
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reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
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2009-05-22 08:01:19 -06:00
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if (reg & WM9081_SPK_MODE)
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ucontrol->value.integer.value[0] = 1;
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else
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ucontrol->value.integer.value[0] = 0;
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return 0;
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}
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/*
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* Stop any attempts to change speaker mode while the speaker is enabled.
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*
|
2011-03-30 19:57:33 -06:00
|
|
|
* We also have some special anti-pop controls dependent on speaker
|
2009-05-22 08:01:19 -06:00
|
|
|
* mode which must be changed along with the mode.
|
|
|
|
*/
|
|
|
|
static int speaker_mode_put(struct snd_kcontrol *kcontrol,
|
|
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
|
2009-07-10 16:12:01 -06:00
|
|
|
unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
|
|
|
|
unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Are we changing anything? */
|
|
|
|
if (ucontrol->value.integer.value[0] ==
|
|
|
|
((reg2 & WM9081_SPK_MODE) != 0))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Don't try to change modes while enabled */
|
|
|
|
if (reg_pwr & WM9081_SPK_ENA)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (ucontrol->value.integer.value[0]) {
|
|
|
|
/* Class AB */
|
|
|
|
reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
|
|
|
|
reg2 |= WM9081_SPK_MODE;
|
|
|
|
} else {
|
|
|
|
/* Class D */
|
|
|
|
reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
|
|
|
|
reg2 &= ~WM9081_SPK_MODE;
|
|
|
|
}
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new wm9081_snd_controls[] = {
|
|
|
|
SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
|
|
|
|
SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
|
|
|
|
|
|
|
|
SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
|
|
|
|
|
|
|
|
SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
|
|
|
|
SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
|
|
|
|
SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
|
|
|
|
|
|
|
|
SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
|
|
|
|
SOC_ENUM("DRC High Slope", drc_high),
|
|
|
|
SOC_ENUM("DRC Low Slope", drc_low),
|
|
|
|
SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
|
|
|
|
SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
|
|
|
|
SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
|
|
|
|
SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
|
|
|
|
SOC_ENUM("DRC Attack", drc_atk),
|
|
|
|
SOC_ENUM("DRC Decay", drc_dcy),
|
|
|
|
SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
|
|
|
|
SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
|
|
|
|
SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
|
|
|
|
SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
|
|
|
|
|
|
|
|
SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
|
|
|
|
|
|
|
|
SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
|
|
|
|
SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
|
|
|
|
SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
|
|
|
|
SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
|
|
|
|
SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
|
|
|
|
out_tlv),
|
|
|
|
SOC_ENUM("DAC Deemphasis", dac_deemph),
|
|
|
|
SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new wm9081_eq_controls[] = {
|
|
|
|
SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
|
|
|
|
SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
|
|
|
|
SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
|
|
|
|
SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
|
|
|
|
SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new mixer[] = {
|
|
|
|
SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
|
|
|
|
SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
|
|
|
|
SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
|
|
|
|
};
|
|
|
|
|
|
|
|
struct _fll_div {
|
|
|
|
u16 fll_fratio;
|
|
|
|
u16 fll_outdiv;
|
|
|
|
u16 fll_clk_ref_div;
|
|
|
|
u16 n;
|
|
|
|
u16 k;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* The size in bits of the FLL divide multiplied by 10
|
|
|
|
* to allow rounding later */
|
|
|
|
#define FIXED_FLL_SIZE ((1 << 16) * 10)
|
|
|
|
|
|
|
|
static struct {
|
|
|
|
unsigned int min;
|
|
|
|
unsigned int max;
|
|
|
|
u16 fll_fratio;
|
|
|
|
int ratio;
|
|
|
|
} fll_fratios[] = {
|
|
|
|
{ 0, 64000, 4, 16 },
|
|
|
|
{ 64000, 128000, 3, 8 },
|
|
|
|
{ 128000, 256000, 2, 4 },
|
|
|
|
{ 256000, 1000000, 1, 2 },
|
|
|
|
{ 1000000, 13500000, 0, 1 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
|
|
|
|
unsigned int Fout)
|
|
|
|
{
|
|
|
|
u64 Kpart;
|
|
|
|
unsigned int K, Ndiv, Nmod, target;
|
|
|
|
unsigned int div;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Fref must be <=13.5MHz */
|
|
|
|
div = 1;
|
|
|
|
while ((Fref / div) > 13500000) {
|
|
|
|
div *= 2;
|
|
|
|
|
|
|
|
if (div > 8) {
|
|
|
|
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
|
|
|
|
Fref);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
fll_div->fll_clk_ref_div = div / 2;
|
|
|
|
|
|
|
|
pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
|
|
|
|
|
|
|
|
/* Apply the division for our remaining calculations */
|
|
|
|
Fref /= div;
|
|
|
|
|
|
|
|
/* Fvco should be 90-100MHz; don't check the upper bound */
|
|
|
|
div = 0;
|
|
|
|
target = Fout * 2;
|
|
|
|
while (target < 90000000) {
|
|
|
|
div++;
|
|
|
|
target *= 2;
|
|
|
|
if (div > 7) {
|
|
|
|
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
|
|
|
|
Fout);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
fll_div->fll_outdiv = div;
|
|
|
|
|
|
|
|
pr_debug("Fvco=%dHz\n", target);
|
|
|
|
|
2011-03-30 19:57:33 -06:00
|
|
|
/* Find an appropriate FLL_FRATIO and factor it out of the target */
|
2009-05-22 08:01:19 -06:00
|
|
|
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
|
|
|
|
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
|
|
|
|
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
|
|
|
|
target /= fll_fratios[i].ratio;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(fll_fratios)) {
|
|
|
|
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now, calculate N.K */
|
|
|
|
Ndiv = target / Fref;
|
|
|
|
|
|
|
|
fll_div->n = Ndiv;
|
|
|
|
Nmod = target % Fref;
|
|
|
|
pr_debug("Nmod=%d\n", Nmod);
|
|
|
|
|
|
|
|
/* Calculate fractional part - scale up so we can round. */
|
|
|
|
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
|
|
|
|
|
|
|
|
do_div(Kpart, Fref);
|
|
|
|
|
|
|
|
K = Kpart & 0xFFFFFFFF;
|
|
|
|
|
|
|
|
if ((K % 10) >= 5)
|
|
|
|
K += 5;
|
|
|
|
|
|
|
|
/* Move down to proper range now rounding is done */
|
|
|
|
fll_div->k = K / 10;
|
|
|
|
|
|
|
|
pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
|
|
|
|
fll_div->n, fll_div->k,
|
|
|
|
fll_div->fll_fratio, fll_div->fll_outdiv,
|
|
|
|
fll_div->fll_clk_ref_div);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
|
|
|
|
unsigned int Fref, unsigned int Fout)
|
|
|
|
{
|
2010-04-14 00:35:19 -06:00
|
|
|
struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
|
2009-05-22 08:01:19 -06:00
|
|
|
u16 reg1, reg4, reg5;
|
|
|
|
struct _fll_div fll_div;
|
|
|
|
int ret;
|
|
|
|
int clk_sys_reg;
|
|
|
|
|
|
|
|
/* Any change? */
|
|
|
|
if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Disable the FLL */
|
|
|
|
if (Fout == 0) {
|
|
|
|
dev_dbg(codec->dev, "FLL disabled\n");
|
|
|
|
wm9081->fll_fref = 0;
|
|
|
|
wm9081->fll_fout = 0;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = fll_factors(&fll_div, Fref, Fout);
|
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
|
|
|
|
|
|
|
|
switch (fll_id) {
|
|
|
|
case WM9081_SYSCLK_FLL_MCLK:
|
|
|
|
reg5 |= 0x1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable CLK_SYS while we reconfigure */
|
2009-07-10 16:12:01 -06:00
|
|
|
clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
|
2009-05-22 08:01:19 -06:00
|
|
|
if (clk_sys_reg & WM9081_CLK_SYS_ENA)
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
|
2009-05-22 08:01:19 -06:00
|
|
|
clk_sys_reg & ~WM9081_CLK_SYS_ENA);
|
|
|
|
|
|
|
|
/* Any FLL configuration change requires that the FLL be
|
|
|
|
* disabled first. */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg1 &= ~WM9081_FLL_ENA;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Apply the configuration */
|
|
|
|
if (fll_div.k)
|
|
|
|
reg1 |= WM9081_FLL_FRAC_MASK;
|
|
|
|
else
|
|
|
|
reg1 &= ~WM9081_FLL_FRAC_MASK;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_FLL_CONTROL_2,
|
2009-05-22 08:01:19 -06:00
|
|
|
(fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
|
|
|
|
(fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg4 &= ~WM9081_FLL_N_MASK;
|
|
|
|
reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
|
|
|
|
reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
2010-12-03 15:51:34 -07:00
|
|
|
/* Set gain to the recommended value */
|
|
|
|
snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
|
|
|
|
WM9081_FLL_GAIN_MASK, 0);
|
|
|
|
|
2009-05-22 08:01:19 -06:00
|
|
|
/* Enable the FLL */
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Then bring CLK_SYS up again if it was disabled */
|
|
|
|
if (clk_sys_reg & WM9081_CLK_SYS_ENA)
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
|
|
|
|
|
|
|
|
wm9081->fll_fref = Fref;
|
|
|
|
wm9081->fll_fout = Fout;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int configure_clock(struct snd_soc_codec *codec)
|
|
|
|
{
|
2010-04-14 00:35:19 -06:00
|
|
|
struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
|
2009-05-22 08:01:19 -06:00
|
|
|
int new_sysclk, i, target;
|
|
|
|
unsigned int reg;
|
|
|
|
int ret = 0;
|
|
|
|
int mclkdiv = 0;
|
|
|
|
int fll = 0;
|
|
|
|
|
|
|
|
switch (wm9081->sysclk_source) {
|
|
|
|
case WM9081_SYSCLK_MCLK:
|
|
|
|
if (wm9081->mclk_rate > 12225000) {
|
|
|
|
mclkdiv = 1;
|
|
|
|
wm9081->sysclk_rate = wm9081->mclk_rate / 2;
|
|
|
|
} else {
|
|
|
|
wm9081->sysclk_rate = wm9081->mclk_rate;
|
|
|
|
}
|
|
|
|
wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case WM9081_SYSCLK_FLL_MCLK:
|
|
|
|
/* If we have a sample rate calculate a CLK_SYS that
|
|
|
|
* gives us a suitable DAC configuration, plus BCLK.
|
|
|
|
* Ideally we would check to see if we can clock
|
|
|
|
* directly from MCLK and only use the FLL if this is
|
|
|
|
* not the case, though care must be taken with free
|
|
|
|
* running mode.
|
|
|
|
*/
|
|
|
|
if (wm9081->master && wm9081->bclk) {
|
|
|
|
/* Make sure we can generate CLK_SYS and BCLK
|
|
|
|
* and that we've got 3MHz for optimal
|
|
|
|
* performance. */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
|
|
|
|
target = wm9081->fs * clk_sys_rates[i].ratio;
|
2009-05-22 17:01:05 -06:00
|
|
|
new_sysclk = target;
|
2009-05-22 08:01:19 -06:00
|
|
|
if (target >= wm9081->bclk &&
|
|
|
|
target > 3000000)
|
2009-05-22 17:01:05 -06:00
|
|
|
break;
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
2009-07-15 03:36:51 -06:00
|
|
|
|
|
|
|
if (i == ARRAY_SIZE(clk_sys_rates))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2009-05-22 08:01:19 -06:00
|
|
|
} else if (wm9081->fs) {
|
|
|
|
for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
|
|
|
|
new_sysclk = clk_sys_rates[i].ratio
|
|
|
|
* wm9081->fs;
|
|
|
|
if (new_sysclk > 3000000)
|
|
|
|
break;
|
|
|
|
}
|
2009-07-15 03:36:51 -06:00
|
|
|
|
|
|
|
if (i == ARRAY_SIZE(clk_sys_rates))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2009-05-22 08:01:19 -06:00
|
|
|
} else {
|
|
|
|
new_sysclk = 12288000;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
|
|
|
|
wm9081->mclk_rate, new_sysclk);
|
|
|
|
if (ret == 0) {
|
|
|
|
wm9081->sysclk_rate = new_sysclk;
|
|
|
|
|
|
|
|
/* Switch SYSCLK over to FLL */
|
|
|
|
fll = 1;
|
|
|
|
} else {
|
|
|
|
wm9081->sysclk_rate = wm9081->mclk_rate;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
if (mclkdiv)
|
|
|
|
reg |= WM9081_MCLKDIV2;
|
|
|
|
else
|
|
|
|
reg &= ~WM9081_MCLKDIV2;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
|
2009-05-22 08:01:19 -06:00
|
|
|
if (fll)
|
|
|
|
reg |= WM9081_CLK_SRC_SEL;
|
|
|
|
else
|
|
|
|
reg &= ~WM9081_CLK_SRC_SEL;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_sys_event(struct snd_soc_dapm_widget *w,
|
|
|
|
struct snd_kcontrol *kcontrol, int event)
|
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = w->codec;
|
2010-04-14 00:35:19 -06:00
|
|
|
struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* This should be done on init() for bypass paths */
|
|
|
|
switch (wm9081->sysclk_source) {
|
|
|
|
case WM9081_SYSCLK_MCLK:
|
|
|
|
dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
|
|
|
|
break;
|
|
|
|
case WM9081_SYSCLK_FLL_MCLK:
|
|
|
|
dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
|
|
|
|
wm9081->mclk_rate);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(codec->dev, "System clock not configured\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
case SND_SOC_DAPM_PRE_PMU:
|
|
|
|
configure_clock(codec);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_DAPM_POST_PMD:
|
|
|
|
/* Disable the FLL if it's running */
|
|
|
|
wm9081_set_fll(codec, 0, 0, 0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
|
|
|
|
SND_SOC_DAPM_INPUT("IN1"),
|
|
|
|
SND_SOC_DAPM_INPUT("IN2"),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
|
|
|
|
mixer, ARRAY_SIZE(mixer)),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
|
|
|
|
|
2011-03-08 11:52:08 -07:00
|
|
|
SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
|
|
|
|
SND_SOC_DAPM_PGA("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("LINEOUT"),
|
|
|
|
SND_SOC_DAPM_OUTPUT("SPKN"),
|
|
|
|
SND_SOC_DAPM_OUTPUT("SPKP"),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
|
|
|
|
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
|
|
|
|
SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
|
|
|
|
SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
|
|
|
|
};
|
|
|
|
|
|
|
|
|
2011-03-07 09:39:50 -07:00
|
|
|
static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
|
2009-05-22 08:01:19 -06:00
|
|
|
{ "DAC", NULL, "CLK_SYS" },
|
|
|
|
{ "DAC", NULL, "CLK_DSP" },
|
|
|
|
|
|
|
|
{ "Mixer", "IN1 Switch", "IN1" },
|
|
|
|
{ "Mixer", "IN2 Switch", "IN2" },
|
|
|
|
{ "Mixer", "Playback Switch", "DAC" },
|
|
|
|
|
|
|
|
{ "LINEOUT PGA", NULL, "Mixer" },
|
|
|
|
{ "LINEOUT PGA", NULL, "TOCLK" },
|
|
|
|
{ "LINEOUT PGA", NULL, "CLK_SYS" },
|
|
|
|
|
|
|
|
{ "LINEOUT", NULL, "LINEOUT PGA" },
|
|
|
|
|
|
|
|
{ "Speaker PGA", NULL, "Mixer" },
|
|
|
|
{ "Speaker PGA", NULL, "TOCLK" },
|
|
|
|
{ "Speaker PGA", NULL, "CLK_SYS" },
|
|
|
|
|
2011-03-08 11:52:08 -07:00
|
|
|
{ "Speaker", NULL, "Speaker PGA" },
|
|
|
|
|
|
|
|
{ "SPKN", NULL, "Speaker" },
|
|
|
|
{ "SPKP", NULL, "Speaker" },
|
2009-05-22 08:01:19 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static int wm9081_set_bias_level(struct snd_soc_codec *codec,
|
|
|
|
enum snd_soc_bias_level level)
|
|
|
|
{
|
|
|
|
u16 reg;
|
|
|
|
|
|
|
|
switch (level) {
|
|
|
|
case SND_SOC_BIAS_ON:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_BIAS_PREPARE:
|
|
|
|
/* VMID=2*40k */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg &= ~WM9081_VMID_SEL_MASK;
|
|
|
|
reg |= 0x2;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Normal bias current */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg &= ~WM9081_STBY_BIAS_ENA;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_BIAS_STANDBY:
|
|
|
|
/* Initial cold start */
|
2010-11-05 07:53:46 -06:00
|
|
|
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
|
2009-05-22 08:01:19 -06:00
|
|
|
/* Disable LINEOUT discharge */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg &= ~WM9081_LINEOUT_DISCH;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Select startup bias source */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* VMID 2*4k; Soft VMID ramp enable */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg |= WM9081_VMID_RAMP | 0x6;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
mdelay(100);
|
|
|
|
|
|
|
|
/* Normal bias enable & soft start off */
|
|
|
|
reg |= WM9081_BIAS_ENA;
|
|
|
|
reg &= ~WM9081_VMID_RAMP;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Standard bias source */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg &= ~WM9081_BIAS_SRC;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* VMID 2*240k */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg &= ~WM9081_VMID_SEL_MASK;
|
|
|
|
reg |= 0x40;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Standby bias current on */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg |= WM9081_STBY_BIAS_ENA;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_BIAS_OFF:
|
|
|
|
/* Startup bias source */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg |= WM9081_BIAS_SRC;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Disable VMID and biases with soft ramping */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
|
|
|
|
reg |= WM9081_VMID_RAMP;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Actively discharge LINEOUT */
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
|
2009-05-22 08:01:19 -06:00
|
|
|
reg |= WM9081_LINEOUT_DISCH;
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-11-05 07:53:46 -06:00
|
|
|
codec->dapm.bias_level = level;
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
|
|
|
|
unsigned int fmt)
|
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = dai->codec;
|
2010-04-14 00:35:19 -06:00
|
|
|
struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
|
2009-07-10 16:12:01 -06:00
|
|
|
unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
|
|
|
|
WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
|
|
|
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
wm9081->master = 0;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFM:
|
|
|
|
aif2 |= WM9081_LRCLK_DIR;
|
|
|
|
wm9081->master = 1;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFS:
|
|
|
|
aif2 |= WM9081_BCLK_DIR;
|
|
|
|
wm9081->master = 1;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
|
|
|
|
wm9081->master = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
|
|
|
aif2 |= WM9081_AIF_LRCLK_INV;
|
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
|
|
|
aif2 |= 0x3;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
|
aif2 |= 0x2;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_RIGHT_J:
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
aif2 |= 0x1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
|
|
|
/* frame inversion not valid for DSP modes */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
|
|
aif2 |= WM9081_AIF_BCLK_INV;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
|
case SND_SOC_DAIFMT_RIGHT_J:
|
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
|
|
aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
|
|
aif2 |= WM9081_AIF_BCLK_INV;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
|
|
aif2 |= WM9081_AIF_LRCLK_INV;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wm9081_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = dai->codec;
|
2010-04-14 00:35:19 -06:00
|
|
|
struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
|
2009-05-22 08:01:19 -06:00
|
|
|
int ret, i, best, best_val, cur_val;
|
|
|
|
unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
|
2009-05-22 08:01:19 -06:00
|
|
|
clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
|
2009-05-22 08:01:19 -06:00
|
|
|
aif2 &= ~WM9081_AIF_WL_MASK;
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
|
2009-05-22 08:01:19 -06:00
|
|
|
aif3 &= ~WM9081_BCLK_DIV_MASK;
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
|
2009-05-22 08:01:19 -06:00
|
|
|
aif4 &= ~WM9081_LRCLK_RATE_MASK;
|
|
|
|
|
|
|
|
wm9081->fs = params_rate(params);
|
|
|
|
|
2009-08-11 09:28:39 -06:00
|
|
|
if (wm9081->tdm_width) {
|
|
|
|
/* If TDM is set up then that fixes our BCLK. */
|
2009-05-22 08:01:19 -06:00
|
|
|
int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
|
|
|
|
WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
|
2009-08-11 09:28:39 -06:00
|
|
|
|
|
|
|
wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
|
|
|
|
} else {
|
|
|
|
/* Otherwise work out a BCLK from the sample size */
|
|
|
|
wm9081->bclk = 2 * wm9081->fs;
|
|
|
|
|
|
|
|
switch (params_format(params)) {
|
|
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
|
|
wm9081->bclk *= 16;
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_FORMAT_S20_3LE:
|
|
|
|
wm9081->bclk *= 20;
|
|
|
|
aif2 |= 0x4;
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_FORMAT_S24_LE:
|
|
|
|
wm9081->bclk *= 24;
|
|
|
|
aif2 |= 0x8;
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
|
|
wm9081->bclk *= 32;
|
|
|
|
aif2 |= 0xc;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
|
|
|
|
|
|
|
|
ret = configure_clock(codec);
|
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Select nearest CLK_SYS_RATE */
|
|
|
|
best = 0;
|
|
|
|
best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
|
|
|
|
- wm9081->fs);
|
|
|
|
for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
|
|
|
|
cur_val = abs((wm9081->sysclk_rate /
|
2009-08-18 12:18:35 -06:00
|
|
|
clk_sys_rates[i].ratio) - wm9081->fs);
|
2009-05-22 08:01:19 -06:00
|
|
|
if (cur_val < best_val) {
|
|
|
|
best = i;
|
|
|
|
best_val = cur_val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
|
|
|
|
clk_sys_rates[best].ratio);
|
|
|
|
clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
|
|
|
|
<< WM9081_CLK_SYS_RATE_SHIFT);
|
|
|
|
|
|
|
|
/* SAMPLE_RATE */
|
|
|
|
best = 0;
|
|
|
|
best_val = abs(wm9081->fs - sample_rates[0].rate);
|
|
|
|
for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
|
|
|
|
/* Closest match */
|
|
|
|
cur_val = abs(wm9081->fs - sample_rates[i].rate);
|
|
|
|
if (cur_val < best_val) {
|
|
|
|
best = i;
|
|
|
|
best_val = cur_val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
|
|
|
|
sample_rates[best].rate);
|
2009-05-22 17:01:05 -06:00
|
|
|
clk_ctrl2 |= (sample_rates[best].sample_rate
|
|
|
|
<< WM9081_SAMPLE_RATE_SHIFT);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* BCLK_DIV */
|
|
|
|
best = 0;
|
|
|
|
best_val = INT_MAX;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
|
|
|
|
cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
|
|
|
|
- wm9081->bclk;
|
|
|
|
if (cur_val < 0) /* Table is sorted */
|
|
|
|
break;
|
|
|
|
if (cur_val < best_val) {
|
|
|
|
best = i;
|
|
|
|
best_val = cur_val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
|
|
|
|
dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
|
|
|
|
bclk_divs[best].div, wm9081->bclk);
|
|
|
|
aif3 |= bclk_divs[best].bclk_div;
|
|
|
|
|
|
|
|
/* LRCLK is a simple fraction of BCLK */
|
|
|
|
dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
|
|
|
|
aif4 |= wm9081->bclk / wm9081->fs;
|
|
|
|
|
|
|
|
/* Apply a ReTune Mobile configuration if it's in use */
|
2011-03-01 13:10:46 -07:00
|
|
|
if (wm9081->pdata.num_retune_configs) {
|
|
|
|
struct wm9081_pdata *pdata = &wm9081->pdata;
|
2009-05-22 08:01:19 -06:00
|
|
|
struct wm9081_retune_mobile_setting *s;
|
|
|
|
int eq1;
|
|
|
|
|
|
|
|
best = 0;
|
2011-03-01 13:10:46 -07:00
|
|
|
best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
|
|
|
|
for (i = 0; i < pdata->num_retune_configs; i++) {
|
|
|
|
cur_val = abs(pdata->retune_configs[i].rate -
|
|
|
|
wm9081->fs);
|
2009-05-22 08:01:19 -06:00
|
|
|
if (cur_val < best_val) {
|
|
|
|
best_val = cur_val;
|
|
|
|
best = i;
|
|
|
|
}
|
|
|
|
}
|
2011-03-01 13:10:46 -07:00
|
|
|
s = &pdata->retune_configs[best];
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
|
|
|
|
s->name, s->rate);
|
|
|
|
|
|
|
|
/* If the EQ is enabled then disable it while we write out */
|
2009-07-10 16:12:01 -06:00
|
|
|
eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
|
2009-05-22 08:01:19 -06:00
|
|
|
if (eq1 & WM9081_EQ_ENA)
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_EQ_1, 0);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
/* Write out the other values */
|
|
|
|
for (i = 1; i < ARRAY_SIZE(s->config); i++)
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_EQ_1, eq1);
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
|
|
|
|
snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
|
|
|
|
snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
|
|
|
|
snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
|
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = codec_dai->codec;
|
|
|
|
unsigned int reg;
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
if (mute)
|
|
|
|
reg |= WM9081_DAC_MUTE;
|
|
|
|
else
|
|
|
|
reg &= ~WM9081_DAC_MUTE;
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-03-07 13:59:45 -07:00
|
|
|
static int wm9081_set_sysclk(struct snd_soc_codec *codec,
|
2009-05-22 08:01:19 -06:00
|
|
|
int clk_id, unsigned int freq, int dir)
|
|
|
|
{
|
2010-04-14 00:35:19 -06:00
|
|
|
struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
switch (clk_id) {
|
|
|
|
case WM9081_SYSCLK_MCLK:
|
|
|
|
case WM9081_SYSCLK_FLL_MCLK:
|
|
|
|
wm9081->sysclk_source = clk_id;
|
|
|
|
wm9081->mclk_rate = freq;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
|
2009-06-15 18:44:31 -06:00
|
|
|
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
|
2009-05-22 08:01:19 -06:00
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = dai->codec;
|
2010-04-14 00:35:19 -06:00
|
|
|
struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
|
2009-07-10 16:12:01 -06:00
|
|
|
unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
|
|
|
|
|
2009-08-11 09:28:39 -06:00
|
|
|
if (slots < 0 || slots > 4)
|
2009-05-22 08:01:19 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
2009-08-11 09:28:39 -06:00
|
|
|
wm9081->tdm_width = slot_width;
|
|
|
|
|
|
|
|
if (slots == 0)
|
|
|
|
slots = 1;
|
|
|
|
|
2009-05-22 08:01:19 -06:00
|
|
|
aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
|
|
|
|
|
2009-06-15 18:44:31 -06:00
|
|
|
switch (rx_mask) {
|
2009-05-22 08:01:19 -06:00
|
|
|
case 1:
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
aif1 |= 0x10;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
aif1 |= 0x20;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
aif1 |= 0x30;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
|
|
|
|
|
|
|
|
#define WM9081_FORMATS \
|
|
|
|
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
|
|
|
|
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
|
|
|
|
|
|
|
|
static struct snd_soc_dai_ops wm9081_dai_ops = {
|
|
|
|
.hw_params = wm9081_hw_params,
|
|
|
|
.set_fmt = wm9081_set_dai_fmt,
|
|
|
|
.digital_mute = wm9081_digital_mute,
|
|
|
|
.set_tdm_slot = wm9081_set_tdm_slot,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* We report two channels because the CODEC processes a stereo signal, even
|
|
|
|
* though it is only capable of handling a mono output.
|
|
|
|
*/
|
2010-03-17 14:15:21 -06:00
|
|
|
static struct snd_soc_dai_driver wm9081_dai = {
|
|
|
|
.name = "wm9081-hifi",
|
2009-05-22 08:01:19 -06:00
|
|
|
.playback = {
|
|
|
|
.stream_name = "HiFi Playback",
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = WM9081_RATES,
|
|
|
|
.formats = WM9081_FORMATS,
|
|
|
|
},
|
|
|
|
.ops = &wm9081_dai_ops,
|
|
|
|
};
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static int wm9081_probe(struct snd_soc_codec *codec)
|
2009-05-22 08:01:19 -06:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
|
|
|
|
int ret;
|
|
|
|
u16 reg;
|
2009-05-22 08:01:19 -06:00
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
codec->control_data = wm9081->control_data;
|
|
|
|
ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type);
|
|
|
|
if (ret != 0) {
|
|
|
|
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
|
|
|
|
return ret;
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
|
|
|
|
if (reg != 0x9081) {
|
|
|
|
dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
|
|
|
|
ret = -EINVAL;
|
|
|
|
return ret;
|
|
|
|
}
|
2009-05-22 08:01:19 -06:00
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
ret = wm9081_reset(codec);
|
2009-05-22 08:01:19 -06:00
|
|
|
if (ret < 0) {
|
2010-03-17 14:15:21 -06:00
|
|
|
dev_err(codec->dev, "Failed to issue reset\n");
|
|
|
|
return ret;
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
|
|
|
|
2011-03-01 13:10:46 -07:00
|
|
|
reg = 0;
|
|
|
|
if (wm9081->pdata.irq_high)
|
|
|
|
reg |= WM9081_IRQ_POL;
|
|
|
|
if (!wm9081->pdata.irq_cmos)
|
|
|
|
reg |= WM9081_IRQ_OP_CTRL;
|
|
|
|
snd_soc_update_bits(codec, WM9081_INTERRUPT_CONTROL,
|
|
|
|
WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
|
|
|
|
|
|
/* Enable zero cross by default */
|
|
|
|
reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
|
|
|
|
snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
|
|
|
|
reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
|
|
|
|
snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
|
|
|
|
reg | WM9081_SPKPGAZC);
|
|
|
|
|
2009-05-22 08:01:19 -06:00
|
|
|
snd_soc_add_controls(codec, wm9081_snd_controls,
|
|
|
|
ARRAY_SIZE(wm9081_snd_controls));
|
2011-03-01 13:10:46 -07:00
|
|
|
if (!wm9081->pdata.num_retune_configs) {
|
2009-05-22 08:01:19 -06:00
|
|
|
dev_dbg(codec->dev,
|
|
|
|
"No ReTune Mobile data, using normal EQ\n");
|
|
|
|
snd_soc_add_controls(codec, wm9081_eq_controls,
|
|
|
|
ARRAY_SIZE(wm9081_eq_controls));
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static int wm9081_remove(struct snd_soc_codec *codec)
|
2009-05-22 08:01:19 -06:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
2009-05-22 08:01:19 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
2010-03-17 14:15:21 -06:00
|
|
|
static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
|
2009-05-22 08:01:19 -06:00
|
|
|
{
|
|
|
|
wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static int wm9081_resume(struct snd_soc_codec *codec)
|
2009-05-22 08:01:19 -06:00
|
|
|
{
|
|
|
|
u16 *reg_cache = codec->reg_cache;
|
|
|
|
int i;
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
for (i = 0; i < codec->driver->reg_cache_size; i++) {
|
2009-05-22 08:01:19 -06:00
|
|
|
if (i == WM9081_SOFTWARE_RESET)
|
|
|
|
continue;
|
|
|
|
|
2009-07-10 16:12:01 -06:00
|
|
|
snd_soc_write(codec, i, reg_cache[i]);
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define wm9081_suspend NULL
|
|
|
|
#define wm9081_resume NULL
|
|
|
|
#endif
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
|
2009-05-22 08:01:19 -06:00
|
|
|
.probe = wm9081_probe,
|
|
|
|
.remove = wm9081_remove,
|
|
|
|
.suspend = wm9081_suspend,
|
|
|
|
.resume = wm9081_resume,
|
2011-03-07 13:59:45 -07:00
|
|
|
|
|
|
|
.set_sysclk = wm9081_set_sysclk,
|
2010-03-17 14:15:21 -06:00
|
|
|
.set_bias_level = wm9081_set_bias_level,
|
2011-03-07 13:59:45 -07:00
|
|
|
|
2010-09-10 11:14:56 -06:00
|
|
|
.reg_cache_size = ARRAY_SIZE(wm9081_reg_defaults),
|
2010-03-17 14:15:21 -06:00
|
|
|
.reg_word_size = sizeof(u16),
|
|
|
|
.reg_cache_default = wm9081_reg_defaults,
|
|
|
|
.volatile_register = wm9081_volatile_register,
|
2011-03-07 13:59:45 -07:00
|
|
|
|
2011-03-07 09:39:50 -07:00
|
|
|
.dapm_widgets = wm9081_dapm_widgets,
|
|
|
|
.num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
|
|
|
|
.dapm_routes = wm9081_audio_paths,
|
|
|
|
.num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
|
2009-05-22 08:01:19 -06:00
|
|
|
};
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
|
2009-05-22 08:01:19 -06:00
|
|
|
static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
|
|
|
|
const struct i2c_device_id *id)
|
|
|
|
{
|
|
|
|
struct wm9081_priv *wm9081;
|
2010-03-17 14:15:21 -06:00
|
|
|
int ret;
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
|
|
|
|
if (wm9081 == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
i2c_set_clientdata(i2c, wm9081);
|
2010-12-28 13:08:57 -07:00
|
|
|
wm9081->control_type = SND_SOC_I2C;
|
2010-03-17 14:15:21 -06:00
|
|
|
wm9081->control_data = i2c;
|
2009-05-22 08:01:19 -06:00
|
|
|
|
2011-03-01 13:05:23 -07:00
|
|
|
if (dev_get_platdata(&i2c->dev))
|
2011-03-01 13:10:46 -07:00
|
|
|
memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
|
|
|
|
sizeof(wm9081->pdata));
|
2011-03-01 13:05:23 -07:00
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
ret = snd_soc_register_codec(&i2c->dev,
|
|
|
|
&soc_codec_dev_wm9081, &wm9081_dai, 1);
|
|
|
|
if (ret < 0)
|
|
|
|
kfree(wm9081);
|
|
|
|
return ret;
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static __devexit int wm9081_i2c_remove(struct i2c_client *client)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
snd_soc_unregister_codec(&client->dev);
|
|
|
|
kfree(i2c_get_clientdata(client));
|
2009-05-22 08:01:19 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_device_id wm9081_i2c_id[] = {
|
|
|
|
{ "wm9081", 0 },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
|
|
|
|
|
|
|
|
static struct i2c_driver wm9081_i2c_driver = {
|
|
|
|
.driver = {
|
2011-02-24 13:26:02 -07:00
|
|
|
.name = "wm9081",
|
2009-05-22 08:01:19 -06:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
.probe = wm9081_i2c_probe,
|
|
|
|
.remove = __devexit_p(wm9081_i2c_remove),
|
|
|
|
.id_table = wm9081_i2c_id,
|
|
|
|
};
|
2010-03-17 14:15:21 -06:00
|
|
|
#endif
|
2009-05-22 08:01:19 -06:00
|
|
|
|
|
|
|
static int __init wm9081_modinit(void)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
int ret = 0;
|
|
|
|
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
|
2009-05-22 08:01:19 -06:00
|
|
|
ret = i2c_add_driver(&wm9081_i2c_driver);
|
|
|
|
if (ret != 0) {
|
|
|
|
printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
|
|
|
|
ret);
|
|
|
|
}
|
2010-03-17 14:15:21 -06:00
|
|
|
#endif
|
2009-05-22 08:01:19 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
module_init(wm9081_modinit);
|
|
|
|
|
|
|
|
static void __exit wm9081_exit(void)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
|
2009-05-22 08:01:19 -06:00
|
|
|
i2c_del_driver(&wm9081_i2c_driver);
|
2010-03-17 14:15:21 -06:00
|
|
|
#endif
|
2009-05-22 08:01:19 -06:00
|
|
|
}
|
|
|
|
module_exit(wm9081_exit);
|
|
|
|
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("ASoC WM9081 driver");
|
|
|
|
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|