2008-06-23 05:50:15 -06:00
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/*
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* talitos - Freescale Integrated Security Engine (SEC) device driver
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*
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2011-07-14 21:21:38 -06:00
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* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
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2008-06-23 05:50:15 -06:00
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*
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* Scatterlist Crypto API glue code copied from files with the following:
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* Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
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*
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* Crypto algorithm registration code copied from hifn driver:
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* 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/crypto.h>
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#include <linux/hw_random.h>
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2013-09-17 13:28:33 -06:00
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2008-06-23 05:50:15 -06:00
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#include <linux/of_platform.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/rtnetlink.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2008-06-23 05:50:15 -06:00
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#include <crypto/algapi.h>
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#include <crypto/aes.h>
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2008-07-10 04:29:18 -06:00
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#include <crypto/des.h>
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2008-06-23 05:50:15 -06:00
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#include <crypto/sha.h>
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2010-05-19 03:20:36 -06:00
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#include <crypto/md5.h>
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2015-05-11 03:47:48 -06:00
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#include <crypto/internal/aead.h>
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2008-06-23 05:50:15 -06:00
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#include <crypto/authenc.h>
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2009-03-29 01:52:32 -06:00
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#include <crypto/skcipher.h>
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2010-05-19 03:19:33 -06:00
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#include <crypto/hash.h>
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#include <crypto/internal/hash.h>
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2009-03-29 01:52:32 -06:00
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#include <crypto/scatterwalk.h>
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2008-06-23 05:50:15 -06:00
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#include "talitos.h"
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2015-04-17 08:32:07 -06:00
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static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
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bool is_sec1)
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2009-08-12 19:51:51 -06:00
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{
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2015-04-17 08:31:53 -06:00
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ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
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2015-04-17 08:32:07 -06:00
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if (!is_sec1)
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ptr->eptr = upper_32_bits(dma_addr);
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2009-08-12 19:51:51 -06:00
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}
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2015-05-11 11:04:56 -06:00
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static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned int len,
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2015-04-17 08:32:07 -06:00
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bool is_sec1)
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2015-04-17 08:31:59 -06:00
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{
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2015-04-17 08:32:07 -06:00
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if (is_sec1) {
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ptr->res = 0;
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ptr->len1 = cpu_to_be16(len);
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} else {
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ptr->len = cpu_to_be16(len);
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}
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2015-04-17 08:31:59 -06:00
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}
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2015-04-17 08:32:07 -06:00
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static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
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bool is_sec1)
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2015-04-17 08:31:59 -06:00
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{
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2015-04-17 08:32:07 -06:00
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if (is_sec1)
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return be16_to_cpu(ptr->len1);
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else
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return be16_to_cpu(ptr->len);
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2015-04-17 08:31:59 -06:00
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}
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2015-04-17 08:32:07 -06:00
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static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr, bool is_sec1)
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2015-04-17 08:31:55 -06:00
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{
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2015-04-17 08:32:07 -06:00
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if (!is_sec1)
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ptr->j_extent = 0;
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2015-04-17 08:31:55 -06:00
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}
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2008-06-23 05:50:15 -06:00
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/*
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* map virtual single (contiguous) pointer to h/w descriptor pointer
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*/
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static void map_single_talitos_ptr(struct device *dev,
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2015-04-17 08:31:53 -06:00
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struct talitos_ptr *ptr,
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2015-05-11 11:04:56 -06:00
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unsigned int len, void *data,
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2008-06-23 05:50:15 -06:00
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enum dma_data_direction dir)
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{
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2009-08-12 19:51:51 -06:00
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dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
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2015-04-17 08:32:07 -06:00
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struct talitos_private *priv = dev_get_drvdata(dev);
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bool is_sec1 = has_ftr_sec1(priv);
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2009-08-12 19:51:51 -06:00
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2015-04-17 08:32:07 -06:00
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to_talitos_ptr_len(ptr, len, is_sec1);
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to_talitos_ptr(ptr, dma_addr, is_sec1);
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to_talitos_ptr_extent_clear(ptr, is_sec1);
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2008-06-23 05:50:15 -06:00
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}
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/*
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* unmap bus single (contiguous) h/w descriptor pointer
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*/
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static void unmap_single_talitos_ptr(struct device *dev,
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2015-04-17 08:31:53 -06:00
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struct talitos_ptr *ptr,
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2008-06-23 05:50:15 -06:00
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enum dma_data_direction dir)
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{
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2015-04-17 08:32:07 -06:00
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struct talitos_private *priv = dev_get_drvdata(dev);
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bool is_sec1 = has_ftr_sec1(priv);
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2015-04-17 08:31:53 -06:00
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dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
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2015-04-17 08:32:07 -06:00
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from_talitos_ptr_len(ptr, is_sec1), dir);
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2008-06-23 05:50:15 -06:00
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}
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static int reset_channel(struct device *dev, int ch)
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{
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struct talitos_private *priv = dev_get_drvdata(dev);
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unsigned int timeout = TALITOS_TIMEOUT;
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
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bool is_sec1 = has_ftr_sec1(priv);
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2008-06-23 05:50:15 -06:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
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if (is_sec1) {
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setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
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TALITOS1_CCCR_LO_RESET);
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2008-06-23 05:50:15 -06:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
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while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
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TALITOS1_CCCR_LO_RESET) && --timeout)
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cpu_relax();
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} else {
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setbits32(priv->chan[ch].reg + TALITOS_CCCR,
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TALITOS2_CCCR_RESET);
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while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
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TALITOS2_CCCR_RESET) && --timeout)
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cpu_relax();
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}
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2008-06-23 05:50:15 -06:00
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if (timeout == 0) {
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dev_err(dev, "failed to reset channel %d\n", ch);
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return -EIO;
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}
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2009-08-12 19:51:51 -06:00
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/* set 36-bit addressing, done writeback enable and done IRQ enable */
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2011-11-21 01:13:27 -07:00
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setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
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2009-08-12 19:51:51 -06:00
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TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
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2008-06-23 05:50:15 -06:00
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2008-10-12 06:33:14 -06:00
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/* and ICCR writeback, if available */
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if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
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2011-11-21 01:13:27 -07:00
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setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
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2008-10-12 06:33:14 -06:00
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TALITOS_CCCR_LO_IWSE);
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2008-06-23 05:50:15 -06:00
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return 0;
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}
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static int reset_device(struct device *dev)
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{
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struct talitos_private *priv = dev_get_drvdata(dev);
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unsigned int timeout = TALITOS_TIMEOUT;
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
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bool is_sec1 = has_ftr_sec1(priv);
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u32 mcr = is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
|
2008-06-23 05:50:15 -06:00
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2011-11-21 01:13:27 -07:00
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setbits32(priv->reg + TALITOS_MCR, mcr);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
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|
while ((in_be32(priv->reg + TALITOS_MCR) & mcr)
|
2008-06-23 05:50:15 -06:00
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&& --timeout)
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cpu_relax();
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2011-12-12 13:59:11 -07:00
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if (priv->irq[1]) {
|
2011-11-21 01:13:27 -07:00
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mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
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setbits32(priv->reg + TALITOS_MCR, mcr);
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}
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|
2008-06-23 05:50:15 -06:00
|
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|
if (timeout == 0) {
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|
|
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dev_err(dev, "failed to reset device\n");
|
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|
|
return -EIO;
|
|
|
|
}
|
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return 0;
|
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}
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|
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/*
|
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|
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* Reset and initialize the device
|
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*/
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static int init_device(struct device *dev)
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|
{
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|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
int ch, err;
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Master reset
|
|
|
|
* errata documentation: warning: certain SEC interrupts
|
|
|
|
* are not fully cleared by writing the MCR:SWR bit,
|
|
|
|
* set bit twice to completely reset
|
|
|
|
*/
|
|
|
|
err = reset_device(dev);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = reset_device(dev);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* reset channels */
|
|
|
|
for (ch = 0; ch < priv->num_channels; ch++) {
|
|
|
|
err = reset_channel(dev, ch);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* enable channel done and error interrupts */
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
if (is_sec1) {
|
|
|
|
clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
|
|
|
|
clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
|
|
|
|
/* disable parity error check in DEU (erroneous? test vect.) */
|
|
|
|
setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
|
|
|
|
} else {
|
|
|
|
setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT);
|
|
|
|
setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
|
|
|
|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2008-10-12 06:33:14 -06:00
|
|
|
/* disable integrity check error interrupts (use writeback instead) */
|
|
|
|
if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
|
2015-04-17 08:32:11 -06:00
|
|
|
setbits32(priv->reg_mdeu + TALITOS_EUICR_LO,
|
2008-10-12 06:33:14 -06:00
|
|
|
TALITOS_MDEUICR_LO_ICE);
|
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* talitos_submit - submits a descriptor to the device for processing
|
|
|
|
* @dev: the SEC device to be used
|
2011-07-14 21:21:38 -06:00
|
|
|
* @ch: the SEC device channel to be used
|
2008-06-23 05:50:15 -06:00
|
|
|
* @desc: the descriptor to be processed by the device
|
|
|
|
* @callback: whom to call when processing is complete
|
|
|
|
* @context: a handle for use by caller (optional)
|
|
|
|
*
|
|
|
|
* desc must contain valid dma-mapped (bus physical) address pointers.
|
|
|
|
* callback must check err and feedback in descriptor header
|
|
|
|
* for device processing status.
|
|
|
|
*/
|
2012-07-03 10:16:52 -06:00
|
|
|
int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
|
|
|
|
void (*callback)(struct device *dev,
|
|
|
|
struct talitos_desc *desc,
|
|
|
|
void *context, int error),
|
|
|
|
void *context)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
struct talitos_request *request;
|
2011-07-14 21:21:38 -06:00
|
|
|
unsigned long flags;
|
2008-06-23 05:50:15 -06:00
|
|
|
int head;
|
2015-04-17 08:32:09 -06:00
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
|
2008-07-17 06:16:40 -06:00
|
|
|
/* h/w fifo is full */
|
2009-08-12 19:50:38 -06:00
|
|
|
spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
|
2008-06-23 05:50:15 -06:00
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
head = priv->chan[ch].head;
|
|
|
|
request = &priv->chan[ch].fifo[head];
|
2008-07-17 06:16:40 -06:00
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
/* map descriptor and save caller data */
|
2015-04-17 08:32:09 -06:00
|
|
|
if (is_sec1) {
|
|
|
|
desc->hdr1 = desc->hdr;
|
|
|
|
desc->next_desc = 0;
|
|
|
|
request->dma_desc = dma_map_single(dev, &desc->hdr1,
|
|
|
|
TALITOS_DESC_SIZE,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
} else {
|
|
|
|
request->dma_desc = dma_map_single(dev, desc,
|
|
|
|
TALITOS_DESC_SIZE,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
request->callback = callback;
|
|
|
|
request->context = context;
|
|
|
|
|
|
|
|
/* increment fifo head */
|
2009-08-12 19:50:38 -06:00
|
|
|
priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
smp_wmb();
|
|
|
|
request->desc = desc;
|
|
|
|
|
|
|
|
/* GO! */
|
|
|
|
wmb();
|
2011-11-21 01:13:27 -07:00
|
|
|
out_be32(priv->chan[ch].reg + TALITOS_FF,
|
|
|
|
upper_32_bits(request->dma_desc));
|
|
|
|
out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
|
2010-09-23 01:56:38 -06:00
|
|
|
lower_32_bits(request->dma_desc));
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
2012-07-03 10:16:52 -06:00
|
|
|
EXPORT_SYMBOL(talitos_submit);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* process what was done, notify callback of error if not
|
|
|
|
*/
|
|
|
|
static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
|
|
|
|
{
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
struct talitos_request *request, saved_req;
|
|
|
|
unsigned long flags;
|
|
|
|
int tail, status;
|
2015-04-17 08:32:09 -06:00
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
tail = priv->chan[ch].tail;
|
|
|
|
while (priv->chan[ch].fifo[tail].desc) {
|
2015-04-17 08:32:09 -06:00
|
|
|
__be32 hdr;
|
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
request = &priv->chan[ch].fifo[tail];
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* descriptors with their done bits set don't get the error */
|
|
|
|
rmb();
|
2015-04-17 08:32:09 -06:00
|
|
|
hdr = is_sec1 ? request->desc->hdr1 : request->desc->hdr;
|
|
|
|
|
|
|
|
if ((hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
|
2008-06-23 05:50:15 -06:00
|
|
|
status = 0;
|
2008-12-19 23:09:25 -07:00
|
|
|
else
|
2008-06-23 05:50:15 -06:00
|
|
|
if (!error)
|
|
|
|
break;
|
|
|
|
else
|
|
|
|
status = error;
|
|
|
|
|
|
|
|
dma_unmap_single(dev, request->dma_desc,
|
2015-04-17 08:32:09 -06:00
|
|
|
TALITOS_DESC_SIZE,
|
2009-03-29 01:53:23 -06:00
|
|
|
DMA_BIDIRECTIONAL);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* copy entries so we can call callback outside lock */
|
|
|
|
saved_req.desc = request->desc;
|
|
|
|
saved_req.callback = request->callback;
|
|
|
|
saved_req.context = request->context;
|
|
|
|
|
|
|
|
/* release request entry in fifo */
|
|
|
|
smp_wmb();
|
|
|
|
request->desc = NULL;
|
|
|
|
|
|
|
|
/* increment fifo tail */
|
2009-08-12 19:50:38 -06:00
|
|
|
priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
|
2008-07-17 06:16:40 -06:00
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
atomic_dec(&priv->chan[ch].submit_count);
|
2008-07-17 06:16:40 -06:00
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
saved_req.callback(dev, saved_req.desc, saved_req.context,
|
|
|
|
status);
|
|
|
|
/* channel may resume processing in single desc error case */
|
|
|
|
if (error && !reset_ch && status == error)
|
|
|
|
return;
|
2009-08-12 19:50:38 -06:00
|
|
|
spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
|
|
|
|
tail = priv->chan[ch].tail;
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* process completed requests for channels that have done status
|
|
|
|
*/
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
#define DEF_TALITOS1_DONE(name, ch_done_mask) \
|
|
|
|
static void talitos1_done_##name(unsigned long data) \
|
|
|
|
{ \
|
|
|
|
struct device *dev = (struct device *)data; \
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev); \
|
|
|
|
unsigned long flags; \
|
|
|
|
\
|
|
|
|
if (ch_done_mask & 0x10000000) \
|
|
|
|
flush_channel(dev, 0, 0, 0); \
|
|
|
|
if (priv->num_channels == 1) \
|
|
|
|
goto out; \
|
|
|
|
if (ch_done_mask & 0x40000000) \
|
|
|
|
flush_channel(dev, 1, 0, 0); \
|
|
|
|
if (ch_done_mask & 0x00010000) \
|
|
|
|
flush_channel(dev, 2, 0, 0); \
|
|
|
|
if (ch_done_mask & 0x00040000) \
|
|
|
|
flush_channel(dev, 3, 0, 0); \
|
|
|
|
\
|
|
|
|
out: \
|
|
|
|
/* At this point, all completed channels have been processed */ \
|
|
|
|
/* Unmask done interrupts for channels completed later on. */ \
|
|
|
|
spin_lock_irqsave(&priv->reg_lock, flags); \
|
|
|
|
clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
|
|
|
|
clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT); \
|
|
|
|
spin_unlock_irqrestore(&priv->reg_lock, flags); \
|
|
|
|
}
|
|
|
|
|
|
|
|
DEF_TALITOS1_DONE(4ch, TALITOS1_ISR_4CHDONE)
|
|
|
|
|
|
|
|
#define DEF_TALITOS2_DONE(name, ch_done_mask) \
|
|
|
|
static void talitos2_done_##name(unsigned long data) \
|
2011-11-21 01:13:27 -07:00
|
|
|
{ \
|
|
|
|
struct device *dev = (struct device *)data; \
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev); \
|
2012-03-30 08:49:53 -06:00
|
|
|
unsigned long flags; \
|
2011-11-21 01:13:27 -07:00
|
|
|
\
|
|
|
|
if (ch_done_mask & 1) \
|
|
|
|
flush_channel(dev, 0, 0, 0); \
|
|
|
|
if (priv->num_channels == 1) \
|
|
|
|
goto out; \
|
|
|
|
if (ch_done_mask & (1 << 2)) \
|
|
|
|
flush_channel(dev, 1, 0, 0); \
|
|
|
|
if (ch_done_mask & (1 << 4)) \
|
|
|
|
flush_channel(dev, 2, 0, 0); \
|
|
|
|
if (ch_done_mask & (1 << 6)) \
|
|
|
|
flush_channel(dev, 3, 0, 0); \
|
|
|
|
\
|
|
|
|
out: \
|
|
|
|
/* At this point, all completed channels have been processed */ \
|
|
|
|
/* Unmask done interrupts for channels completed later on. */ \
|
2012-03-30 08:49:53 -06:00
|
|
|
spin_lock_irqsave(&priv->reg_lock, flags); \
|
2011-11-21 01:13:27 -07:00
|
|
|
setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); \
|
2012-03-30 08:49:53 -06:00
|
|
|
spin_unlock_irqrestore(&priv->reg_lock, flags); \
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
|
|
|
|
DEF_TALITOS2_DONE(4ch, TALITOS2_ISR_4CHDONE)
|
|
|
|
DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
|
|
|
|
DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* locate current (offending) descriptor
|
|
|
|
*/
|
2011-10-21 07:20:28 -06:00
|
|
|
static u32 current_desc_hdr(struct device *dev, int ch)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
2013-11-13 03:20:37 -07:00
|
|
|
int tail, iter;
|
2008-06-23 05:50:15 -06:00
|
|
|
dma_addr_t cur_desc;
|
|
|
|
|
2013-11-13 03:20:37 -07:00
|
|
|
cur_desc = ((u64)in_be32(priv->chan[ch].reg + TALITOS_CDPR)) << 32;
|
|
|
|
cur_desc |= in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2013-11-13 03:20:37 -07:00
|
|
|
if (!cur_desc) {
|
|
|
|
dev_err(dev, "CDPR is NULL, giving up search for offending descriptor\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
tail = priv->chan[ch].tail;
|
|
|
|
|
|
|
|
iter = tail;
|
|
|
|
while (priv->chan[ch].fifo[iter].dma_desc != cur_desc) {
|
|
|
|
iter = (iter + 1) & (priv->fifo_len - 1);
|
|
|
|
if (iter == tail) {
|
2008-06-23 05:50:15 -06:00
|
|
|
dev_err(dev, "couldn't locate current descriptor\n");
|
2011-10-21 07:20:28 -06:00
|
|
|
return 0;
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-13 03:20:37 -07:00
|
|
|
return priv->chan[ch].fifo[iter].desc->hdr;
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* user diagnostics; report root cause of error based on execution unit status
|
|
|
|
*/
|
2011-10-21 07:20:28 -06:00
|
|
|
static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
int i;
|
|
|
|
|
2011-10-21 07:20:28 -06:00
|
|
|
if (!desc_hdr)
|
2011-11-21 01:13:27 -07:00
|
|
|
desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
|
2011-10-21 07:20:28 -06:00
|
|
|
|
|
|
|
switch (desc_hdr & DESC_HDR_SEL0_MASK) {
|
2008-06-23 05:50:15 -06:00
|
|
|
case DESC_HDR_SEL0_AFEU:
|
|
|
|
dev_err(dev, "AFEUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_afeu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_afeu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
case DESC_HDR_SEL0_DEU:
|
|
|
|
dev_err(dev, "DEUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_deu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_deu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
case DESC_HDR_SEL0_MDEUA:
|
|
|
|
case DESC_HDR_SEL0_MDEUB:
|
|
|
|
dev_err(dev, "MDEUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_mdeu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_mdeu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
case DESC_HDR_SEL0_RNG:
|
|
|
|
dev_err(dev, "RNGUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_rngu + TALITOS_ISR),
|
|
|
|
in_be32(priv->reg_rngu + TALITOS_ISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
case DESC_HDR_SEL0_PKEU:
|
|
|
|
dev_err(dev, "PKEUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_pkeu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_pkeu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
case DESC_HDR_SEL0_AESU:
|
|
|
|
dev_err(dev, "AESUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_aesu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_aesu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
case DESC_HDR_SEL0_CRCU:
|
|
|
|
dev_err(dev, "CRCUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_crcu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_crcu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
case DESC_HDR_SEL0_KEU:
|
|
|
|
dev_err(dev, "KEUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_pkeu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_pkeu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-10-21 07:20:28 -06:00
|
|
|
switch (desc_hdr & DESC_HDR_SEL1_MASK) {
|
2008-06-23 05:50:15 -06:00
|
|
|
case DESC_HDR_SEL1_MDEUA:
|
|
|
|
case DESC_HDR_SEL1_MDEUB:
|
|
|
|
dev_err(dev, "MDEUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_mdeu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_mdeu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
case DESC_HDR_SEL1_CRCU:
|
|
|
|
dev_err(dev, "CRCUISR 0x%08x_%08x\n",
|
2015-04-17 08:32:11 -06:00
|
|
|
in_be32(priv->reg_crcu + TALITOS_EUISR),
|
|
|
|
in_be32(priv->reg_crcu + TALITOS_EUISR_LO));
|
2008-06-23 05:50:15 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++)
|
|
|
|
dev_err(dev, "DESCBUF 0x%08x_%08x\n",
|
2011-11-21 01:13:27 -07:00
|
|
|
in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
|
|
|
|
in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* recover from error interrupts
|
|
|
|
*/
|
2011-12-12 13:59:12 -07:00
|
|
|
static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
unsigned int timeout = TALITOS_TIMEOUT;
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
int ch, error, reset_dev = 0;
|
2015-05-11 11:04:56 -06:00
|
|
|
u32 v_lo;
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
|
|
|
int reset_ch = is_sec1 ? 1 : 0; /* only SEC2 supports continuation */
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
for (ch = 0; ch < priv->num_channels; ch++) {
|
|
|
|
/* skip channels without errors */
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
if (is_sec1) {
|
|
|
|
/* bits 29, 31, 17, 19 */
|
|
|
|
if (!(isr & (1 << (29 + (ch & 1) * 2 - (ch & 2) * 6))))
|
|
|
|
continue;
|
|
|
|
} else {
|
|
|
|
if (!(isr & (1 << (ch * 2 + 1))))
|
|
|
|
continue;
|
|
|
|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
error = -EINVAL;
|
|
|
|
|
2011-11-21 01:13:27 -07:00
|
|
|
v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_DOF) {
|
|
|
|
dev_err(dev, "double fetch fifo overflow error\n");
|
|
|
|
error = -EAGAIN;
|
|
|
|
reset_ch = 1;
|
|
|
|
}
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_SOF) {
|
|
|
|
/* h/w dropped descriptor */
|
|
|
|
dev_err(dev, "single fetch fifo overflow error\n");
|
|
|
|
error = -EAGAIN;
|
|
|
|
}
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_MDTE)
|
|
|
|
dev_err(dev, "master data transfer error\n");
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
dev_err(dev, is_sec1 ? "pointeur not complete error\n"
|
|
|
|
: "s/g data length zero error\n");
|
2008-06-23 05:50:15 -06:00
|
|
|
if (v_lo & TALITOS_CCPSR_LO_FPZ)
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
dev_err(dev, is_sec1 ? "parity error\n"
|
|
|
|
: "fetch pointer zero error\n");
|
2008-06-23 05:50:15 -06:00
|
|
|
if (v_lo & TALITOS_CCPSR_LO_IDH)
|
|
|
|
dev_err(dev, "illegal descriptor header error\n");
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_IEU)
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
dev_err(dev, is_sec1 ? "static assignment error\n"
|
|
|
|
: "invalid exec unit error\n");
|
2008-06-23 05:50:15 -06:00
|
|
|
if (v_lo & TALITOS_CCPSR_LO_EU)
|
2011-10-21 07:20:28 -06:00
|
|
|
report_eu_error(dev, ch, current_desc_hdr(dev, ch));
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
if (!is_sec1) {
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_GB)
|
|
|
|
dev_err(dev, "gather boundary error\n");
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_GRL)
|
|
|
|
dev_err(dev, "gather return/length error\n");
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_SB)
|
|
|
|
dev_err(dev, "scatter boundary error\n");
|
|
|
|
if (v_lo & TALITOS_CCPSR_LO_SRL)
|
|
|
|
dev_err(dev, "scatter return/length error\n");
|
|
|
|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
flush_channel(dev, ch, error, reset_ch);
|
|
|
|
|
|
|
|
if (reset_ch) {
|
|
|
|
reset_channel(dev, ch);
|
|
|
|
} else {
|
2011-11-21 01:13:27 -07:00
|
|
|
setbits32(priv->chan[ch].reg + TALITOS_CCCR,
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
TALITOS2_CCCR_CONT);
|
2011-11-21 01:13:27 -07:00
|
|
|
setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
|
|
|
|
while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
TALITOS2_CCCR_CONT) && --timeout)
|
2008-06-23 05:50:15 -06:00
|
|
|
cpu_relax();
|
|
|
|
if (timeout == 0) {
|
|
|
|
dev_err(dev, "failed to restart channel %d\n",
|
|
|
|
ch);
|
|
|
|
reset_dev = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
if (reset_dev || (is_sec1 && isr & ~TALITOS1_ISR_4CHERR) ||
|
|
|
|
(!is_sec1 && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) {
|
|
|
|
if (is_sec1 && (isr_lo & TALITOS1_ISR_TEA_ERR))
|
|
|
|
dev_err(dev, "TEA error: ISR 0x%08x_%08x\n",
|
|
|
|
isr, isr_lo);
|
|
|
|
else
|
|
|
|
dev_err(dev, "done overflow, internal time out, or "
|
|
|
|
"rngu error: ISR 0x%08x_%08x\n", isr, isr_lo);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* purge request queues */
|
|
|
|
for (ch = 0; ch < priv->num_channels; ch++)
|
|
|
|
flush_channel(dev, ch, -EIO, 1);
|
|
|
|
|
|
|
|
/* reset and reinitialize the device */
|
|
|
|
init_device(dev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
#define DEF_TALITOS1_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
|
|
|
|
static irqreturn_t talitos1_interrupt_##name(int irq, void *data) \
|
|
|
|
{ \
|
|
|
|
struct device *dev = data; \
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev); \
|
|
|
|
u32 isr, isr_lo; \
|
|
|
|
unsigned long flags; \
|
|
|
|
\
|
|
|
|
spin_lock_irqsave(&priv->reg_lock, flags); \
|
|
|
|
isr = in_be32(priv->reg + TALITOS_ISR); \
|
|
|
|
isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
|
|
|
|
/* Acknowledge interrupt */ \
|
|
|
|
out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
|
|
|
|
out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
|
|
|
|
\
|
|
|
|
if (unlikely(isr & ch_err_mask || isr_lo & TALITOS1_IMR_LO_INIT)) { \
|
|
|
|
spin_unlock_irqrestore(&priv->reg_lock, flags); \
|
|
|
|
talitos_error(dev, isr & ch_err_mask, isr_lo); \
|
|
|
|
} \
|
|
|
|
else { \
|
|
|
|
if (likely(isr & ch_done_mask)) { \
|
|
|
|
/* mask further done interrupts. */ \
|
|
|
|
setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
|
|
|
|
/* done_task will unmask done interrupts at exit */ \
|
|
|
|
tasklet_schedule(&priv->done_task[tlet]); \
|
|
|
|
} \
|
|
|
|
spin_unlock_irqrestore(&priv->reg_lock, flags); \
|
|
|
|
} \
|
|
|
|
\
|
|
|
|
return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
|
|
|
|
IRQ_NONE; \
|
|
|
|
}
|
|
|
|
|
|
|
|
DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)
|
|
|
|
|
|
|
|
#define DEF_TALITOS2_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
|
|
|
|
static irqreturn_t talitos2_interrupt_##name(int irq, void *data) \
|
2011-11-21 01:13:27 -07:00
|
|
|
{ \
|
|
|
|
struct device *dev = data; \
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev); \
|
|
|
|
u32 isr, isr_lo; \
|
2012-03-30 08:49:53 -06:00
|
|
|
unsigned long flags; \
|
2011-11-21 01:13:27 -07:00
|
|
|
\
|
2012-03-30 08:49:53 -06:00
|
|
|
spin_lock_irqsave(&priv->reg_lock, flags); \
|
2011-11-21 01:13:27 -07:00
|
|
|
isr = in_be32(priv->reg + TALITOS_ISR); \
|
|
|
|
isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
|
|
|
|
/* Acknowledge interrupt */ \
|
|
|
|
out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
|
|
|
|
out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
|
|
|
|
\
|
2012-03-30 08:49:53 -06:00
|
|
|
if (unlikely(isr & ch_err_mask || isr_lo)) { \
|
|
|
|
spin_unlock_irqrestore(&priv->reg_lock, flags); \
|
|
|
|
talitos_error(dev, isr & ch_err_mask, isr_lo); \
|
|
|
|
} \
|
|
|
|
else { \
|
2011-11-21 01:13:27 -07:00
|
|
|
if (likely(isr & ch_done_mask)) { \
|
|
|
|
/* mask further done interrupts. */ \
|
|
|
|
clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
|
|
|
|
/* done_task will unmask done interrupts at exit */ \
|
|
|
|
tasklet_schedule(&priv->done_task[tlet]); \
|
|
|
|
} \
|
2012-03-30 08:49:53 -06:00
|
|
|
spin_unlock_irqrestore(&priv->reg_lock, flags); \
|
|
|
|
} \
|
2011-11-21 01:13:27 -07:00
|
|
|
\
|
|
|
|
return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
|
|
|
|
IRQ_NONE; \
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
|
|
|
|
DEF_TALITOS2_INTERRUPT(4ch, TALITOS2_ISR_4CHDONE, TALITOS2_ISR_4CHERR, 0)
|
|
|
|
DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
|
|
|
|
0)
|
|
|
|
DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
|
|
|
|
1)
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* hwrng
|
|
|
|
*/
|
|
|
|
static int talitos_rng_data_present(struct hwrng *rng, int wait)
|
|
|
|
{
|
|
|
|
struct device *dev = (struct device *)rng->priv;
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
u32 ofl;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 20; i++) {
|
2015-04-17 08:32:11 -06:00
|
|
|
ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
|
2008-06-23 05:50:15 -06:00
|
|
|
TALITOS_RNGUSR_LO_OFL;
|
|
|
|
if (ofl || !wait)
|
|
|
|
break;
|
|
|
|
udelay(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
return !!ofl;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
|
|
|
|
{
|
|
|
|
struct device *dev = (struct device *)rng->priv;
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
/* rng fifo requires 64-bit accesses */
|
2015-04-17 08:32:11 -06:00
|
|
|
*data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
|
|
|
|
*data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
return sizeof(u32);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int talitos_rng_init(struct hwrng *rng)
|
|
|
|
{
|
|
|
|
struct device *dev = (struct device *)rng->priv;
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
unsigned int timeout = TALITOS_TIMEOUT;
|
|
|
|
|
2015-04-17 08:32:11 -06:00
|
|
|
setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
|
|
|
|
while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
|
|
|
|
& TALITOS_RNGUSR_LO_RD)
|
2008-06-23 05:50:15 -06:00
|
|
|
&& --timeout)
|
|
|
|
cpu_relax();
|
|
|
|
if (timeout == 0) {
|
|
|
|
dev_err(dev, "failed to reset rng hw\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* start generating */
|
2015-04-17 08:32:11 -06:00
|
|
|
setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int talitos_register_rng(struct device *dev)
|
|
|
|
{
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
2015-08-05 15:52:08 -06:00
|
|
|
int err;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
priv->rng.name = dev_driver_string(dev),
|
|
|
|
priv->rng.init = talitos_rng_init,
|
|
|
|
priv->rng.data_present = talitos_rng_data_present,
|
|
|
|
priv->rng.data_read = talitos_rng_data_read,
|
|
|
|
priv->rng.priv = (unsigned long)dev;
|
|
|
|
|
2015-08-05 15:52:08 -06:00
|
|
|
err = hwrng_register(&priv->rng);
|
|
|
|
if (!err)
|
|
|
|
priv->rng_registered = true;
|
|
|
|
|
|
|
|
return err;
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void talitos_unregister_rng(struct device *dev)
|
|
|
|
{
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
|
2015-08-05 15:52:08 -06:00
|
|
|
if (!priv->rng_registered)
|
|
|
|
return;
|
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
hwrng_unregister(&priv->rng);
|
2015-08-05 15:52:08 -06:00
|
|
|
priv->rng_registered = false;
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* crypto alg
|
|
|
|
*/
|
|
|
|
#define TALITOS_CRA_PRIORITY 3000
|
2012-07-03 10:16:53 -06:00
|
|
|
#define TALITOS_MAX_KEY_SIZE 96
|
2008-07-10 04:29:18 -06:00
|
|
|
#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
|
2008-07-03 05:08:46 -06:00
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
struct talitos_ctx {
|
|
|
|
struct device *dev;
|
2011-07-14 21:21:38 -06:00
|
|
|
int ch;
|
2008-06-23 05:50:15 -06:00
|
|
|
__be32 desc_hdr_template;
|
|
|
|
u8 key[TALITOS_MAX_KEY_SIZE];
|
2008-07-03 05:08:46 -06:00
|
|
|
u8 iv[TALITOS_MAX_IV_LENGTH];
|
2008-06-23 05:50:15 -06:00
|
|
|
unsigned int keylen;
|
|
|
|
unsigned int enckeylen;
|
|
|
|
unsigned int authkeylen;
|
|
|
|
};
|
|
|
|
|
2010-05-19 03:20:36 -06:00
|
|
|
#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
|
|
|
|
#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
|
|
|
|
|
|
|
|
struct talitos_ahash_req_ctx {
|
2010-05-19 03:21:53 -06:00
|
|
|
u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
|
2010-05-19 03:20:36 -06:00
|
|
|
unsigned int hw_context_size;
|
|
|
|
u8 buf[HASH_MAX_BLOCK_SIZE];
|
|
|
|
u8 bufnext[HASH_MAX_BLOCK_SIZE];
|
2010-05-19 03:21:53 -06:00
|
|
|
unsigned int swinit;
|
2010-05-19 03:20:36 -06:00
|
|
|
unsigned int first;
|
|
|
|
unsigned int last;
|
|
|
|
unsigned int to_hash_later;
|
2015-05-11 11:04:56 -06:00
|
|
|
unsigned int nbuf;
|
2010-05-19 03:20:36 -06:00
|
|
|
struct scatterlist bufsl[2];
|
|
|
|
struct scatterlist *psrc;
|
|
|
|
};
|
|
|
|
|
2009-03-29 01:50:50 -06:00
|
|
|
static int aead_setkey(struct crypto_aead *authenc,
|
|
|
|
const u8 *key, unsigned int keylen)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
|
2013-10-15 05:49:34 -06:00
|
|
|
struct crypto_authenc_keys keys;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2013-10-15 05:49:34 -06:00
|
|
|
if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
|
2008-06-23 05:50:15 -06:00
|
|
|
goto badkey;
|
|
|
|
|
2013-10-15 05:49:34 -06:00
|
|
|
if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
|
2008-06-23 05:50:15 -06:00
|
|
|
goto badkey;
|
|
|
|
|
2013-10-15 05:49:34 -06:00
|
|
|
memcpy(ctx->key, keys.authkey, keys.authkeylen);
|
|
|
|
memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2013-10-15 05:49:34 -06:00
|
|
|
ctx->keylen = keys.authkeylen + keys.enckeylen;
|
|
|
|
ctx->enckeylen = keys.enckeylen;
|
|
|
|
ctx->authkeylen = keys.authkeylen;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
badkey:
|
|
|
|
crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2009-03-29 01:50:50 -06:00
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|
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* talitos_edesc - s/w-extended descriptor
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2008-06-23 05:50:15 -06:00
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|
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* @src_nents: number of segments in input scatterlist
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* @dst_nents: number of segments in output scatterlist
|
2012-08-02 08:16:39 -06:00
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* @src_chained: whether src is chained or not
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* @dst_chained: whether dst is chained or not
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2015-07-30 03:53:22 -06:00
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* @icv_ool: whether ICV is out-of-line
|
2012-08-02 08:16:40 -06:00
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* @iv_dma: dma address of iv for checking continuity and link table
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2008-06-23 05:50:15 -06:00
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* @dma_len: length of dma mapped link_tbl space
|
2015-04-17 08:32:15 -06:00
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* @dma_link_tbl: bus physical address of link_tbl/buf
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2008-06-23 05:50:15 -06:00
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* @desc: h/w descriptor
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2015-04-17 08:32:15 -06:00
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* @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
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* @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
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2008-06-23 05:50:15 -06:00
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*
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* if decrypting (with authcheck), or either one of src_nents or dst_nents
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* is greater than 1, an integrity check value is concatenated to the end
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* of link_tbl data
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*/
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2009-03-29 01:50:50 -06:00
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struct talitos_edesc {
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2008-06-23 05:50:15 -06:00
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int src_nents;
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int dst_nents;
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2012-08-02 08:16:39 -06:00
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bool src_chained;
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bool dst_chained;
|
2015-07-30 03:53:22 -06:00
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bool icv_ool;
|
2012-08-02 08:16:40 -06:00
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dma_addr_t iv_dma;
|
2008-06-23 05:50:15 -06:00
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int dma_len;
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dma_addr_t dma_link_tbl;
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struct talitos_desc desc;
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2015-04-17 08:32:15 -06:00
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union {
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struct talitos_ptr link_tbl[0];
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u8 buf[0];
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};
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2008-06-23 05:50:15 -06:00
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};
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2009-03-29 01:52:32 -06:00
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static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
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unsigned int nents, enum dma_data_direction dir,
|
2012-08-02 08:16:39 -06:00
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bool chained)
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2009-03-29 01:52:32 -06:00
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{
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if (unlikely(chained))
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while (sg) {
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dma_map_sg(dev, sg, 1, dir);
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2015-01-20 01:06:16 -07:00
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sg = sg_next(sg);
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2009-03-29 01:52:32 -06:00
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}
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else
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dma_map_sg(dev, sg, nents, dir);
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return nents;
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}
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static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
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enum dma_data_direction dir)
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{
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while (sg) {
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dma_unmap_sg(dev, sg, 1, dir);
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2015-01-20 01:06:16 -07:00
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sg = sg_next(sg);
|
2009-03-29 01:52:32 -06:00
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}
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}
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static void talitos_sg_unmap(struct device *dev,
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struct talitos_edesc *edesc,
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struct scatterlist *src,
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struct scatterlist *dst)
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{
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unsigned int src_nents = edesc->src_nents ? : 1;
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unsigned int dst_nents = edesc->dst_nents ? : 1;
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if (src != dst) {
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2012-08-02 08:16:39 -06:00
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if (edesc->src_chained)
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2009-03-29 01:52:32 -06:00
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talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
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else
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dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
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2010-05-19 03:20:36 -06:00
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if (dst) {
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2012-08-02 08:16:39 -06:00
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if (edesc->dst_chained)
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2010-05-19 03:20:36 -06:00
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talitos_unmap_sg_chain(dev, dst,
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DMA_FROM_DEVICE);
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else
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dma_unmap_sg(dev, dst, dst_nents,
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DMA_FROM_DEVICE);
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}
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2009-03-29 01:52:32 -06:00
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} else
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2012-08-02 08:16:39 -06:00
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if (edesc->src_chained)
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2009-03-29 01:52:32 -06:00
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talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
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else
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dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
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}
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|
2008-06-23 05:50:15 -06:00
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static void ipsec_esp_unmap(struct device *dev,
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2009-03-29 01:50:50 -06:00
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struct talitos_edesc *edesc,
|
2008-06-23 05:50:15 -06:00
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struct aead_request *areq)
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{
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unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
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unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
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unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
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unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
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2009-03-29 01:52:32 -06:00
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talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
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2008-06-23 05:50:15 -06:00
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if (edesc->dma_len)
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dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
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DMA_BIDIRECTIONAL);
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}
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/*
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* ipsec_esp descriptor callbacks
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*/
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static void ipsec_esp_encrypt_done(struct device *dev,
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struct talitos_desc *desc, void *context,
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int err)
|
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{
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struct aead_request *areq = context;
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struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
|
2015-07-30 03:53:22 -06:00
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unsigned int authsize = crypto_aead_authsize(authenc);
|
2009-03-29 01:53:59 -06:00
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struct talitos_edesc *edesc;
|
2008-06-23 05:50:15 -06:00
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struct scatterlist *sg;
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void *icvdata;
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2009-03-29 01:53:59 -06:00
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edesc = container_of(desc, struct talitos_edesc, desc);
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|
2008-06-23 05:50:15 -06:00
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ipsec_esp_unmap(dev, edesc, areq);
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/* copy the generated ICV to dst */
|
2015-07-30 03:53:22 -06:00
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if (edesc->icv_ool) {
|
2008-06-23 05:50:15 -06:00
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icvdata = &edesc->link_tbl[edesc->src_nents +
|
2015-07-30 03:53:22 -06:00
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edesc->dst_nents + 2];
|
2008-06-23 05:50:15 -06:00
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sg = sg_last(areq->dst, edesc->dst_nents);
|
2015-07-30 03:53:22 -06:00
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memcpy((char *)sg_virt(sg) + sg->length - authsize,
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icvdata, authsize);
|
2008-06-23 05:50:15 -06:00
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}
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kfree(edesc);
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aead_request_complete(areq, err);
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}
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|
2008-10-12 06:33:14 -06:00
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static void ipsec_esp_decrypt_swauth_done(struct device *dev,
|
2009-03-29 01:53:23 -06:00
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struct talitos_desc *desc,
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void *context, int err)
|
2008-06-23 05:50:15 -06:00
|
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{
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struct aead_request *req = context;
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struct crypto_aead *authenc = crypto_aead_reqtfm(req);
|
2015-07-30 03:53:22 -06:00
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unsigned int authsize = crypto_aead_authsize(authenc);
|
2009-03-29 01:53:59 -06:00
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struct talitos_edesc *edesc;
|
2008-06-23 05:50:15 -06:00
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struct scatterlist *sg;
|
2015-07-30 03:53:22 -06:00
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char *oicv, *icv;
|
2008-06-23 05:50:15 -06:00
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2009-03-29 01:53:59 -06:00
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edesc = container_of(desc, struct talitos_edesc, desc);
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|
2008-06-23 05:50:15 -06:00
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ipsec_esp_unmap(dev, edesc, req);
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if (!err) {
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/* auth check */
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sg = sg_last(req->dst, edesc->dst_nents ? : 1);
|
2015-07-30 03:53:22 -06:00
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icv = (char *)sg_virt(sg) + sg->length - authsize;
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if (edesc->dma_len) {
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oicv = (char *)&edesc->link_tbl[edesc->src_nents +
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edesc->dst_nents + 2];
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if (edesc->icv_ool)
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icv = oicv + authsize;
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} else
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oicv = (char *)&edesc->link_tbl[0];
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err = memcmp(oicv, icv, authsize) ? -EBADMSG : 0;
|
2008-06-23 05:50:15 -06:00
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}
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kfree(edesc);
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aead_request_complete(req, err);
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}
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|
2008-10-12 06:33:14 -06:00
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static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
|
2009-03-29 01:53:23 -06:00
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struct talitos_desc *desc,
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void *context, int err)
|
2008-10-12 06:33:14 -06:00
|
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{
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|
struct aead_request *req = context;
|
2009-03-29 01:53:59 -06:00
|
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struct talitos_edesc *edesc;
|
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edesc = container_of(desc, struct talitos_edesc, desc);
|
2008-10-12 06:33:14 -06:00
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ipsec_esp_unmap(dev, edesc, req);
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/* check ICV auth status */
|
2009-03-29 01:53:23 -06:00
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if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
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DESC_HDR_LO_ICCR1_PASS))
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err = -EBADMSG;
|
2008-10-12 06:33:14 -06:00
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kfree(edesc);
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aead_request_complete(req, err);
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}
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|
2008-06-23 05:50:15 -06:00
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/*
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* convert scatterlist to SEC h/w link table format
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* stop at cryptlen bytes
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*/
|
2015-07-30 03:53:22 -06:00
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static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
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unsigned int offset, int cryptlen,
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struct talitos_ptr *link_tbl_ptr)
|
2008-06-23 05:50:15 -06:00
|
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{
|
2008-07-03 05:08:46 -06:00
|
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int n_sg = sg_count;
|
2015-07-30 03:53:22 -06:00
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int count = 0;
|
2008-07-03 05:08:46 -06:00
|
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|
2015-07-30 03:53:22 -06:00
|
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while (cryptlen && sg && n_sg--) {
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unsigned int len = sg_dma_len(sg);
|
2008-06-23 05:50:15 -06:00
|
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|
2015-07-30 03:53:22 -06:00
|
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if (offset >= len) {
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offset -= len;
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goto next;
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}
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len -= offset;
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if (len > cryptlen)
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len = cryptlen;
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to_talitos_ptr(link_tbl_ptr + count,
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sg_dma_address(sg) + offset, 0);
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link_tbl_ptr[count].len = cpu_to_be16(len);
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link_tbl_ptr[count].j_extent = 0;
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count++;
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cryptlen -= len;
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offset = 0;
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next:
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sg = sg_next(sg);
|
2008-07-03 05:08:46 -06:00
|
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|
}
|
2008-06-23 05:50:15 -06:00
|
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|
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/* tag end of link table */
|
2015-07-30 03:53:22 -06:00
|
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if (count > 0)
|
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link_tbl_ptr[count - 1].j_extent = DESC_PTR_LNKTBL_RETURN;
|
2008-07-03 05:08:46 -06:00
|
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|
|
2015-07-30 03:53:22 -06:00
|
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|
return count;
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|
|
}
|
|
|
|
|
|
|
|
static inline int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
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|
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int cryptlen,
|
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|
|
struct talitos_ptr *link_tbl_ptr)
|
|
|
|
{
|
|
|
|
return sg_to_link_tbl_offset(sg, sg_count, 0, cryptlen,
|
|
|
|
link_tbl_ptr);
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* fill in and submit ipsec_esp descriptor
|
|
|
|
*/
|
2009-03-29 01:50:50 -06:00
|
|
|
static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
|
2015-07-30 03:53:22 -06:00
|
|
|
void (*callback)(struct device *dev,
|
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|
|
struct talitos_desc *desc,
|
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void *context, int error))
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct crypto_aead *aead = crypto_aead_reqtfm(areq);
|
2015-07-30 03:53:22 -06:00
|
|
|
unsigned int authsize = crypto_aead_authsize(aead);
|
2008-06-23 05:50:15 -06:00
|
|
|
struct talitos_ctx *ctx = crypto_aead_ctx(aead);
|
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|
|
struct device *dev = ctx->dev;
|
|
|
|
struct talitos_desc *desc = &edesc->desc;
|
|
|
|
unsigned int cryptlen = areq->cryptlen;
|
2009-08-12 19:49:06 -06:00
|
|
|
unsigned int ivsize = crypto_aead_ivsize(aead);
|
2015-07-30 03:53:22 -06:00
|
|
|
int tbl_off = 0;
|
2008-07-17 06:20:06 -06:00
|
|
|
int sg_count, ret;
|
2008-10-12 06:33:14 -06:00
|
|
|
int sg_link_tbl_len;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* hmac key */
|
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
|
2015-04-17 08:31:57 -06:00
|
|
|
DMA_TO_DEVICE);
|
2012-08-02 08:16:40 -06:00
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ?: 1,
|
|
|
|
(areq->src == areq->dst) ? DMA_BIDIRECTIONAL
|
|
|
|
: DMA_TO_DEVICE,
|
|
|
|
edesc->src_chained);
|
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
/* hmac data */
|
2015-07-30 03:53:22 -06:00
|
|
|
desc->ptr[1].len = cpu_to_be16(areq->assoclen);
|
|
|
|
if (sg_count > 1 &&
|
|
|
|
(ret = sg_to_link_tbl_offset(areq->src, sg_count, 0,
|
|
|
|
areq->assoclen,
|
|
|
|
&edesc->link_tbl[tbl_off])) > 1) {
|
|
|
|
tbl_off += ret;
|
2012-08-02 08:16:40 -06:00
|
|
|
|
|
|
|
to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
|
2015-04-17 08:32:07 -06:00
|
|
|
sizeof(struct talitos_ptr), 0);
|
2012-08-02 08:16:40 -06:00
|
|
|
desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
|
|
|
|
|
|
|
|
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
|
|
|
|
edesc->dma_len, DMA_BIDIRECTIONAL);
|
|
|
|
} else {
|
2015-07-30 03:53:22 -06:00
|
|
|
to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->src), 0);
|
2012-08-02 08:16:40 -06:00
|
|
|
desc->ptr[1].j_extent = 0;
|
|
|
|
}
|
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
/* cipher iv */
|
2015-04-17 08:32:07 -06:00
|
|
|
to_talitos_ptr(&desc->ptr[2], edesc->iv_dma, 0);
|
2012-08-02 08:16:40 -06:00
|
|
|
desc->ptr[2].len = cpu_to_be16(ivsize);
|
|
|
|
desc->ptr[2].j_extent = 0;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* cipher key */
|
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
|
2015-04-17 08:31:57 -06:00
|
|
|
(char *)&ctx->key + ctx->authkeylen,
|
2008-06-23 05:50:15 -06:00
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* cipher in
|
|
|
|
* map and adjust cipher len to aead request cryptlen.
|
|
|
|
* extent is bytes of HMAC postpended to ciphertext,
|
|
|
|
* typically 12 for ipsec
|
|
|
|
*/
|
|
|
|
desc->ptr[4].len = cpu_to_be16(cryptlen);
|
|
|
|
desc->ptr[4].j_extent = authsize;
|
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
sg_link_tbl_len = cryptlen;
|
|
|
|
if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
|
|
|
|
sg_link_tbl_len += authsize;
|
|
|
|
|
|
|
|
if (sg_count > 1 &&
|
|
|
|
(ret = sg_to_link_tbl_offset(areq->src, sg_count, areq->assoclen,
|
|
|
|
sg_link_tbl_len,
|
|
|
|
&edesc->link_tbl[tbl_off])) > 1) {
|
|
|
|
tbl_off += ret;
|
|
|
|
desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
|
|
|
|
to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
|
|
|
|
tbl_off *
|
|
|
|
sizeof(struct talitos_ptr), 0);
|
|
|
|
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
|
|
|
|
edesc->dma_len,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
} else
|
2015-04-17 08:32:07 -06:00
|
|
|
to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src), 0);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* cipher out */
|
|
|
|
desc->ptr[5].len = cpu_to_be16(cryptlen);
|
|
|
|
desc->ptr[5].j_extent = authsize;
|
|
|
|
|
2009-03-29 01:53:23 -06:00
|
|
|
if (areq->src != areq->dst)
|
2009-03-29 01:52:32 -06:00
|
|
|
sg_count = talitos_map_sg(dev, areq->dst,
|
|
|
|
edesc->dst_nents ? : 1,
|
2012-08-02 08:16:39 -06:00
|
|
|
DMA_FROM_DEVICE, edesc->dst_chained);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
edesc->icv_ool = false;
|
|
|
|
|
|
|
|
if (sg_count > 1 &&
|
|
|
|
(sg_count = sg_to_link_tbl_offset(areq->dst, sg_count,
|
|
|
|
areq->assoclen, cryptlen,
|
|
|
|
&edesc->link_tbl[tbl_off])) >
|
|
|
|
1) {
|
2012-08-02 08:16:40 -06:00
|
|
|
struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2009-08-12 19:51:51 -06:00
|
|
|
to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
|
2015-04-17 08:32:07 -06:00
|
|
|
tbl_off * sizeof(struct talitos_ptr), 0);
|
2008-10-12 06:33:14 -06:00
|
|
|
|
2008-07-30 02:26:57 -06:00
|
|
|
/* Add an entry to the link table for ICV data */
|
2012-08-02 08:16:40 -06:00
|
|
|
tbl_ptr += sg_count - 1;
|
|
|
|
tbl_ptr->j_extent = 0;
|
|
|
|
tbl_ptr++;
|
|
|
|
tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
|
|
|
|
tbl_ptr->len = cpu_to_be16(authsize);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* icv data follows link tables */
|
2012-08-02 08:16:40 -06:00
|
|
|
to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
|
2015-07-30 03:53:22 -06:00
|
|
|
(edesc->src_nents + edesc->dst_nents +
|
|
|
|
2) * sizeof(struct talitos_ptr) +
|
|
|
|
authsize, 0);
|
2008-06-23 05:50:15 -06:00
|
|
|
desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
|
|
|
|
dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
|
|
|
|
edesc->dma_len, DMA_BIDIRECTIONAL);
|
2015-07-30 03:53:22 -06:00
|
|
|
|
|
|
|
edesc->icv_ool = true;
|
|
|
|
} else
|
|
|
|
to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst), 0);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* iv out */
|
2015-04-17 08:31:57 -06:00
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
|
2008-06-23 05:50:15 -06:00
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
2011-07-14 21:21:38 -06:00
|
|
|
ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
|
2008-07-17 06:20:06 -06:00
|
|
|
if (ret != -EINPROGRESS) {
|
|
|
|
ipsec_esp_unmap(dev, edesc, areq);
|
|
|
|
kfree(edesc);
|
|
|
|
}
|
|
|
|
return ret;
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* derive number of elements in scatterlist
|
|
|
|
*/
|
2012-08-02 08:16:39 -06:00
|
|
|
static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct scatterlist *sg = sg_list;
|
|
|
|
int sg_nents = 0;
|
|
|
|
|
2012-08-02 08:16:39 -06:00
|
|
|
*chained = false;
|
2015-05-12 02:28:05 -06:00
|
|
|
while (nbytes > 0 && sg) {
|
2008-06-23 05:50:15 -06:00
|
|
|
sg_nents++;
|
|
|
|
nbytes -= sg->length;
|
2009-03-29 01:52:32 -06:00
|
|
|
if (!sg_is_last(sg) && (sg + 1)->length == 0)
|
2012-08-02 08:16:39 -06:00
|
|
|
*chained = true;
|
2015-01-20 01:06:16 -07:00
|
|
|
sg = sg_next(sg);
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return sg_nents;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2009-03-29 01:50:50 -06:00
|
|
|
* allocate and map the extended descriptor
|
2008-06-23 05:50:15 -06:00
|
|
|
*/
|
2009-03-29 01:52:32 -06:00
|
|
|
static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
|
|
|
|
struct scatterlist *src,
|
|
|
|
struct scatterlist *dst,
|
2012-08-02 08:16:40 -06:00
|
|
|
u8 *iv,
|
|
|
|
unsigned int assoclen,
|
2009-03-29 01:52:32 -06:00
|
|
|
unsigned int cryptlen,
|
|
|
|
unsigned int authsize,
|
2012-08-02 08:16:40 -06:00
|
|
|
unsigned int ivsize,
|
2009-03-29 01:52:32 -06:00
|
|
|
int icv_stashing,
|
2013-11-28 06:11:17 -07:00
|
|
|
u32 cryptoflags,
|
|
|
|
bool encrypt)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
2009-03-29 01:50:50 -06:00
|
|
|
struct talitos_edesc *edesc;
|
2015-07-30 03:53:22 -06:00
|
|
|
int src_nents, dst_nents, alloc_len, dma_len;
|
|
|
|
bool src_chained = false, dst_chained = false;
|
2012-08-02 08:16:40 -06:00
|
|
|
dma_addr_t iv_dma = 0;
|
2009-03-29 01:52:32 -06:00
|
|
|
gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
|
2008-07-17 06:19:18 -06:00
|
|
|
GFP_ATOMIC;
|
2015-04-17 08:32:15 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
|
|
|
int max_len = is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2015-04-17 08:32:15 -06:00
|
|
|
if (cryptlen + authsize > max_len) {
|
2009-03-29 01:52:32 -06:00
|
|
|
dev_err(dev, "length exceeds h/w max limit\n");
|
2008-06-23 05:50:15 -06:00
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
2013-11-19 05:57:49 -07:00
|
|
|
if (ivsize)
|
2012-08-02 08:16:40 -06:00
|
|
|
iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
|
|
|
|
|
2013-11-28 06:11:17 -07:00
|
|
|
if (!dst || dst == src) {
|
2015-07-30 03:53:22 -06:00
|
|
|
src_nents = sg_count(src, assoclen + cryptlen + authsize,
|
|
|
|
&src_chained);
|
2013-11-28 06:11:17 -07:00
|
|
|
src_nents = (src_nents == 1) ? 0 : src_nents;
|
|
|
|
dst_nents = dst ? src_nents : 0;
|
|
|
|
} else { /* dst && dst != src*/
|
2015-07-30 03:53:22 -06:00
|
|
|
src_nents = sg_count(src, assoclen + cryptlen +
|
|
|
|
(encrypt ? 0 : authsize),
|
2013-11-28 06:11:17 -07:00
|
|
|
&src_chained);
|
|
|
|
src_nents = (src_nents == 1) ? 0 : src_nents;
|
2015-07-30 03:53:22 -06:00
|
|
|
dst_nents = sg_count(dst, assoclen + cryptlen +
|
|
|
|
(encrypt ? authsize : 0),
|
2013-11-28 06:11:17 -07:00
|
|
|
&dst_chained);
|
|
|
|
dst_nents = (dst_nents == 1) ? 0 : dst_nents;
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* allocate space for base edesc plus the link tables,
|
2015-07-30 03:53:22 -06:00
|
|
|
* allowing for two separate entries for AD and generated ICV (+ 2),
|
|
|
|
* and space for two sets of ICVs (stashed and generated)
|
2008-06-23 05:50:15 -06:00
|
|
|
*/
|
2009-03-29 01:50:50 -06:00
|
|
|
alloc_len = sizeof(struct talitos_edesc);
|
2015-07-30 03:53:22 -06:00
|
|
|
if (src_nents || dst_nents) {
|
2015-04-17 08:32:15 -06:00
|
|
|
if (is_sec1)
|
2015-05-11 04:10:09 -06:00
|
|
|
dma_len = (src_nents ? cryptlen : 0) +
|
|
|
|
(dst_nents ? cryptlen : 0);
|
2015-04-17 08:32:15 -06:00
|
|
|
else
|
2015-07-30 03:53:22 -06:00
|
|
|
dma_len = (src_nents + dst_nents + 2) *
|
|
|
|
sizeof(struct talitos_ptr) + authsize * 2;
|
2008-06-23 05:50:15 -06:00
|
|
|
alloc_len += dma_len;
|
|
|
|
} else {
|
|
|
|
dma_len = 0;
|
2009-03-29 01:52:32 -06:00
|
|
|
alloc_len += icv_stashing ? authsize : 0;
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
2008-07-17 06:19:18 -06:00
|
|
|
edesc = kmalloc(alloc_len, GFP_DMA | flags);
|
2008-06-23 05:50:15 -06:00
|
|
|
if (!edesc) {
|
2012-08-02 08:16:40 -06:00
|
|
|
if (iv_dma)
|
|
|
|
dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
|
2013-11-19 05:57:49 -07:00
|
|
|
|
2009-03-29 01:52:32 -06:00
|
|
|
dev_err(dev, "could not allocate edescriptor\n");
|
2008-06-23 05:50:15 -06:00
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
edesc->src_nents = src_nents;
|
|
|
|
edesc->dst_nents = dst_nents;
|
2012-08-02 08:16:39 -06:00
|
|
|
edesc->src_chained = src_chained;
|
|
|
|
edesc->dst_chained = dst_chained;
|
2012-08-02 08:16:40 -06:00
|
|
|
edesc->iv_dma = iv_dma;
|
2008-06-23 05:50:15 -06:00
|
|
|
edesc->dma_len = dma_len;
|
2010-05-19 03:20:36 -06:00
|
|
|
if (dma_len)
|
|
|
|
edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
|
|
|
|
edesc->dma_len,
|
|
|
|
DMA_BIDIRECTIONAL);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
return edesc;
|
|
|
|
}
|
|
|
|
|
2012-08-02 08:16:40 -06:00
|
|
|
static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
|
2013-11-28 06:11:17 -07:00
|
|
|
int icv_stashing, bool encrypt)
|
2009-03-29 01:52:32 -06:00
|
|
|
{
|
|
|
|
struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
|
2015-07-30 03:53:22 -06:00
|
|
|
unsigned int authsize = crypto_aead_authsize(authenc);
|
2009-03-29 01:52:32 -06:00
|
|
|
struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
|
2012-08-02 08:16:40 -06:00
|
|
|
unsigned int ivsize = crypto_aead_ivsize(authenc);
|
2009-03-29 01:52:32 -06:00
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
|
2012-08-02 08:16:40 -06:00
|
|
|
iv, areq->assoclen, areq->cryptlen,
|
2015-07-30 03:53:22 -06:00
|
|
|
authsize, ivsize, icv_stashing,
|
2013-11-28 06:11:17 -07:00
|
|
|
areq->base.flags, encrypt);
|
2009-03-29 01:52:32 -06:00
|
|
|
}
|
|
|
|
|
2009-03-29 01:50:50 -06:00
|
|
|
static int aead_encrypt(struct aead_request *req)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct crypto_aead *authenc = crypto_aead_reqtfm(req);
|
|
|
|
struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
|
2009-03-29 01:50:50 -06:00
|
|
|
struct talitos_edesc *edesc;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
/* allocate extended descriptor */
|
2013-11-28 06:11:17 -07:00
|
|
|
edesc = aead_edesc_alloc(req, req->iv, 0, true);
|
2008-06-23 05:50:15 -06:00
|
|
|
if (IS_ERR(edesc))
|
|
|
|
return PTR_ERR(edesc);
|
|
|
|
|
|
|
|
/* set encrypt */
|
2008-07-03 05:08:46 -06:00
|
|
|
edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
return ipsec_esp(edesc, req, ipsec_esp_encrypt_done);
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
2009-03-29 01:50:50 -06:00
|
|
|
static int aead_decrypt(struct aead_request *req)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct crypto_aead *authenc = crypto_aead_reqtfm(req);
|
2015-07-30 03:53:22 -06:00
|
|
|
unsigned int authsize = crypto_aead_authsize(authenc);
|
2008-06-23 05:50:15 -06:00
|
|
|
struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
|
2008-10-12 06:33:14 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(ctx->dev);
|
2009-03-29 01:50:50 -06:00
|
|
|
struct talitos_edesc *edesc;
|
2008-06-23 05:50:15 -06:00
|
|
|
struct scatterlist *sg;
|
|
|
|
void *icvdata;
|
|
|
|
|
|
|
|
req->cryptlen -= authsize;
|
|
|
|
|
|
|
|
/* allocate extended descriptor */
|
2013-11-28 06:11:17 -07:00
|
|
|
edesc = aead_edesc_alloc(req, req->iv, 1, false);
|
2008-06-23 05:50:15 -06:00
|
|
|
if (IS_ERR(edesc))
|
|
|
|
return PTR_ERR(edesc);
|
|
|
|
|
2008-10-12 06:33:14 -06:00
|
|
|
if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
|
2009-03-29 01:53:23 -06:00
|
|
|
((!edesc->src_nents && !edesc->dst_nents) ||
|
|
|
|
priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2008-10-12 06:33:14 -06:00
|
|
|
/* decrypt and check the ICV */
|
2009-03-29 01:53:23 -06:00
|
|
|
edesc->desc.hdr = ctx->desc_hdr_template |
|
|
|
|
DESC_HDR_DIR_INBOUND |
|
2008-10-12 06:33:14 -06:00
|
|
|
DESC_HDR_MODE1_MDEU_CICV;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2008-10-12 06:33:14 -06:00
|
|
|
/* reset integrity check result bits */
|
|
|
|
edesc->desc.hdr_lo = 0;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
return ipsec_esp(edesc, req, ipsec_esp_decrypt_hwauth_done);
|
2009-03-29 01:53:23 -06:00
|
|
|
}
|
2008-10-12 06:33:14 -06:00
|
|
|
|
2009-03-29 01:53:23 -06:00
|
|
|
/* Have to check the ICV with software */
|
|
|
|
edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
|
2008-10-12 06:33:14 -06:00
|
|
|
|
2009-03-29 01:53:23 -06:00
|
|
|
/* stash incoming ICV for later cmp with ICV generated by the h/w */
|
|
|
|
if (edesc->dma_len)
|
2015-07-30 03:53:22 -06:00
|
|
|
icvdata = (char *)&edesc->link_tbl[edesc->src_nents +
|
|
|
|
edesc->dst_nents + 2];
|
2009-03-29 01:53:23 -06:00
|
|
|
else
|
|
|
|
icvdata = &edesc->link_tbl[0];
|
2008-10-12 06:33:14 -06:00
|
|
|
|
2009-03-29 01:53:23 -06:00
|
|
|
sg = sg_last(req->src, edesc->src_nents ? : 1);
|
2008-10-12 06:33:14 -06:00
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
memcpy(icvdata, (char *)sg_virt(sg) + sg->length - authsize, authsize);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
return ipsec_esp(edesc, req, ipsec_esp_decrypt_swauth_done);
|
2008-06-23 05:50:15 -06:00
|
|
|
}
|
|
|
|
|
2009-03-29 01:52:32 -06:00
|
|
|
static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
|
|
|
|
const u8 *key, unsigned int keylen)
|
|
|
|
{
|
|
|
|
struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
|
|
|
|
|
|
|
|
memcpy(&ctx->key, key, keylen);
|
|
|
|
ctx->keylen = keylen;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-17 08:31:51 -06:00
|
|
|
static void unmap_sg_talitos_ptr(struct device *dev, struct scatterlist *src,
|
|
|
|
struct scatterlist *dst, unsigned int len,
|
|
|
|
struct talitos_edesc *edesc)
|
|
|
|
{
|
2015-04-17 08:32:15 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
|
|
|
|
|
|
|
if (is_sec1) {
|
|
|
|
if (!edesc->src_nents) {
|
|
|
|
dma_unmap_sg(dev, src, 1,
|
|
|
|
dst != src ? DMA_TO_DEVICE
|
|
|
|
: DMA_BIDIRECTIONAL);
|
|
|
|
}
|
|
|
|
if (dst && edesc->dst_nents) {
|
|
|
|
dma_sync_single_for_device(dev,
|
|
|
|
edesc->dma_link_tbl + len,
|
|
|
|
len, DMA_FROM_DEVICE);
|
|
|
|
sg_copy_from_buffer(dst, edesc->dst_nents ? : 1,
|
|
|
|
edesc->buf + len, len);
|
|
|
|
} else if (dst && dst != src) {
|
|
|
|
dma_unmap_sg(dev, dst, 1, DMA_FROM_DEVICE);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
talitos_sg_unmap(dev, edesc, src, dst);
|
|
|
|
}
|
2015-04-17 08:31:51 -06:00
|
|
|
}
|
|
|
|
|
2009-03-29 01:52:32 -06:00
|
|
|
static void common_nonsnoop_unmap(struct device *dev,
|
|
|
|
struct talitos_edesc *edesc,
|
|
|
|
struct ablkcipher_request *areq)
|
|
|
|
{
|
|
|
|
unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
|
2015-04-17 08:31:51 -06:00
|
|
|
|
|
|
|
unmap_sg_talitos_ptr(dev, areq->src, areq->dst, areq->nbytes, edesc);
|
2009-03-29 01:52:32 -06:00
|
|
|
unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
|
|
|
|
unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
if (edesc->dma_len)
|
|
|
|
dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ablkcipher_done(struct device *dev,
|
|
|
|
struct talitos_desc *desc, void *context,
|
|
|
|
int err)
|
|
|
|
{
|
|
|
|
struct ablkcipher_request *areq = context;
|
2009-03-29 01:53:59 -06:00
|
|
|
struct talitos_edesc *edesc;
|
|
|
|
|
|
|
|
edesc = container_of(desc, struct talitos_edesc, desc);
|
2009-03-29 01:52:32 -06:00
|
|
|
|
|
|
|
common_nonsnoop_unmap(dev, edesc, areq);
|
|
|
|
|
|
|
|
kfree(edesc);
|
|
|
|
|
|
|
|
areq->base.complete(&areq->base, err);
|
|
|
|
}
|
|
|
|
|
2015-04-17 08:31:51 -06:00
|
|
|
int map_sg_in_talitos_ptr(struct device *dev, struct scatterlist *src,
|
|
|
|
unsigned int len, struct talitos_edesc *edesc,
|
|
|
|
enum dma_data_direction dir, struct talitos_ptr *ptr)
|
|
|
|
{
|
|
|
|
int sg_count;
|
2015-04-17 08:32:07 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
2015-04-17 08:31:51 -06:00
|
|
|
|
2015-04-17 08:32:07 -06:00
|
|
|
to_talitos_ptr_len(ptr, len, is_sec1);
|
2015-04-17 08:31:51 -06:00
|
|
|
|
2015-04-17 08:32:15 -06:00
|
|
|
if (is_sec1) {
|
|
|
|
sg_count = edesc->src_nents ? : 1;
|
2015-04-17 08:31:51 -06:00
|
|
|
|
2015-04-17 08:32:15 -06:00
|
|
|
if (sg_count == 1) {
|
|
|
|
dma_map_sg(dev, src, 1, dir);
|
|
|
|
to_talitos_ptr(ptr, sg_dma_address(src), is_sec1);
|
2015-04-17 08:31:51 -06:00
|
|
|
} else {
|
2015-04-17 08:32:15 -06:00
|
|
|
sg_copy_to_buffer(src, sg_count, edesc->buf, len);
|
|
|
|
to_talitos_ptr(ptr, edesc->dma_link_tbl, is_sec1);
|
|
|
|
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
|
|
|
|
len, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
to_talitos_ptr_extent_clear(ptr, is_sec1);
|
|
|
|
|
|
|
|
sg_count = talitos_map_sg(dev, src, edesc->src_nents ? : 1, dir,
|
|
|
|
edesc->src_chained);
|
|
|
|
|
|
|
|
if (sg_count == 1) {
|
2015-04-17 08:32:07 -06:00
|
|
|
to_talitos_ptr(ptr, sg_dma_address(src), is_sec1);
|
2015-04-17 08:32:15 -06:00
|
|
|
} else {
|
|
|
|
sg_count = sg_to_link_tbl(src, sg_count, len,
|
|
|
|
&edesc->link_tbl[0]);
|
|
|
|
if (sg_count > 1) {
|
|
|
|
to_talitos_ptr(ptr, edesc->dma_link_tbl, 0);
|
|
|
|
ptr->j_extent |= DESC_PTR_LNKTBL_JUMP;
|
|
|
|
dma_sync_single_for_device(dev,
|
|
|
|
edesc->dma_link_tbl,
|
|
|
|
edesc->dma_len,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
} else {
|
|
|
|
/* Only one segment now, so no link tbl needed*/
|
|
|
|
to_talitos_ptr(ptr, sg_dma_address(src),
|
|
|
|
is_sec1);
|
|
|
|
}
|
2015-04-17 08:31:51 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return sg_count;
|
|
|
|
}
|
|
|
|
|
|
|
|
void map_sg_out_talitos_ptr(struct device *dev, struct scatterlist *dst,
|
|
|
|
unsigned int len, struct talitos_edesc *edesc,
|
|
|
|
enum dma_data_direction dir,
|
|
|
|
struct talitos_ptr *ptr, int sg_count)
|
|
|
|
{
|
2015-04-17 08:32:07 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
|
|
|
|
2015-04-17 08:31:51 -06:00
|
|
|
if (dir != DMA_NONE)
|
|
|
|
sg_count = talitos_map_sg(dev, dst, edesc->dst_nents ? : 1,
|
|
|
|
dir, edesc->dst_chained);
|
|
|
|
|
2015-04-17 08:32:15 -06:00
|
|
|
to_talitos_ptr_len(ptr, len, is_sec1);
|
|
|
|
|
|
|
|
if (is_sec1) {
|
|
|
|
if (sg_count == 1) {
|
|
|
|
if (dir != DMA_NONE)
|
|
|
|
dma_map_sg(dev, dst, 1, dir);
|
|
|
|
to_talitos_ptr(ptr, sg_dma_address(dst), is_sec1);
|
|
|
|
} else {
|
|
|
|
to_talitos_ptr(ptr, edesc->dma_link_tbl + len, is_sec1);
|
|
|
|
dma_sync_single_for_device(dev,
|
|
|
|
edesc->dma_link_tbl + len,
|
|
|
|
len, DMA_FROM_DEVICE);
|
|
|
|
}
|
2015-04-17 08:31:51 -06:00
|
|
|
} else {
|
2015-04-17 08:32:15 -06:00
|
|
|
to_talitos_ptr_extent_clear(ptr, is_sec1);
|
|
|
|
|
|
|
|
if (sg_count == 1) {
|
|
|
|
to_talitos_ptr(ptr, sg_dma_address(dst), is_sec1);
|
|
|
|
} else {
|
|
|
|
struct talitos_ptr *link_tbl_ptr =
|
|
|
|
&edesc->link_tbl[edesc->src_nents + 1];
|
|
|
|
|
|
|
|
to_talitos_ptr(ptr, edesc->dma_link_tbl +
|
|
|
|
(edesc->src_nents + 1) *
|
|
|
|
sizeof(struct talitos_ptr), 0);
|
|
|
|
ptr->j_extent |= DESC_PTR_LNKTBL_JUMP;
|
2015-05-11 11:04:56 -06:00
|
|
|
sg_to_link_tbl(dst, sg_count, len, link_tbl_ptr);
|
2015-04-17 08:32:15 -06:00
|
|
|
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
|
|
|
|
edesc->dma_len,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
}
|
2015-04-17 08:31:51 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-03-29 01:52:32 -06:00
|
|
|
static int common_nonsnoop(struct talitos_edesc *edesc,
|
|
|
|
struct ablkcipher_request *areq,
|
|
|
|
void (*callback) (struct device *dev,
|
|
|
|
struct talitos_desc *desc,
|
|
|
|
void *context, int error))
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
|
|
|
|
struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
|
|
|
|
struct device *dev = ctx->dev;
|
|
|
|
struct talitos_desc *desc = &edesc->desc;
|
|
|
|
unsigned int cryptlen = areq->nbytes;
|
2012-08-02 08:16:40 -06:00
|
|
|
unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
|
2009-03-29 01:52:32 -06:00
|
|
|
int sg_count, ret;
|
2015-04-17 08:32:07 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
2009-03-29 01:52:32 -06:00
|
|
|
|
|
|
|
/* first DWORD empty */
|
2015-04-17 08:31:49 -06:00
|
|
|
desc->ptr[0] = zero_entry;
|
2009-03-29 01:52:32 -06:00
|
|
|
|
|
|
|
/* cipher iv */
|
2015-04-17 08:32:07 -06:00
|
|
|
to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, is_sec1);
|
|
|
|
to_talitos_ptr_len(&desc->ptr[1], ivsize, is_sec1);
|
|
|
|
to_talitos_ptr_extent_clear(&desc->ptr[1], is_sec1);
|
2009-03-29 01:52:32 -06:00
|
|
|
|
|
|
|
/* cipher key */
|
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
|
2015-04-17 08:31:57 -06:00
|
|
|
(char *)&ctx->key, DMA_TO_DEVICE);
|
2009-03-29 01:52:32 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* cipher in
|
|
|
|
*/
|
2015-04-17 08:31:51 -06:00
|
|
|
sg_count = map_sg_in_talitos_ptr(dev, areq->src, cryptlen, edesc,
|
|
|
|
(areq->src == areq->dst) ?
|
|
|
|
DMA_BIDIRECTIONAL : DMA_TO_DEVICE,
|
|
|
|
&desc->ptr[3]);
|
2009-03-29 01:52:32 -06:00
|
|
|
|
|
|
|
/* cipher out */
|
2015-04-17 08:31:51 -06:00
|
|
|
map_sg_out_talitos_ptr(dev, areq->dst, cryptlen, edesc,
|
|
|
|
(areq->src == areq->dst) ? DMA_NONE
|
|
|
|
: DMA_FROM_DEVICE,
|
|
|
|
&desc->ptr[4], sg_count);
|
2009-03-29 01:52:32 -06:00
|
|
|
|
|
|
|
/* iv out */
|
2015-04-17 08:31:57 -06:00
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
|
2009-03-29 01:52:32 -06:00
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
|
|
|
/* last DWORD empty */
|
2015-04-17 08:31:49 -06:00
|
|
|
desc->ptr[6] = zero_entry;
|
2009-03-29 01:52:32 -06:00
|
|
|
|
2011-07-14 21:21:38 -06:00
|
|
|
ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
|
2009-03-29 01:52:32 -06:00
|
|
|
if (ret != -EINPROGRESS) {
|
|
|
|
common_nonsnoop_unmap(dev, edesc, areq);
|
|
|
|
kfree(edesc);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-03-29 01:53:23 -06:00
|
|
|
static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
|
2013-11-28 06:11:17 -07:00
|
|
|
areq, bool encrypt)
|
2009-03-29 01:52:32 -06:00
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
|
|
|
|
struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
|
2012-08-02 08:16:40 -06:00
|
|
|
unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
|
2009-03-29 01:52:32 -06:00
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
|
2012-08-02 08:16:40 -06:00
|
|
|
areq->info, 0, areq->nbytes, 0, ivsize, 0,
|
2013-11-28 06:11:17 -07:00
|
|
|
areq->base.flags, encrypt);
|
2009-03-29 01:52:32 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int ablkcipher_encrypt(struct ablkcipher_request *areq)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
|
|
|
|
struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
|
|
|
|
struct talitos_edesc *edesc;
|
|
|
|
|
|
|
|
/* allocate extended descriptor */
|
2013-11-28 06:11:17 -07:00
|
|
|
edesc = ablkcipher_edesc_alloc(areq, true);
|
2009-03-29 01:52:32 -06:00
|
|
|
if (IS_ERR(edesc))
|
|
|
|
return PTR_ERR(edesc);
|
|
|
|
|
|
|
|
/* set encrypt */
|
|
|
|
edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
|
|
|
|
|
2011-07-14 21:21:39 -06:00
|
|
|
return common_nonsnoop(edesc, areq, ablkcipher_done);
|
2009-03-29 01:52:32 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int ablkcipher_decrypt(struct ablkcipher_request *areq)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
|
|
|
|
struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
|
|
|
|
struct talitos_edesc *edesc;
|
|
|
|
|
|
|
|
/* allocate extended descriptor */
|
2013-11-28 06:11:17 -07:00
|
|
|
edesc = ablkcipher_edesc_alloc(areq, false);
|
2009-03-29 01:52:32 -06:00
|
|
|
if (IS_ERR(edesc))
|
|
|
|
return PTR_ERR(edesc);
|
|
|
|
|
|
|
|
edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
|
|
|
|
|
2011-07-14 21:21:39 -06:00
|
|
|
return common_nonsnoop(edesc, areq, ablkcipher_done);
|
2009-03-29 01:52:32 -06:00
|
|
|
}
|
|
|
|
|
2010-05-19 03:20:36 -06:00
|
|
|
static void common_nonsnoop_hash_unmap(struct device *dev,
|
|
|
|
struct talitos_edesc *edesc,
|
|
|
|
struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
2015-04-17 08:32:07 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
2010-05-19 03:20:36 -06:00
|
|
|
|
|
|
|
unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
|
|
|
|
|
2015-04-17 08:31:51 -06:00
|
|
|
unmap_sg_talitos_ptr(dev, req_ctx->psrc, NULL, 0, edesc);
|
|
|
|
|
2010-05-19 03:20:36 -06:00
|
|
|
/* When using hashctx-in, must unmap it. */
|
2015-04-17 08:32:07 -06:00
|
|
|
if (from_talitos_ptr_len(&edesc->desc.ptr[1], is_sec1))
|
2010-05-19 03:20:36 -06:00
|
|
|
unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
2015-04-17 08:32:07 -06:00
|
|
|
if (from_talitos_ptr_len(&edesc->desc.ptr[2], is_sec1))
|
2010-05-19 03:20:36 -06:00
|
|
|
unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
if (edesc->dma_len)
|
|
|
|
dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ahash_done(struct device *dev,
|
|
|
|
struct talitos_desc *desc, void *context,
|
|
|
|
int err)
|
|
|
|
{
|
|
|
|
struct ahash_request *areq = context;
|
|
|
|
struct talitos_edesc *edesc =
|
|
|
|
container_of(desc, struct talitos_edesc, desc);
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
if (!req_ctx->last && req_ctx->to_hash_later) {
|
|
|
|
/* Position any partial block for next update/final/finup */
|
|
|
|
memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
|
2010-06-15 23:29:15 -06:00
|
|
|
req_ctx->nbuf = req_ctx->to_hash_later;
|
2010-05-19 03:20:36 -06:00
|
|
|
}
|
|
|
|
common_nonsnoop_hash_unmap(dev, edesc, areq);
|
|
|
|
|
|
|
|
kfree(edesc);
|
|
|
|
|
|
|
|
areq->base.complete(&areq->base, err);
|
|
|
|
}
|
|
|
|
|
2015-04-17 08:32:18 -06:00
|
|
|
/*
|
|
|
|
* SEC1 doesn't like hashing of 0 sized message, so we do the padding
|
|
|
|
* ourself and submit a padded block
|
|
|
|
*/
|
|
|
|
void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
|
|
|
|
struct talitos_edesc *edesc,
|
|
|
|
struct talitos_ptr *ptr)
|
|
|
|
{
|
|
|
|
static u8 padded_hash[64] = {
|
|
|
|
0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
pr_err_once("Bug in SEC1, padding ourself\n");
|
|
|
|
edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
|
|
|
|
map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
|
|
|
|
(char *)padded_hash, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
|
2010-05-19 03:20:36 -06:00
|
|
|
static int common_nonsnoop_hash(struct talitos_edesc *edesc,
|
|
|
|
struct ahash_request *areq, unsigned int length,
|
|
|
|
void (*callback) (struct device *dev,
|
|
|
|
struct talitos_desc *desc,
|
|
|
|
void *context, int error))
|
|
|
|
{
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
|
|
|
|
struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
struct device *dev = ctx->dev;
|
|
|
|
struct talitos_desc *desc = &edesc->desc;
|
2015-04-17 08:31:51 -06:00
|
|
|
int ret;
|
2015-04-17 08:32:07 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
2010-05-19 03:20:36 -06:00
|
|
|
|
|
|
|
/* first DWORD empty */
|
|
|
|
desc->ptr[0] = zero_entry;
|
|
|
|
|
2010-05-19 03:21:53 -06:00
|
|
|
/* hash context in */
|
|
|
|
if (!req_ctx->first || req_ctx->swinit) {
|
2010-05-19 03:20:36 -06:00
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[1],
|
|
|
|
req_ctx->hw_context_size,
|
2015-04-17 08:31:57 -06:00
|
|
|
(char *)req_ctx->hw_context,
|
2010-05-19 03:20:36 -06:00
|
|
|
DMA_TO_DEVICE);
|
2010-05-19 03:21:53 -06:00
|
|
|
req_ctx->swinit = 0;
|
2010-05-19 03:20:36 -06:00
|
|
|
} else {
|
|
|
|
desc->ptr[1] = zero_entry;
|
|
|
|
/* Indicate next op is not the first. */
|
|
|
|
req_ctx->first = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* HMAC key */
|
|
|
|
if (ctx->keylen)
|
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
|
2015-04-17 08:31:57 -06:00
|
|
|
(char *)&ctx->key, DMA_TO_DEVICE);
|
2010-05-19 03:20:36 -06:00
|
|
|
else
|
|
|
|
desc->ptr[2] = zero_entry;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* data in
|
|
|
|
*/
|
2015-04-17 08:31:51 -06:00
|
|
|
map_sg_in_talitos_ptr(dev, req_ctx->psrc, length, edesc,
|
|
|
|
DMA_TO_DEVICE, &desc->ptr[3]);
|
2010-05-19 03:20:36 -06:00
|
|
|
|
|
|
|
/* fifth DWORD empty */
|
|
|
|
desc->ptr[4] = zero_entry;
|
|
|
|
|
|
|
|
/* hash/HMAC out -or- hash context out */
|
|
|
|
if (req_ctx->last)
|
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[5],
|
|
|
|
crypto_ahash_digestsize(tfm),
|
2015-04-17 08:31:57 -06:00
|
|
|
areq->result, DMA_FROM_DEVICE);
|
2010-05-19 03:20:36 -06:00
|
|
|
else
|
|
|
|
map_single_talitos_ptr(dev, &desc->ptr[5],
|
|
|
|
req_ctx->hw_context_size,
|
2015-04-17 08:31:57 -06:00
|
|
|
req_ctx->hw_context, DMA_FROM_DEVICE);
|
2010-05-19 03:20:36 -06:00
|
|
|
|
|
|
|
/* last DWORD empty */
|
|
|
|
desc->ptr[6] = zero_entry;
|
|
|
|
|
2015-04-17 08:32:18 -06:00
|
|
|
if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
|
|
|
|
talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
|
|
|
|
|
2011-07-14 21:21:38 -06:00
|
|
|
ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
|
2010-05-19 03:20:36 -06:00
|
|
|
if (ret != -EINPROGRESS) {
|
|
|
|
common_nonsnoop_hash_unmap(dev, edesc, areq);
|
|
|
|
kfree(edesc);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
|
|
|
|
unsigned int nbytes)
|
|
|
|
{
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
|
|
|
|
struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, NULL, 0,
|
2013-11-28 06:11:17 -07:00
|
|
|
nbytes, 0, 0, 0, areq->base.flags, false);
|
2010-05-19 03:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int ahash_init(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
/* Initialize the context */
|
2010-06-15 23:29:15 -06:00
|
|
|
req_ctx->nbuf = 0;
|
2010-05-19 03:21:53 -06:00
|
|
|
req_ctx->first = 1; /* first indicates h/w must init its context */
|
|
|
|
req_ctx->swinit = 0; /* assume h/w init of context */
|
2010-05-19 03:20:36 -06:00
|
|
|
req_ctx->hw_context_size =
|
|
|
|
(crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
|
|
|
|
? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
|
|
|
|
: TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-19 03:21:53 -06:00
|
|
|
/*
|
|
|
|
* on h/w without explicit sha224 support, we initialize h/w context
|
|
|
|
* manually with sha224 constants, and tell it to run sha256.
|
|
|
|
*/
|
|
|
|
static int ahash_init_sha224_swinit(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
ahash_init(areq);
|
|
|
|
req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
|
|
|
|
|
2010-09-23 01:56:38 -06:00
|
|
|
req_ctx->hw_context[0] = SHA224_H0;
|
|
|
|
req_ctx->hw_context[1] = SHA224_H1;
|
|
|
|
req_ctx->hw_context[2] = SHA224_H2;
|
|
|
|
req_ctx->hw_context[3] = SHA224_H3;
|
|
|
|
req_ctx->hw_context[4] = SHA224_H4;
|
|
|
|
req_ctx->hw_context[5] = SHA224_H5;
|
|
|
|
req_ctx->hw_context[6] = SHA224_H6;
|
|
|
|
req_ctx->hw_context[7] = SHA224_H7;
|
2010-05-19 03:21:53 -06:00
|
|
|
|
|
|
|
/* init 64-bit count */
|
|
|
|
req_ctx->hw_context[8] = 0;
|
|
|
|
req_ctx->hw_context[9] = 0;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-19 03:20:36 -06:00
|
|
|
static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
|
|
|
|
{
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
|
|
|
|
struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
struct talitos_edesc *edesc;
|
|
|
|
unsigned int blocksize =
|
|
|
|
crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
|
|
|
|
unsigned int nbytes_to_hash;
|
|
|
|
unsigned int to_hash_later;
|
2010-06-15 23:29:15 -06:00
|
|
|
unsigned int nsg;
|
2012-08-02 08:16:39 -06:00
|
|
|
bool chained;
|
2010-05-19 03:20:36 -06:00
|
|
|
|
2010-06-15 23:29:15 -06:00
|
|
|
if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
|
|
|
|
/* Buffer up to one whole block */
|
2010-05-19 03:20:36 -06:00
|
|
|
sg_copy_to_buffer(areq->src,
|
|
|
|
sg_count(areq->src, nbytes, &chained),
|
2010-06-15 23:29:15 -06:00
|
|
|
req_ctx->buf + req_ctx->nbuf, nbytes);
|
|
|
|
req_ctx->nbuf += nbytes;
|
2010-05-19 03:20:36 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-15 23:29:15 -06:00
|
|
|
/* At least (blocksize + 1) bytes are available to hash */
|
|
|
|
nbytes_to_hash = nbytes + req_ctx->nbuf;
|
|
|
|
to_hash_later = nbytes_to_hash & (blocksize - 1);
|
|
|
|
|
|
|
|
if (req_ctx->last)
|
|
|
|
to_hash_later = 0;
|
|
|
|
else if (to_hash_later)
|
|
|
|
/* There is a partial block. Hash the full block(s) now */
|
|
|
|
nbytes_to_hash -= to_hash_later;
|
|
|
|
else {
|
|
|
|
/* Keep one block buffered */
|
|
|
|
nbytes_to_hash -= blocksize;
|
|
|
|
to_hash_later = blocksize;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Chain in any previously buffered data */
|
|
|
|
if (req_ctx->nbuf) {
|
|
|
|
nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
|
|
|
|
sg_init_table(req_ctx->bufsl, nsg);
|
|
|
|
sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
|
|
|
|
if (nsg > 1)
|
2015-08-07 10:15:13 -06:00
|
|
|
sg_chain(req_ctx->bufsl, 2, areq->src);
|
2010-05-19 03:20:36 -06:00
|
|
|
req_ctx->psrc = req_ctx->bufsl;
|
2010-06-15 23:29:15 -06:00
|
|
|
} else
|
2010-05-19 03:20:36 -06:00
|
|
|
req_ctx->psrc = areq->src;
|
2010-06-15 23:29:15 -06:00
|
|
|
|
|
|
|
if (to_hash_later) {
|
|
|
|
int nents = sg_count(areq->src, nbytes, &chained);
|
2013-07-08 17:01:55 -06:00
|
|
|
sg_pcopy_to_buffer(areq->src, nents,
|
2010-06-15 23:29:15 -06:00
|
|
|
req_ctx->bufnext,
|
|
|
|
to_hash_later,
|
|
|
|
nbytes - to_hash_later);
|
2010-05-19 03:20:36 -06:00
|
|
|
}
|
2010-06-15 23:29:15 -06:00
|
|
|
req_ctx->to_hash_later = to_hash_later;
|
2010-05-19 03:20:36 -06:00
|
|
|
|
2010-06-15 23:29:15 -06:00
|
|
|
/* Allocate extended descriptor */
|
2010-05-19 03:20:36 -06:00
|
|
|
edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
|
|
|
|
if (IS_ERR(edesc))
|
|
|
|
return PTR_ERR(edesc);
|
|
|
|
|
|
|
|
edesc->desc.hdr = ctx->desc_hdr_template;
|
|
|
|
|
|
|
|
/* On last one, request SEC to pad; otherwise continue */
|
|
|
|
if (req_ctx->last)
|
|
|
|
edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
|
|
|
|
else
|
|
|
|
edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
|
|
|
|
|
2010-05-19 03:21:53 -06:00
|
|
|
/* request SEC to INIT hash. */
|
|
|
|
if (req_ctx->first && !req_ctx->swinit)
|
2010-05-19 03:20:36 -06:00
|
|
|
edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
|
|
|
|
|
|
|
|
/* When the tfm context has a keylen, it's an HMAC.
|
|
|
|
* A first or last (ie. not middle) descriptor must request HMAC.
|
|
|
|
*/
|
|
|
|
if (ctx->keylen && (req_ctx->first || req_ctx->last))
|
|
|
|
edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
|
|
|
|
|
|
|
|
return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
|
|
|
|
ahash_done);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ahash_update(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
req_ctx->last = 0;
|
|
|
|
|
|
|
|
return ahash_process_req(areq, areq->nbytes);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ahash_final(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
req_ctx->last = 1;
|
|
|
|
|
|
|
|
return ahash_process_req(areq, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ahash_finup(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
req_ctx->last = 1;
|
|
|
|
|
|
|
|
return ahash_process_req(areq, areq->nbytes);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ahash_digest(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
2010-05-19 03:21:53 -06:00
|
|
|
struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
|
2010-05-19 03:20:36 -06:00
|
|
|
|
2010-05-19 03:21:53 -06:00
|
|
|
ahash->init(areq);
|
2010-05-19 03:20:36 -06:00
|
|
|
req_ctx->last = 1;
|
|
|
|
|
|
|
|
return ahash_process_req(areq, areq->nbytes);
|
|
|
|
}
|
|
|
|
|
2011-11-21 01:13:25 -07:00
|
|
|
struct keyhash_result {
|
|
|
|
struct completion completion;
|
|
|
|
int err;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void keyhash_complete(struct crypto_async_request *req, int err)
|
|
|
|
{
|
|
|
|
struct keyhash_result *res = req->data;
|
|
|
|
|
|
|
|
if (err == -EINPROGRESS)
|
|
|
|
return;
|
|
|
|
|
|
|
|
res->err = err;
|
|
|
|
complete(&res->completion);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
|
|
|
|
u8 *hash)
|
|
|
|
{
|
|
|
|
struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
|
|
|
|
|
|
|
|
struct scatterlist sg[1];
|
|
|
|
struct ahash_request *req;
|
|
|
|
struct keyhash_result hresult;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
init_completion(&hresult.completion);
|
|
|
|
|
|
|
|
req = ahash_request_alloc(tfm, GFP_KERNEL);
|
|
|
|
if (!req)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
/* Keep tfm keylen == 0 during hash of the long key */
|
|
|
|
ctx->keylen = 0;
|
|
|
|
ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
|
|
|
|
keyhash_complete, &hresult);
|
|
|
|
|
|
|
|
sg_init_one(&sg[0], key, keylen);
|
|
|
|
|
|
|
|
ahash_request_set_crypt(req, sg, hash, keylen);
|
|
|
|
ret = crypto_ahash_digest(req);
|
|
|
|
switch (ret) {
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
case -EINPROGRESS:
|
|
|
|
case -EBUSY:
|
|
|
|
ret = wait_for_completion_interruptible(
|
|
|
|
&hresult.completion);
|
|
|
|
if (!ret)
|
|
|
|
ret = hresult.err;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
ahash_request_free(req);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
|
|
|
struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
|
|
|
|
unsigned int blocksize =
|
|
|
|
crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
|
|
|
|
unsigned int digestsize = crypto_ahash_digestsize(tfm);
|
|
|
|
unsigned int keysize = keylen;
|
|
|
|
u8 hash[SHA512_DIGEST_SIZE];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (keylen <= blocksize)
|
|
|
|
memcpy(ctx->key, key, keysize);
|
|
|
|
else {
|
|
|
|
/* Must get the hash of the long key */
|
|
|
|
ret = keyhash(tfm, key, keylen, hash);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
keysize = digestsize;
|
|
|
|
memcpy(ctx->key, hash, digestsize);
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->keylen = keysize;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
struct talitos_alg_template {
|
2010-05-19 03:18:38 -06:00
|
|
|
u32 type;
|
|
|
|
union {
|
|
|
|
struct crypto_alg crypto;
|
2010-05-19 03:19:33 -06:00
|
|
|
struct ahash_alg hash;
|
2015-07-30 03:53:22 -06:00
|
|
|
struct aead_alg aead;
|
2010-05-19 03:18:38 -06:00
|
|
|
} alg;
|
2008-06-23 05:50:15 -06:00
|
|
|
__be32 desc_hdr_template;
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct talitos_alg_template driver_algs[] = {
|
Revert "crypto: talitos - add IPsec ESN support"
This reverts commit e763eb699be723fb41af818118068c6b3afdaf8d.
Current IPsec ESN implementation for authencesn(cbc(aes), hmac(sha))
(separate encryption and integrity algorithms) does not conform
to RFC4303.
ICV is generated by hashing the sequence
SPI, SeqNum-High, SeqNum-Low, IV, Payload
instead of
SPI, SeqNum-Low, IV, Payload, SeqNum-High.
Cc: <stable@vger.kernel.org> # 3.8, 3.7
Reported-by: Chaoxing Lin <Chaoxing.Lin@ultra-3eti.com>
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-03-20 08:31:38 -06:00
|
|
|
/* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
|
2010-05-19 03:18:38 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha1),cbc(aes))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha1-"
|
|
|
|
"cbc-aes-talitos",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA1_DIGEST_SIZE,
|
2009-03-29 01:50:50 -06:00
|
|
|
},
|
2008-06-23 05:50:15 -06:00
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_AESU |
|
|
|
|
DESC_HDR_MODE0_AESU_CBC |
|
|
|
|
DESC_HDR_SEL1_MDEUA |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEU_SHA1_HMAC,
|
2008-07-03 05:08:46 -06:00
|
|
|
},
|
2010-05-19 03:18:38 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha1),"
|
|
|
|
"cbc(des3_ede))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha1-"
|
|
|
|
"cbc-3des-talitos",
|
|
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA1_DIGEST_SIZE,
|
2009-03-29 01:50:50 -06:00
|
|
|
},
|
2008-07-03 05:08:46 -06:00
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_DEU |
|
|
|
|
DESC_HDR_MODE0_DEU_CBC |
|
|
|
|
DESC_HDR_MODE0_DEU_3DES |
|
|
|
|
DESC_HDR_SEL1_MDEUA |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEU_SHA1_HMAC,
|
2008-07-10 04:29:18 -06:00
|
|
|
},
|
2012-07-03 10:16:53 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha224),cbc(aes))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha224-"
|
|
|
|
"cbc-aes-talitos",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA224_DIGEST_SIZE,
|
2012-07-03 10:16:53 -06:00
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_AESU |
|
|
|
|
DESC_HDR_MODE0_AESU_CBC |
|
|
|
|
DESC_HDR_SEL1_MDEUA |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEU_SHA224_HMAC,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha224),"
|
|
|
|
"cbc(des3_ede))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha224-"
|
|
|
|
"cbc-3des-talitos",
|
|
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA224_DIGEST_SIZE,
|
2012-07-03 10:16:53 -06:00
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_DEU |
|
|
|
|
DESC_HDR_MODE0_DEU_CBC |
|
|
|
|
DESC_HDR_MODE0_DEU_3DES |
|
|
|
|
DESC_HDR_SEL1_MDEUA |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEU_SHA224_HMAC,
|
|
|
|
},
|
2010-05-19 03:18:38 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha256),cbc(aes))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha256-"
|
|
|
|
"cbc-aes-talitos",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA256_DIGEST_SIZE,
|
2009-03-29 01:50:50 -06:00
|
|
|
},
|
2008-07-10 04:29:18 -06:00
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_AESU |
|
|
|
|
DESC_HDR_MODE0_AESU_CBC |
|
|
|
|
DESC_HDR_SEL1_MDEUA |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEU_SHA256_HMAC,
|
|
|
|
},
|
2010-05-19 03:18:38 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha256),"
|
|
|
|
"cbc(des3_ede))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha256-"
|
|
|
|
"cbc-3des-talitos",
|
|
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA256_DIGEST_SIZE,
|
2009-03-29 01:50:50 -06:00
|
|
|
},
|
2008-07-10 04:29:18 -06:00
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_DEU |
|
|
|
|
DESC_HDR_MODE0_DEU_CBC |
|
|
|
|
DESC_HDR_MODE0_DEU_3DES |
|
|
|
|
DESC_HDR_SEL1_MDEUA |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEU_SHA256_HMAC,
|
|
|
|
},
|
2010-05-19 03:18:38 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha384),cbc(aes))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha384-"
|
|
|
|
"cbc-aes-talitos",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA384_DIGEST_SIZE,
|
2012-07-03 10:16:53 -06:00
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_AESU |
|
|
|
|
DESC_HDR_MODE0_AESU_CBC |
|
|
|
|
DESC_HDR_SEL1_MDEUB |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha384),"
|
|
|
|
"cbc(des3_ede))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha384-"
|
|
|
|
"cbc-3des-talitos",
|
|
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA384_DIGEST_SIZE,
|
2012-07-03 10:16:53 -06:00
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_DEU |
|
|
|
|
DESC_HDR_MODE0_DEU_CBC |
|
|
|
|
DESC_HDR_MODE0_DEU_3DES |
|
|
|
|
DESC_HDR_SEL1_MDEUB |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha512),cbc(aes))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha512-"
|
|
|
|
"cbc-aes-talitos",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA512_DIGEST_SIZE,
|
2012-07-03 10:16:53 -06:00
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_AESU |
|
|
|
|
DESC_HDR_MODE0_AESU_CBC |
|
|
|
|
DESC_HDR_SEL1_MDEUB |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha512),"
|
|
|
|
"cbc(des3_ede))",
|
|
|
|
.cra_driver_name = "authenc-hmac-sha512-"
|
|
|
|
"cbc-3des-talitos",
|
|
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA512_DIGEST_SIZE,
|
2012-07-03 10:16:53 -06:00
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_DEU |
|
|
|
|
DESC_HDR_MODE0_DEU_CBC |
|
|
|
|
DESC_HDR_MODE0_DEU_3DES |
|
|
|
|
DESC_HDR_SEL1_MDEUB |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(md5),cbc(aes))",
|
|
|
|
.cra_driver_name = "authenc-hmac-md5-"
|
|
|
|
"cbc-aes-talitos",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = MD5_DIGEST_SIZE,
|
2009-03-29 01:50:50 -06:00
|
|
|
},
|
2008-07-10 04:29:18 -06:00
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_AESU |
|
|
|
|
DESC_HDR_MODE0_AESU_CBC |
|
|
|
|
DESC_HDR_SEL1_MDEUA |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEU_MD5_HMAC,
|
|
|
|
},
|
2010-05-19 03:18:38 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AEAD,
|
2015-07-30 03:53:22 -06:00
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
|
|
|
|
.cra_driver_name = "authenc-hmac-md5-"
|
|
|
|
"cbc-3des-talitos",
|
|
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC,
|
|
|
|
},
|
|
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.maxauthsize = MD5_DIGEST_SIZE,
|
2009-03-29 01:50:50 -06:00
|
|
|
},
|
2008-07-10 04:29:18 -06:00
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
|
|
|
|
DESC_HDR_SEL0_DEU |
|
|
|
|
DESC_HDR_MODE0_DEU_CBC |
|
|
|
|
DESC_HDR_MODE0_DEU_3DES |
|
|
|
|
DESC_HDR_SEL1_MDEUA |
|
|
|
|
DESC_HDR_MODE1_MDEU_INIT |
|
|
|
|
DESC_HDR_MODE1_MDEU_PAD |
|
|
|
|
DESC_HDR_MODE1_MDEU_MD5_HMAC,
|
2009-03-29 01:52:32 -06:00
|
|
|
},
|
|
|
|
/* ABLKCIPHER algorithms. */
|
2010-05-19 03:18:38 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.alg.crypto = {
|
2009-03-29 01:52:32 -06:00
|
|
|
.cra_name = "cbc(aes)",
|
|
|
|
.cra_driver_name = "cbc-aes-talitos",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
.cra_ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_AESU |
|
|
|
|
DESC_HDR_MODE0_AESU_CBC,
|
|
|
|
},
|
2010-05-19 03:18:38 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.alg.crypto = {
|
2009-03-29 01:52:32 -06:00
|
|
|
.cra_name = "cbc(des3_ede)",
|
|
|
|
.cra_driver_name = "cbc-3des-talitos",
|
|
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
.cra_ablkcipher = {
|
|
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_DEU |
|
|
|
|
DESC_HDR_MODE0_DEU_CBC |
|
|
|
|
DESC_HDR_MODE0_DEU_3DES,
|
2010-05-19 03:20:36 -06:00
|
|
|
},
|
|
|
|
/* AHASH algorithms. */
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = MD5_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "md5",
|
|
|
|
.cra_driver_name = "md5-talitos",
|
2015-03-03 06:21:34 -07:00
|
|
|
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
|
2010-05-19 03:20:36 -06:00
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_MD5,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha1",
|
|
|
|
.cra_driver_name = "sha1-talitos",
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_SHA1,
|
|
|
|
},
|
2010-05-19 03:21:53 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA224_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha224",
|
|
|
|
.cra_driver_name = "sha224-talitos",
|
|
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_SHA224,
|
|
|
|
},
|
2010-05-19 03:20:36 -06:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA256_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha256",
|
|
|
|
.cra_driver_name = "sha256-talitos",
|
|
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_SHA256,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA384_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha384",
|
|
|
|
.cra_driver_name = "sha384-talitos",
|
|
|
|
.cra_blocksize = SHA384_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUB |
|
|
|
|
DESC_HDR_MODE0_MDEUB_SHA384,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA512_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha512",
|
|
|
|
.cra_driver_name = "sha512-talitos",
|
|
|
|
.cra_blocksize = SHA512_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUB |
|
|
|
|
DESC_HDR_MODE0_MDEUB_SHA512,
|
|
|
|
},
|
2011-11-21 01:13:25 -07:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = MD5_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(md5)",
|
|
|
|
.cra_driver_name = "hmac-md5-talitos",
|
2015-03-03 06:21:34 -07:00
|
|
|
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
|
2011-11-21 01:13:25 -07:00
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_MD5,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha1)",
|
|
|
|
.cra_driver_name = "hmac-sha1-talitos",
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_SHA1,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA224_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha224)",
|
|
|
|
.cra_driver_name = "hmac-sha224-talitos",
|
|
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_SHA224,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA256_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha256)",
|
|
|
|
.cra_driver_name = "hmac-sha256-talitos",
|
|
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_SHA256,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA384_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha384)",
|
|
|
|
.cra_driver_name = "hmac-sha384-talitos",
|
|
|
|
.cra_blocksize = SHA384_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUB |
|
|
|
|
DESC_HDR_MODE0_MDEUB_SHA384,
|
|
|
|
},
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA512_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha512)",
|
|
|
|
.cra_driver_name = "hmac-sha512-talitos",
|
|
|
|
.cra_blocksize = SHA512_BLOCK_SIZE,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUB |
|
|
|
|
DESC_HDR_MODE0_MDEUB_SHA512,
|
|
|
|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
struct talitos_crypto_alg {
|
|
|
|
struct list_head entry;
|
|
|
|
struct device *dev;
|
2010-05-19 03:19:33 -06:00
|
|
|
struct talitos_alg_template algt;
|
2008-06-23 05:50:15 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static int talitos_cra_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct crypto_alg *alg = tfm->__crt_alg;
|
2009-03-29 01:53:59 -06:00
|
|
|
struct talitos_crypto_alg *talitos_alg;
|
2008-06-23 05:50:15 -06:00
|
|
|
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
|
2011-07-14 21:21:38 -06:00
|
|
|
struct talitos_private *priv;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2010-05-19 03:20:36 -06:00
|
|
|
if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
|
|
|
|
talitos_alg = container_of(__crypto_ahash_alg(alg),
|
|
|
|
struct talitos_crypto_alg,
|
|
|
|
algt.alg.hash);
|
|
|
|
else
|
|
|
|
talitos_alg = container_of(alg, struct talitos_crypto_alg,
|
|
|
|
algt.alg.crypto);
|
2009-03-29 01:53:59 -06:00
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
/* update context with ptr to dev */
|
|
|
|
ctx->dev = talitos_alg->dev;
|
2009-03-29 01:53:59 -06:00
|
|
|
|
2011-07-14 21:21:38 -06:00
|
|
|
/* assign SEC channel to tfm in round-robin fashion */
|
|
|
|
priv = dev_get_drvdata(ctx->dev);
|
|
|
|
ctx->ch = atomic_inc_return(&priv->last_chan) &
|
|
|
|
(priv->num_channels - 1);
|
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
/* copy descriptor header template value */
|
2010-05-19 03:19:33 -06:00
|
|
|
ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2011-07-14 21:21:39 -06:00
|
|
|
/* select done notification */
|
|
|
|
ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
|
|
|
|
|
2010-05-19 03:20:36 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-07-30 03:53:22 -06:00
|
|
|
static int talitos_cra_init_aead(struct crypto_aead *tfm)
|
2010-05-19 03:20:36 -06:00
|
|
|
{
|
2015-07-30 03:53:22 -06:00
|
|
|
talitos_cra_init(crypto_aead_tfm(tfm));
|
2008-06-23 05:50:15 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-19 03:20:36 -06:00
|
|
|
static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
|
|
|
|
talitos_cra_init(tfm);
|
|
|
|
|
|
|
|
ctx->keylen = 0;
|
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
|
|
sizeof(struct talitos_ahash_req_ctx));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-06-23 05:50:15 -06:00
|
|
|
/*
|
|
|
|
* given the alg's descriptor header template, determine whether descriptor
|
|
|
|
* type and primary/secondary execution units required match the hw
|
|
|
|
* capabilities description provided in the device tree node.
|
|
|
|
*/
|
|
|
|
static int hw_supports(struct device *dev, __be32 desc_hdr_template)
|
|
|
|
{
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
|
|
|
|
(1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
|
|
|
|
|
|
|
|
if (SECONDARY_EU(desc_hdr_template))
|
|
|
|
ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
|
|
|
|
& priv->exec_units);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-08-06 09:25:50 -06:00
|
|
|
static int talitos_remove(struct platform_device *ofdev)
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
struct device *dev = &ofdev->dev;
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
struct talitos_crypto_alg *t_alg, *n;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
|
2010-05-19 03:19:33 -06:00
|
|
|
switch (t_alg->algt.type) {
|
|
|
|
case CRYPTO_ALG_TYPE_ABLKCIPHER:
|
|
|
|
break;
|
2015-07-30 03:53:22 -06:00
|
|
|
case CRYPTO_ALG_TYPE_AEAD:
|
|
|
|
crypto_unregister_aead(&t_alg->algt.alg.aead);
|
2010-05-19 03:19:33 -06:00
|
|
|
case CRYPTO_ALG_TYPE_AHASH:
|
|
|
|
crypto_unregister_ahash(&t_alg->algt.alg.hash);
|
|
|
|
break;
|
|
|
|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
list_del(&t_alg->entry);
|
|
|
|
kfree(t_alg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hw_supports(dev, DESC_HDR_SEL0_RNG))
|
|
|
|
talitos_unregister_rng(dev);
|
|
|
|
|
2015-08-05 15:52:08 -06:00
|
|
|
for (i = 0; priv->chan && i < priv->num_channels; i++)
|
2010-09-23 01:56:08 -06:00
|
|
|
kfree(priv->chan[i].fifo);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2009-08-12 19:50:38 -06:00
|
|
|
kfree(priv->chan);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2011-11-21 01:13:27 -07:00
|
|
|
for (i = 0; i < 2; i++)
|
2011-12-12 13:59:11 -07:00
|
|
|
if (priv->irq[i]) {
|
2011-11-21 01:13:27 -07:00
|
|
|
free_irq(priv->irq[i], dev);
|
|
|
|
irq_dispose_mapping(priv->irq[i]);
|
|
|
|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
|
2011-11-21 01:13:27 -07:00
|
|
|
tasklet_kill(&priv->done_task[0]);
|
2011-12-12 13:59:11 -07:00
|
|
|
if (priv->irq[1])
|
2011-11-21 01:13:27 -07:00
|
|
|
tasklet_kill(&priv->done_task[1]);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
iounmap(priv->reg);
|
|
|
|
|
|
|
|
kfree(priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
|
|
|
|
struct talitos_alg_template
|
|
|
|
*template)
|
|
|
|
{
|
2010-05-19 03:21:53 -06:00
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
2008-06-23 05:50:15 -06:00
|
|
|
struct talitos_crypto_alg *t_alg;
|
|
|
|
struct crypto_alg *alg;
|
|
|
|
|
|
|
|
t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
|
|
|
|
if (!t_alg)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
2010-05-19 03:19:33 -06:00
|
|
|
t_alg->algt = *template;
|
|
|
|
|
|
|
|
switch (t_alg->algt.type) {
|
|
|
|
case CRYPTO_ALG_TYPE_ABLKCIPHER:
|
2010-05-19 03:20:36 -06:00
|
|
|
alg = &t_alg->algt.alg.crypto;
|
|
|
|
alg->cra_init = talitos_cra_init;
|
2012-08-08 19:32:00 -06:00
|
|
|
alg->cra_type = &crypto_ablkcipher_type;
|
2012-08-08 19:33:34 -06:00
|
|
|
alg->cra_ablkcipher.setkey = ablkcipher_setkey;
|
|
|
|
alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
|
|
|
|
alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
|
|
|
|
alg->cra_ablkcipher.geniv = "eseqiv";
|
2010-05-19 03:20:36 -06:00
|
|
|
break;
|
2010-05-19 03:19:33 -06:00
|
|
|
case CRYPTO_ALG_TYPE_AEAD:
|
2015-07-30 03:53:22 -06:00
|
|
|
alg = &t_alg->algt.alg.aead.base;
|
|
|
|
t_alg->algt.alg.aead.init = talitos_cra_init_aead;
|
|
|
|
t_alg->algt.alg.aead.setkey = aead_setkey;
|
|
|
|
t_alg->algt.alg.aead.encrypt = aead_encrypt;
|
|
|
|
t_alg->algt.alg.aead.decrypt = aead_decrypt;
|
2010-05-19 03:19:33 -06:00
|
|
|
break;
|
|
|
|
case CRYPTO_ALG_TYPE_AHASH:
|
|
|
|
alg = &t_alg->algt.alg.hash.halg.base;
|
2010-05-19 03:20:36 -06:00
|
|
|
alg->cra_init = talitos_cra_init_ahash;
|
2012-08-08 19:32:00 -06:00
|
|
|
alg->cra_type = &crypto_ahash_type;
|
2012-08-08 19:33:34 -06:00
|
|
|
t_alg->algt.alg.hash.init = ahash_init;
|
|
|
|
t_alg->algt.alg.hash.update = ahash_update;
|
|
|
|
t_alg->algt.alg.hash.final = ahash_final;
|
|
|
|
t_alg->algt.alg.hash.finup = ahash_finup;
|
|
|
|
t_alg->algt.alg.hash.digest = ahash_digest;
|
|
|
|
t_alg->algt.alg.hash.setkey = ahash_setkey;
|
|
|
|
|
2011-11-21 01:13:25 -07:00
|
|
|
if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
|
2011-12-12 13:59:10 -07:00
|
|
|
!strncmp(alg->cra_name, "hmac", 4)) {
|
|
|
|
kfree(t_alg);
|
2011-11-21 01:13:25 -07:00
|
|
|
return ERR_PTR(-ENOTSUPP);
|
2011-12-12 13:59:10 -07:00
|
|
|
}
|
2010-05-19 03:21:53 -06:00
|
|
|
if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
|
2011-11-21 01:13:25 -07:00
|
|
|
(!strcmp(alg->cra_name, "sha224") ||
|
|
|
|
!strcmp(alg->cra_name, "hmac(sha224)"))) {
|
2010-05-19 03:21:53 -06:00
|
|
|
t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
|
|
|
|
t_alg->algt.desc_hdr_template =
|
|
|
|
DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
|
|
|
|
DESC_HDR_SEL0_MDEUA |
|
|
|
|
DESC_HDR_MODE0_MDEU_SHA256;
|
|
|
|
}
|
2010-05-19 03:20:36 -06:00
|
|
|
break;
|
2010-09-23 01:55:27 -06:00
|
|
|
default:
|
|
|
|
dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
|
2015-05-11 11:03:24 -06:00
|
|
|
kfree(t_alg);
|
2010-09-23 01:55:27 -06:00
|
|
|
return ERR_PTR(-EINVAL);
|
2010-05-19 03:19:33 -06:00
|
|
|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
alg->cra_module = THIS_MODULE;
|
|
|
|
alg->cra_priority = TALITOS_CRA_PRIORITY;
|
|
|
|
alg->cra_alignmask = 0;
|
|
|
|
alg->cra_ctxsize = sizeof(struct talitos_ctx);
|
2011-11-01 06:39:56 -06:00
|
|
|
alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
t_alg->dev = dev;
|
|
|
|
|
|
|
|
return t_alg;
|
|
|
|
}
|
|
|
|
|
2011-11-21 01:13:27 -07:00
|
|
|
static int talitos_probe_irq(struct platform_device *ofdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &ofdev->dev;
|
|
|
|
struct device_node *np = ofdev->dev.of_node;
|
|
|
|
struct talitos_private *priv = dev_get_drvdata(dev);
|
|
|
|
int err;
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
bool is_sec1 = has_ftr_sec1(priv);
|
2011-11-21 01:13:27 -07:00
|
|
|
|
|
|
|
priv->irq[0] = irq_of_parse_and_map(np, 0);
|
2011-12-12 13:59:11 -07:00
|
|
|
if (!priv->irq[0]) {
|
2011-11-21 01:13:27 -07:00
|
|
|
dev_err(dev, "failed to map irq\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
if (is_sec1) {
|
|
|
|
err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
|
|
|
|
dev_driver_string(dev), dev);
|
|
|
|
goto primary_out;
|
|
|
|
}
|
2011-11-21 01:13:27 -07:00
|
|
|
|
|
|
|
priv->irq[1] = irq_of_parse_and_map(np, 1);
|
|
|
|
|
|
|
|
/* get the primary irq line */
|
2011-12-12 13:59:11 -07:00
|
|
|
if (!priv->irq[1]) {
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
err = request_irq(priv->irq[0], talitos2_interrupt_4ch, 0,
|
2011-11-21 01:13:27 -07:00
|
|
|
dev_driver_string(dev), dev);
|
|
|
|
goto primary_out;
|
|
|
|
}
|
|
|
|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
err = request_irq(priv->irq[0], talitos2_interrupt_ch0_2, 0,
|
2011-11-21 01:13:27 -07:00
|
|
|
dev_driver_string(dev), dev);
|
|
|
|
if (err)
|
|
|
|
goto primary_out;
|
|
|
|
|
|
|
|
/* get the secondary irq line */
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
|
|
|
err = request_irq(priv->irq[1], talitos2_interrupt_ch1_3, 0,
|
2011-11-21 01:13:27 -07:00
|
|
|
dev_driver_string(dev), dev);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "failed to request secondary irq\n");
|
|
|
|
irq_dispose_mapping(priv->irq[1]);
|
2011-12-12 13:59:11 -07:00
|
|
|
priv->irq[1] = 0;
|
2011-11-21 01:13:27 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
primary_out:
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "failed to request primary irq\n");
|
|
|
|
irq_dispose_mapping(priv->irq[0]);
|
2011-12-12 13:59:11 -07:00
|
|
|
priv->irq[0] = 0;
|
2011-11-21 01:13:27 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2011-02-17 02:43:24 -07:00
|
|
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static int talitos_probe(struct platform_device *ofdev)
|
2008-06-23 05:50:15 -06:00
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|
|
{
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struct device *dev = &ofdev->dev;
|
2010-04-13 17:12:29 -06:00
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|
|
struct device_node *np = ofdev->dev.of_node;
|
2008-06-23 05:50:15 -06:00
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|
struct talitos_private *priv;
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|
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const unsigned int *prop;
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int i, err;
|
2015-04-17 08:32:11 -06:00
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|
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int stride;
|
2008-06-23 05:50:15 -06:00
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priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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|
2014-01-28 05:17:23 -07:00
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INIT_LIST_HEAD(&priv->alg_list);
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2008-06-23 05:50:15 -06:00
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dev_set_drvdata(dev, priv);
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|
priv->ofdev = ofdev;
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2012-03-30 08:49:53 -06:00
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spin_lock_init(&priv->reg_lock);
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|
2008-06-23 05:50:15 -06:00
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|
priv->reg = of_iomap(np, 0);
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if (!priv->reg) {
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dev_err(dev, "failed to of_iomap\n");
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|
err = -ENOMEM;
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goto err_out;
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}
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|
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/* get SEC version capabilities from device tree */
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prop = of_get_property(np, "fsl,num-channels", NULL);
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if (prop)
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priv->num_channels = *prop;
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prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
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if (prop)
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priv->chfifo_len = *prop;
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prop = of_get_property(np, "fsl,exec-units-mask", NULL);
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if (prop)
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priv->exec_units = *prop;
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prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
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if (prop)
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priv->desc_types = *prop;
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if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
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!priv->exec_units || !priv->desc_types) {
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dev_err(dev, "invalid property data in device tree node\n");
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err = -EINVAL;
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goto err_out;
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}
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2008-07-30 02:26:57 -06:00
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if (of_device_is_compatible(np, "fsl,sec3.0"))
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priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
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2008-10-12 06:33:14 -06:00
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if (of_device_is_compatible(np, "fsl,sec2.1"))
|
2010-05-19 03:21:53 -06:00
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priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
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2011-11-21 01:13:25 -07:00
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TALITOS_FTR_SHA224_HWINIT |
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TALITOS_FTR_HMAC_OK;
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2008-10-12 06:33:14 -06:00
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|
2015-04-17 08:32:05 -06:00
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if (of_device_is_compatible(np, "fsl,sec1.0"))
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priv->features |= TALITOS_FTR_SEC1;
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|
2015-04-17 08:32:11 -06:00
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if (of_device_is_compatible(np, "fsl,sec1.2")) {
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priv->reg_deu = priv->reg + TALITOS12_DEU;
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priv->reg_aesu = priv->reg + TALITOS12_AESU;
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priv->reg_mdeu = priv->reg + TALITOS12_MDEU;
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stride = TALITOS1_CH_STRIDE;
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} else if (of_device_is_compatible(np, "fsl,sec1.0")) {
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priv->reg_deu = priv->reg + TALITOS10_DEU;
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priv->reg_aesu = priv->reg + TALITOS10_AESU;
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priv->reg_mdeu = priv->reg + TALITOS10_MDEU;
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priv->reg_afeu = priv->reg + TALITOS10_AFEU;
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priv->reg_rngu = priv->reg + TALITOS10_RNGU;
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priv->reg_pkeu = priv->reg + TALITOS10_PKEU;
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stride = TALITOS1_CH_STRIDE;
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} else {
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priv->reg_deu = priv->reg + TALITOS2_DEU;
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priv->reg_aesu = priv->reg + TALITOS2_AESU;
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priv->reg_mdeu = priv->reg + TALITOS2_MDEU;
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priv->reg_afeu = priv->reg + TALITOS2_AFEU;
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priv->reg_rngu = priv->reg + TALITOS2_RNGU;
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priv->reg_pkeu = priv->reg + TALITOS2_PKEU;
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priv->reg_keu = priv->reg + TALITOS2_KEU;
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priv->reg_crcu = priv->reg + TALITOS2_CRCU;
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stride = TALITOS2_CH_STRIDE;
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}
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 08:32:13 -06:00
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err = talitos_probe_irq(ofdev);
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if (err)
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goto err_out;
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if (of_device_is_compatible(np, "fsl,sec1.0")) {
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tasklet_init(&priv->done_task[0], talitos1_done_4ch,
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(unsigned long)dev);
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} else {
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if (!priv->irq[1]) {
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tasklet_init(&priv->done_task[0], talitos2_done_4ch,
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(unsigned long)dev);
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} else {
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tasklet_init(&priv->done_task[0], talitos2_done_ch0_2,
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(unsigned long)dev);
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tasklet_init(&priv->done_task[1], talitos2_done_ch1_3,
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(unsigned long)dev);
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}
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}
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2009-08-12 19:50:38 -06:00
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priv->chan = kzalloc(sizeof(struct talitos_channel) *
|
|
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priv->num_channels, GFP_KERNEL);
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if (!priv->chan) {
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dev_err(dev, "failed to allocate channel management space\n");
|
2008-06-23 05:50:15 -06:00
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|
|
err = -ENOMEM;
|
|
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|
goto err_out;
|
|
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}
|
|
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|
2015-03-03 06:21:33 -07:00
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priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
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|
2011-11-21 01:13:27 -07:00
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for (i = 0; i < priv->num_channels; i++) {
|
2015-04-17 08:32:11 -06:00
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priv->chan[i].reg = priv->reg + stride * (i + 1);
|
2011-12-12 13:59:11 -07:00
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if (!priv->irq[1] || !(i & 1))
|
2011-11-21 01:13:27 -07:00
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priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
|
2011-11-21 01:13:27 -07:00
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|
2009-08-12 19:50:38 -06:00
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spin_lock_init(&priv->chan[i].head_lock);
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spin_lock_init(&priv->chan[i].tail_lock);
|
2008-06-23 05:50:15 -06:00
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|
2009-08-12 19:50:38 -06:00
|
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priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
|
|
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priv->fifo_len, GFP_KERNEL);
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if (!priv->chan[i].fifo) {
|
2008-06-23 05:50:15 -06:00
|
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|
dev_err(dev, "failed to allocate request fifo %d\n", i);
|
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|
err = -ENOMEM;
|
|
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|
goto err_out;
|
|
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|
}
|
|
|
|
|
2009-08-12 19:50:38 -06:00
|
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|
atomic_set(&priv->chan[i].submit_count,
|
|
|
|
-(priv->chfifo_len - 1));
|
2015-03-03 06:21:33 -07:00
|
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}
|
2008-06-23 05:50:15 -06:00
|
|
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|
2009-08-12 19:51:51 -06:00
|
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dma_set_mask(dev, DMA_BIT_MASK(36));
|
|
|
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|
2008-06-23 05:50:15 -06:00
|
|
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/* reset and initialize the h/w */
|
|
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|
err = init_device(dev);
|
|
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|
if (err) {
|
|
|
|
dev_err(dev, "failed to initialize device\n");
|
|
|
|
goto err_out;
|
|
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}
|
|
|
|
|
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/* register the RNG, if available */
|
|
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if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
|
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err = talitos_register_rng(dev);
|
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if (err) {
|
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dev_err(dev, "failed to register hwrng: %d\n", err);
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goto err_out;
|
|
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} else
|
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dev_info(dev, "hwrng\n");
|
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}
|
|
|
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|
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|
|
/* register crypto algorithms the device supports */
|
|
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for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
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if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
|
|
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struct talitos_crypto_alg *t_alg;
|
2015-07-30 03:53:22 -06:00
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struct crypto_alg *alg = NULL;
|
2008-06-23 05:50:15 -06:00
|
|
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|
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t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
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if (IS_ERR(t_alg)) {
|
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err = PTR_ERR(t_alg);
|
2011-12-12 13:59:10 -07:00
|
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|
if (err == -ENOTSUPP)
|
2011-11-21 01:13:25 -07:00
|
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|
continue;
|
2008-06-23 05:50:15 -06:00
|
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|
goto err_out;
|
|
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}
|
|
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|
|
2010-05-19 03:19:33 -06:00
|
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|
switch (t_alg->algt.type) {
|
|
|
|
case CRYPTO_ALG_TYPE_ABLKCIPHER:
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err = crypto_register_alg(
|
|
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&t_alg->algt.alg.crypto);
|
2015-07-30 03:53:22 -06:00
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alg = &t_alg->algt.alg.crypto;
|
2010-05-19 03:19:33 -06:00
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break;
|
2015-07-30 03:53:22 -06:00
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|
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case CRYPTO_ALG_TYPE_AEAD:
|
|
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|
err = crypto_register_aead(
|
|
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&t_alg->algt.alg.aead);
|
|
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alg = &t_alg->algt.alg.aead.base;
|
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|
break;
|
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|
|
2010-05-19 03:19:33 -06:00
|
|
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case CRYPTO_ALG_TYPE_AHASH:
|
|
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|
err = crypto_register_ahash(
|
|
|
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&t_alg->algt.alg.hash);
|
2015-07-30 03:53:22 -06:00
|
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|
alg = &t_alg->algt.alg.hash.halg.base;
|
2010-05-19 03:19:33 -06:00
|
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break;
|
|
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|
}
|
2008-06-23 05:50:15 -06:00
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "%s alg registration failed\n",
|
2015-07-30 03:53:22 -06:00
|
|
|
alg->cra_driver_name);
|
2008-06-23 05:50:15 -06:00
|
|
|
kfree(t_alg);
|
Revert "crypto: talitos - add IPsec ESN support"
This reverts commit e763eb699be723fb41af818118068c6b3afdaf8d.
Current IPsec ESN implementation for authencesn(cbc(aes), hmac(sha))
(separate encryption and integrity algorithms) does not conform
to RFC4303.
ICV is generated by hashing the sequence
SPI, SeqNum-High, SeqNum-Low, IV, Payload
instead of
SPI, SeqNum-Low, IV, Payload, SeqNum-High.
Cc: <stable@vger.kernel.org> # 3.8, 3.7
Reported-by: Chaoxing Lin <Chaoxing.Lin@ultra-3eti.com>
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-03-20 08:31:38 -06:00
|
|
|
} else
|
2008-06-23 05:50:15 -06:00
|
|
|
list_add_tail(&t_alg->entry, &priv->alg_list);
|
|
|
|
}
|
|
|
|
}
|
2011-11-21 01:13:26 -07:00
|
|
|
if (!list_empty(&priv->alg_list))
|
|
|
|
dev_info(dev, "%s algorithms registered in /proc/crypto\n",
|
|
|
|
(char *)of_get_property(np, "compatible", NULL));
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out:
|
|
|
|
talitos_remove(ofdev);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2010-01-17 03:54:01 -07:00
|
|
|
static const struct of_device_id talitos_match[] = {
|
2015-04-17 08:32:20 -06:00
|
|
|
#ifdef CONFIG_CRYPTO_DEV_TALITOS1
|
|
|
|
{
|
|
|
|
.compatible = "fsl,sec1.0",
|
|
|
|
},
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_CRYPTO_DEV_TALITOS2
|
2008-06-23 05:50:15 -06:00
|
|
|
{
|
|
|
|
.compatible = "fsl,sec2.0",
|
|
|
|
},
|
2015-04-17 08:32:20 -06:00
|
|
|
#endif
|
2008-06-23 05:50:15 -06:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, talitos_match);
|
|
|
|
|
2011-02-17 02:43:24 -07:00
|
|
|
static struct platform_driver talitos_driver = {
|
2010-04-13 17:13:02 -06:00
|
|
|
.driver = {
|
|
|
|
.name = "talitos",
|
|
|
|
.of_match_table = talitos_match,
|
|
|
|
},
|
2008-06-23 05:50:15 -06:00
|
|
|
.probe = talitos_probe,
|
2008-11-22 10:34:24 -07:00
|
|
|
.remove = talitos_remove,
|
2008-06-23 05:50:15 -06:00
|
|
|
};
|
|
|
|
|
2011-11-26 06:26:19 -07:00
|
|
|
module_platform_driver(talitos_driver);
|
2008-06-23 05:50:15 -06:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
|
|
|
|
MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
|