2016-06-09 07:29:05 -06:00
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/*
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* Maxim MAX77620 Watchdog Driver
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*
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* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Laxman Dewangan <ldewangan@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mfd/max77620.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/watchdog.h>
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static bool nowayout = WATCHDOG_NOWAYOUT;
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struct max77620_wdt {
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struct device *dev;
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struct regmap *rmap;
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struct watchdog_device wdt_dev;
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};
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static int max77620_wdt_start(struct watchdog_device *wdt_dev)
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{
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struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
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return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
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MAX77620_WDTEN, MAX77620_WDTEN);
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}
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static int max77620_wdt_stop(struct watchdog_device *wdt_dev)
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{
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struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
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return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
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MAX77620_WDTEN, 0);
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}
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static int max77620_wdt_ping(struct watchdog_device *wdt_dev)
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{
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struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
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return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL3,
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MAX77620_WDTC_MASK, 0x1);
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}
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static int max77620_wdt_set_timeout(struct watchdog_device *wdt_dev,
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unsigned int timeout)
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{
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struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
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unsigned int wdt_timeout;
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u8 regval;
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int ret;
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switch (timeout) {
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case 0 ... 2:
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regval = MAX77620_TWD_2s;
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wdt_timeout = 2;
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break;
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case 3 ... 16:
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regval = MAX77620_TWD_16s;
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wdt_timeout = 16;
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break;
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case 17 ... 64:
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regval = MAX77620_TWD_64s;
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wdt_timeout = 64;
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break;
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default:
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regval = MAX77620_TWD_128s;
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wdt_timeout = 128;
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break;
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}
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ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL3,
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MAX77620_WDTC_MASK, 0x1);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
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MAX77620_TWD_MASK, regval);
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if (ret < 0)
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return ret;
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wdt_dev->timeout = wdt_timeout;
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return 0;
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}
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static const struct watchdog_info max77620_wdt_info = {
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.identity = "max77620-watchdog",
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_ops max77620_wdt_ops = {
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.start = max77620_wdt_start,
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.stop = max77620_wdt_stop,
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.ping = max77620_wdt_ping,
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.set_timeout = max77620_wdt_set_timeout,
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};
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static int max77620_wdt_probe(struct platform_device *pdev)
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{
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struct max77620_wdt *wdt;
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struct watchdog_device *wdt_dev;
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unsigned int regval;
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int ret;
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->dev = &pdev->dev;
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wdt->rmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!wdt->rmap) {
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dev_err(wdt->dev, "Failed to get parent regmap\n");
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return -ENODEV;
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}
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wdt_dev = &wdt->wdt_dev;
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wdt_dev->info = &max77620_wdt_info;
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wdt_dev->ops = &max77620_wdt_ops;
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wdt_dev->min_timeout = 2;
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wdt_dev->max_timeout = 128;
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wdt_dev->max_hw_heartbeat_ms = 128 * 1000;
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platform_set_drvdata(pdev, wdt);
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/* Enable WD_RST_WK - WDT expire results in a restart */
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ret = regmap_update_bits(wdt->rmap, MAX77620_REG_ONOFFCNFG2,
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MAX77620_ONOFFCNFG2_WD_RST_WK,
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MAX77620_ONOFFCNFG2_WD_RST_WK);
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if (ret < 0) {
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dev_err(wdt->dev, "Failed to set WD_RST_WK: %d\n", ret);
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return ret;
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}
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/* Set WDT clear in OFF and sleep mode */
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ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
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MAX77620_WDTOFFC | MAX77620_WDTSLPC,
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MAX77620_WDTOFFC | MAX77620_WDTSLPC);
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if (ret < 0) {
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dev_err(wdt->dev, "Failed to set WDT OFF mode: %d\n", ret);
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return ret;
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}
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/* Check if WDT running and if yes then set flags properly */
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ret = regmap_read(wdt->rmap, MAX77620_REG_CNFGGLBL2, ®val);
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if (ret < 0) {
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dev_err(wdt->dev, "Failed to read WDT CFG register: %d\n", ret);
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return ret;
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}
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switch (regval & MAX77620_TWD_MASK) {
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case MAX77620_TWD_2s:
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wdt_dev->timeout = 2;
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break;
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case MAX77620_TWD_16s:
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wdt_dev->timeout = 16;
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break;
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case MAX77620_TWD_64s:
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wdt_dev->timeout = 64;
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break;
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default:
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wdt_dev->timeout = 128;
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break;
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}
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if (regval & MAX77620_WDTEN)
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set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
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watchdog_set_nowayout(wdt_dev, nowayout);
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watchdog_set_drvdata(wdt_dev, wdt);
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ret = watchdog_register_device(wdt_dev);
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if (ret < 0) {
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dev_err(&pdev->dev, "watchdog registration failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int max77620_wdt_remove(struct platform_device *pdev)
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{
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struct max77620_wdt *wdt = platform_get_drvdata(pdev);
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max77620_wdt_stop(&wdt->wdt_dev);
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watchdog_unregister_device(&wdt->wdt_dev);
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return 0;
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}
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2017-08-13 05:28:28 -06:00
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static const struct platform_device_id max77620_wdt_devtype[] = {
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2016-06-09 07:29:05 -06:00
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{ .name = "max77620-watchdog", },
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{ },
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};
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2016-10-14 09:23:51 -06:00
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MODULE_DEVICE_TABLE(platform, max77620_wdt_devtype);
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2016-06-09 07:29:05 -06:00
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static struct platform_driver max77620_wdt_driver = {
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.driver = {
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.name = "max77620-watchdog",
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},
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.probe = max77620_wdt_probe,
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.remove = max77620_wdt_remove,
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.id_table = max77620_wdt_devtype,
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};
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module_platform_driver(max77620_wdt_driver);
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MODULE_DESCRIPTION("Max77620 watchdog timer driver");
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
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"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
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MODULE_LICENSE("GPL v2");
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