2011-09-19 07:34:00 -06:00
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/*
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* Register cache access API
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*
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* Copyright 2011 Wolfson Microelectronics plc
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*
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* Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2011-10-04 15:05:47 -06:00
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#include <linux/bsearch.h>
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2014-10-09 03:02:52 -06:00
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/slab.h>
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2011-10-03 03:50:14 -06:00
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#include <linux/sort.h>
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2011-09-19 07:34:00 -06:00
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2015-03-19 15:50:47 -06:00
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#include "trace.h"
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2011-09-19 07:34:00 -06:00
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#include "internal.h"
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static const struct regcache_ops *cache_types[] = {
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2011-09-19 07:34:02 -06:00
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®cache_rbtree_ops,
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2017-06-08 08:43:19 -06:00
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#if IS_ENABLED(CONFIG_REGCACHE_COMPRESSED)
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2011-09-19 07:34:03 -06:00
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®cache_lzo_ops,
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2017-06-02 07:15:37 -06:00
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#endif
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2012-12-19 07:51:55 -07:00
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®cache_flat_ops,
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2011-09-19 07:34:00 -06:00
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};
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static int regcache_hw_init(struct regmap *map)
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{
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int i, j;
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int ret;
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int count;
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2016-02-02 05:16:51 -07:00
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unsigned int reg, val;
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2011-09-19 07:34:00 -06:00
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void *tmp_buf;
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if (!map->num_reg_defaults_raw)
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return -EINVAL;
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2014-10-09 03:02:57 -06:00
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/* calculate the size of reg_defaults */
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for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
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2016-07-29 15:42:12 -06:00
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if (regmap_readable(map, i * map->reg_stride) &&
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!regmap_volatile(map, i * map->reg_stride))
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2014-10-09 03:02:57 -06:00
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count++;
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2016-07-29 15:42:12 -06:00
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/* all registers are unreadable or volatile, so just bypass */
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2014-10-09 03:02:57 -06:00
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if (!count) {
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map->cache_bypass = true;
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return 0;
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}
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map->num_reg_defaults = count;
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map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
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GFP_KERNEL);
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if (!map->reg_defaults)
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return -ENOMEM;
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2011-09-19 07:34:00 -06:00
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if (!map->reg_defaults_raw) {
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2015-09-26 16:04:07 -06:00
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bool cache_bypass = map->cache_bypass;
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2011-09-19 07:34:00 -06:00
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dev_warn(map->dev, "No cache defaults, reading back from HW\n");
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2012-02-17 06:27:26 -07:00
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2016-01-13 14:41:12 -07:00
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/* Bypass the cache access till data read from HW */
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2015-09-26 16:04:07 -06:00
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map->cache_bypass = true;
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2011-09-19 07:34:00 -06:00
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tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
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2014-10-09 03:02:57 -06:00
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if (!tmp_buf) {
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ret = -ENOMEM;
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goto err_free;
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}
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2013-02-21 11:39:47 -07:00
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ret = regmap_raw_read(map, 0, tmp_buf,
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2016-01-13 14:41:12 -07:00
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map->cache_size_raw);
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2012-02-17 06:27:26 -07:00
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map->cache_bypass = cache_bypass;
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2016-02-02 05:16:51 -07:00
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if (ret == 0) {
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map->reg_defaults_raw = tmp_buf;
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map->cache_free = 1;
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} else {
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kfree(tmp_buf);
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}
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2011-09-19 07:34:00 -06:00
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}
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/* fill the reg_defaults */
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for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
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2016-02-02 05:16:51 -07:00
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reg = i * map->reg_stride;
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if (!regmap_readable(map, reg))
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continue;
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if (regmap_volatile(map, reg))
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2011-09-19 07:34:00 -06:00
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continue;
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2016-02-02 05:16:51 -07:00
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if (map->reg_defaults_raw) {
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val = regcache_get_val(map, map->reg_defaults_raw, i);
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} else {
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bool cache_bypass = map->cache_bypass;
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map->cache_bypass = true;
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ret = regmap_read(map, reg, &val);
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map->cache_bypass = cache_bypass;
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if (ret != 0) {
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dev_err(map->dev, "Failed to read %d: %d\n",
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reg, ret);
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goto err_free;
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}
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}
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map->reg_defaults[j].reg = reg;
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2011-09-19 07:34:00 -06:00
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map->reg_defaults[j].def = val;
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j++;
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}
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return 0;
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2011-11-14 02:40:16 -07:00
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err_free:
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2014-10-09 03:02:57 -06:00
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kfree(map->reg_defaults);
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2011-11-14 02:40:16 -07:00
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return ret;
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2011-09-19 07:34:00 -06:00
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}
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2011-11-16 08:28:16 -07:00
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int regcache_init(struct regmap *map, const struct regmap_config *config)
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2011-09-19 07:34:00 -06:00
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{
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int ret;
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int i;
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void *tmp_buf;
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2011-09-19 09:08:03 -06:00
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if (map->cache_type == REGCACHE_NONE) {
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2015-12-10 20:23:19 -07:00
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if (config->reg_defaults || config->num_reg_defaults_raw)
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dev_warn(map->dev,
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"No cache used with register defaults set!\n");
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2011-09-19 09:08:03 -06:00
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map->cache_bypass = true;
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2011-09-19 07:34:00 -06:00
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return 0;
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2011-09-19 09:08:03 -06:00
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}
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2011-09-19 07:34:00 -06:00
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2015-12-10 20:23:20 -07:00
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if (config->reg_defaults && !config->num_reg_defaults) {
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dev_err(map->dev,
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"Register defaults are set without the number!\n");
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return -EINVAL;
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}
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2015-12-10 20:23:19 -07:00
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for (i = 0; i < config->num_reg_defaults; i++)
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if (config->reg_defaults[i].reg % map->reg_stride)
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return -EINVAL;
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2011-09-19 07:34:00 -06:00
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for (i = 0; i < ARRAY_SIZE(cache_types); i++)
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if (cache_types[i]->type == map->cache_type)
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break;
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if (i == ARRAY_SIZE(cache_types)) {
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dev_err(map->dev, "Could not match compress type: %d\n",
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map->cache_type);
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return -EINVAL;
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}
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2011-11-16 08:28:16 -07:00
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map->num_reg_defaults = config->num_reg_defaults;
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map->num_reg_defaults_raw = config->num_reg_defaults_raw;
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map->reg_defaults_raw = config->reg_defaults_raw;
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2011-11-16 12:34:03 -07:00
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map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
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map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
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2011-11-16 08:28:16 -07:00
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2011-09-19 07:34:00 -06:00
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map->cache = NULL;
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map->cache_ops = cache_types[i];
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if (!map->cache_ops->read ||
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!map->cache_ops->write ||
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!map->cache_ops->name)
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return -EINVAL;
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/* We still need to ensure that the reg_defaults
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* won't vanish from under us. We'll need to make
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* a copy of it.
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*/
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2011-11-16 08:28:17 -07:00
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if (config->reg_defaults) {
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tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
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2011-09-19 07:34:00 -06:00
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sizeof(struct reg_default), GFP_KERNEL);
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if (!tmp_buf)
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return -ENOMEM;
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map->reg_defaults = tmp_buf;
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2011-10-09 06:13:58 -06:00
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} else if (map->num_reg_defaults_raw) {
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2011-09-29 08:24:54 -06:00
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/* Some devices such as PMICs don't have cache defaults,
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2011-09-19 07:34:00 -06:00
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* we cope with this by reading back the HW registers and
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* crafting the cache defaults by hand.
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*/
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ret = regcache_hw_init(map);
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if (ret < 0)
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return ret;
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2014-10-09 03:02:57 -06:00
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if (map->cache_bypass)
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return 0;
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2011-09-19 07:34:00 -06:00
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}
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if (!map->max_register)
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map->max_register = map->num_reg_defaults_raw;
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if (map->cache_ops->init) {
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dev_dbg(map->dev, "Initializing %s cache\n",
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map->cache_ops->name);
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2011-11-14 02:40:17 -07:00
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ret = map->cache_ops->init(map);
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if (ret)
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goto err_free;
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2011-09-19 07:34:00 -06:00
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}
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return 0;
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2011-11-14 02:40:17 -07:00
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err_free:
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kfree(map->reg_defaults);
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if (map->cache_free)
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kfree(map->reg_defaults_raw);
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return ret;
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2011-09-19 07:34:00 -06:00
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}
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void regcache_exit(struct regmap *map)
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{
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if (map->cache_type == REGCACHE_NONE)
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return;
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BUG_ON(!map->cache_ops);
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kfree(map->reg_defaults);
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if (map->cache_free)
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kfree(map->reg_defaults_raw);
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if (map->cache_ops->exit) {
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dev_dbg(map->dev, "Destroying %s cache\n",
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map->cache_ops->name);
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map->cache_ops->exit(map);
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}
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}
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/**
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2017-01-12 04:17:39 -07:00
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* regcache_read - Fetch the value of a given register from the cache.
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2011-09-19 07:34:00 -06:00
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*
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* @map: map to configure.
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* @reg: The register index.
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* @value: The value to be returned.
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*
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* Return a negative value on failure, 0 on success.
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*/
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int regcache_read(struct regmap *map,
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unsigned int reg, unsigned int *value)
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{
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2011-11-30 07:27:08 -07:00
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int ret;
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2011-09-19 07:34:00 -06:00
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if (map->cache_type == REGCACHE_NONE)
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return -ENOSYS;
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BUG_ON(!map->cache_ops);
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2011-11-30 07:27:08 -07:00
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if (!regmap_volatile(map, reg)) {
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ret = map->cache_ops->read(map, reg, value);
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if (ret == 0)
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2015-03-09 05:20:13 -06:00
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trace_regmap_reg_read_cache(map, reg, *value);
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2011-11-30 07:27:08 -07:00
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return ret;
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}
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2011-09-19 07:34:00 -06:00
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return -EINVAL;
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}
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/**
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2017-01-12 04:17:39 -07:00
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* regcache_write - Set the value of a given register in the cache.
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2011-09-19 07:34:00 -06:00
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*
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* @map: map to configure.
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* @reg: The register index.
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* @value: The new register value.
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*
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* Return a negative value on failure, 0 on success.
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*/
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int regcache_write(struct regmap *map,
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unsigned int reg, unsigned int value)
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{
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if (map->cache_type == REGCACHE_NONE)
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return 0;
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BUG_ON(!map->cache_ops);
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if (!regmap_volatile(map, reg))
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return map->cache_ops->write(map, reg, value);
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return 0;
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}
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2015-05-05 16:14:13 -06:00
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static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
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unsigned int val)
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{
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int ret;
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2015-05-05 16:14:14 -06:00
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/* If we don't know the chip just got reset, then sync everything. */
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if (!map->no_sync_defaults)
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return true;
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2015-05-05 16:14:13 -06:00
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/* Is this the hardware default? If so skip. */
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ret = regcache_lookup_reg(map, reg);
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if (ret >= 0 && val == map->reg_defaults[ret].def)
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return false;
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return true;
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}
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2013-06-02 16:15:26 -06:00
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static int regcache_default_sync(struct regmap *map, unsigned int min,
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unsigned int max)
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{
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unsigned int reg;
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|
2014-03-18 14:45:08 -06:00
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for (reg = min; reg <= max; reg += map->reg_stride) {
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2013-06-02 16:15:26 -06:00
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unsigned int val;
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int ret;
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2014-03-18 14:45:09 -06:00
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if (regmap_volatile(map, reg) ||
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!regmap_writeable(map, reg))
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2013-06-02 16:15:26 -06:00
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continue;
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ret = regcache_read(map, reg, &val);
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if (ret)
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return ret;
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|
2015-05-05 16:14:13 -06:00
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if (!regcache_reg_needs_sync(map, reg, val))
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2013-06-02 16:15:26 -06:00
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continue;
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2015-09-26 16:04:07 -06:00
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map->cache_bypass = true;
|
2013-06-02 16:15:26 -06:00
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ret = _regmap_write(map, reg, val);
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2015-09-26 16:04:07 -06:00
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map->cache_bypass = false;
|
2014-09-16 05:04:14 -06:00
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if (ret) {
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dev_err(map->dev, "Unable to sync register %#x. %d\n",
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reg, ret);
|
2013-06-02 16:15:26 -06:00
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return ret;
|
2014-09-16 05:04:14 -06:00
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}
|
2013-06-02 16:15:26 -06:00
|
|
|
dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-09-19 07:34:00 -06:00
|
|
|
/**
|
2017-01-12 04:17:39 -07:00
|
|
|
* regcache_sync - Sync the register cache with the hardware.
|
2011-09-19 07:34:00 -06:00
|
|
|
*
|
|
|
|
* @map: map to configure.
|
|
|
|
*
|
|
|
|
* Any registers that should not be synced should be marked as
|
|
|
|
* volatile. In general drivers can choose not to use the provided
|
|
|
|
* syncing functionality if they so require.
|
|
|
|
*
|
|
|
|
* Return a negative value on failure, 0 on success.
|
|
|
|
*/
|
|
|
|
int regcache_sync(struct regmap *map)
|
|
|
|
{
|
2011-09-27 04:25:06 -06:00
|
|
|
int ret = 0;
|
|
|
|
unsigned int i;
|
2011-09-19 07:34:04 -06:00
|
|
|
const char *name;
|
2015-09-26 16:04:07 -06:00
|
|
|
bool bypass;
|
2011-09-19 07:34:04 -06:00
|
|
|
|
2013-06-02 16:15:26 -06:00
|
|
|
BUG_ON(!map->cache_ops);
|
2011-09-19 07:34:00 -06:00
|
|
|
|
2013-05-23 07:06:15 -06:00
|
|
|
map->lock(map->lock_arg);
|
2011-09-29 07:36:26 -06:00
|
|
|
/* Remember the initial bypass state */
|
|
|
|
bypass = map->cache_bypass;
|
2011-09-27 04:25:06 -06:00
|
|
|
dev_dbg(map->dev, "Syncing %s cache\n",
|
|
|
|
map->cache_ops->name);
|
|
|
|
name = map->cache_ops->name;
|
2015-03-09 05:20:13 -06:00
|
|
|
trace_regcache_sync(map, name, "start");
|
2012-01-21 05:01:14 -07:00
|
|
|
|
2011-10-26 02:34:22 -06:00
|
|
|
if (!map->cache_dirty)
|
|
|
|
goto out;
|
2012-01-25 14:06:33 -07:00
|
|
|
|
2013-10-10 14:06:32 -06:00
|
|
|
map->async = true;
|
|
|
|
|
2012-01-21 05:01:14 -07:00
|
|
|
/* Apply any patch first */
|
2015-09-26 16:04:07 -06:00
|
|
|
map->cache_bypass = true;
|
2012-01-21 05:01:14 -07:00
|
|
|
for (i = 0; i < map->patch_regs; i++) {
|
|
|
|
ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
|
|
|
|
if (ret != 0) {
|
|
|
|
dev_err(map->dev, "Failed to write %x = %x: %d\n",
|
|
|
|
map->patch[i].reg, map->patch[i].def, ret);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
2015-09-26 16:04:07 -06:00
|
|
|
map->cache_bypass = false;
|
2012-01-21 05:01:14 -07:00
|
|
|
|
2013-06-02 16:15:26 -06:00
|
|
|
if (map->cache_ops->sync)
|
|
|
|
ret = map->cache_ops->sync(map, 0, map->max_register);
|
|
|
|
else
|
|
|
|
ret = regcache_default_sync(map, 0, map->max_register);
|
2011-09-27 04:25:06 -06:00
|
|
|
|
2012-02-23 15:05:59 -07:00
|
|
|
if (ret == 0)
|
|
|
|
map->cache_dirty = false;
|
2011-09-27 04:25:06 -06:00
|
|
|
|
|
|
|
out:
|
2011-09-29 07:36:26 -06:00
|
|
|
/* Restore the bypass state */
|
2013-10-10 14:06:32 -06:00
|
|
|
map->async = false;
|
2011-09-29 07:36:26 -06:00
|
|
|
map->cache_bypass = bypass;
|
2015-05-05 16:14:14 -06:00
|
|
|
map->no_sync_defaults = false;
|
2013-05-23 07:06:15 -06:00
|
|
|
map->unlock(map->lock_arg);
|
2011-09-27 04:25:06 -06:00
|
|
|
|
2013-10-10 14:06:32 -06:00
|
|
|
regmap_async_complete(map);
|
|
|
|
|
2015-03-09 05:20:13 -06:00
|
|
|
trace_regcache_sync(map, name, "stop");
|
2013-10-10 14:06:32 -06:00
|
|
|
|
2011-09-27 04:25:06 -06:00
|
|
|
return ret;
|
2011-09-19 07:34:00 -06:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(regcache_sync);
|
|
|
|
|
2012-02-23 13:53:37 -07:00
|
|
|
/**
|
2017-01-12 04:17:39 -07:00
|
|
|
* regcache_sync_region - Sync part of the register cache with the hardware.
|
2012-02-23 13:53:37 -07:00
|
|
|
*
|
|
|
|
* @map: map to sync.
|
|
|
|
* @min: first register to sync
|
|
|
|
* @max: last register to sync
|
|
|
|
*
|
|
|
|
* Write all non-default register values in the specified region to
|
|
|
|
* the hardware.
|
|
|
|
*
|
|
|
|
* Return a negative value on failure, 0 on success.
|
|
|
|
*/
|
|
|
|
int regcache_sync_region(struct regmap *map, unsigned int min,
|
|
|
|
unsigned int max)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
const char *name;
|
2015-09-26 16:04:07 -06:00
|
|
|
bool bypass;
|
2012-02-23 13:53:37 -07:00
|
|
|
|
2013-06-02 16:15:26 -06:00
|
|
|
BUG_ON(!map->cache_ops);
|
2012-02-23 13:53:37 -07:00
|
|
|
|
2013-05-23 07:06:15 -06:00
|
|
|
map->lock(map->lock_arg);
|
2012-02-23 13:53:37 -07:00
|
|
|
|
|
|
|
/* Remember the initial bypass state */
|
|
|
|
bypass = map->cache_bypass;
|
|
|
|
|
|
|
|
name = map->cache_ops->name;
|
|
|
|
dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
|
|
|
|
|
2015-03-09 05:20:13 -06:00
|
|
|
trace_regcache_sync(map, name, "start region");
|
2012-02-23 13:53:37 -07:00
|
|
|
|
|
|
|
if (!map->cache_dirty)
|
|
|
|
goto out;
|
|
|
|
|
2013-10-10 14:06:32 -06:00
|
|
|
map->async = true;
|
|
|
|
|
2013-06-02 16:15:26 -06:00
|
|
|
if (map->cache_ops->sync)
|
|
|
|
ret = map->cache_ops->sync(map, min, max);
|
|
|
|
else
|
|
|
|
ret = regcache_default_sync(map, min, max);
|
2012-02-23 13:53:37 -07:00
|
|
|
|
|
|
|
out:
|
|
|
|
/* Restore the bypass state */
|
|
|
|
map->cache_bypass = bypass;
|
2013-10-10 14:06:32 -06:00
|
|
|
map->async = false;
|
2015-05-05 16:14:14 -06:00
|
|
|
map->no_sync_defaults = false;
|
2013-05-23 07:06:15 -06:00
|
|
|
map->unlock(map->lock_arg);
|
2012-02-23 13:53:37 -07:00
|
|
|
|
2013-10-10 14:06:32 -06:00
|
|
|
regmap_async_complete(map);
|
|
|
|
|
2015-03-09 05:20:13 -06:00
|
|
|
trace_regcache_sync(map, name, "stop region");
|
2013-10-10 14:06:32 -06:00
|
|
|
|
2012-02-23 13:53:37 -07:00
|
|
|
return ret;
|
|
|
|
}
|
2012-04-03 06:08:53 -06:00
|
|
|
EXPORT_SYMBOL_GPL(regcache_sync_region);
|
2012-02-23 13:53:37 -07:00
|
|
|
|
2013-05-08 06:55:22 -06:00
|
|
|
/**
|
2017-01-12 04:17:39 -07:00
|
|
|
* regcache_drop_region - Discard part of the register cache
|
2013-05-08 06:55:22 -06:00
|
|
|
*
|
|
|
|
* @map: map to operate on
|
|
|
|
* @min: first register to discard
|
|
|
|
* @max: last register to discard
|
|
|
|
*
|
|
|
|
* Discard part of the register cache.
|
|
|
|
*
|
|
|
|
* Return a negative value on failure, 0 on success.
|
|
|
|
*/
|
|
|
|
int regcache_drop_region(struct regmap *map, unsigned int min,
|
|
|
|
unsigned int max)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
2013-08-29 02:26:34 -06:00
|
|
|
if (!map->cache_ops || !map->cache_ops->drop)
|
2013-05-08 06:55:22 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
2013-05-23 07:06:15 -06:00
|
|
|
map->lock(map->lock_arg);
|
2013-05-08 06:55:22 -06:00
|
|
|
|
2015-03-09 05:20:13 -06:00
|
|
|
trace_regcache_drop_region(map, min, max);
|
2013-05-08 06:55:22 -06:00
|
|
|
|
2013-08-29 02:26:34 -06:00
|
|
|
ret = map->cache_ops->drop(map, min, max);
|
2013-05-08 06:55:22 -06:00
|
|
|
|
2013-05-23 07:06:15 -06:00
|
|
|
map->unlock(map->lock_arg);
|
2013-05-08 06:55:22 -06:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(regcache_drop_region);
|
|
|
|
|
2011-09-19 11:22:14 -06:00
|
|
|
/**
|
2017-01-12 04:17:39 -07:00
|
|
|
* regcache_cache_only - Put a register map into cache only mode
|
2011-09-19 11:22:14 -06:00
|
|
|
*
|
|
|
|
* @map: map to configure
|
2017-01-12 04:17:39 -07:00
|
|
|
* @enable: flag if changes should be written to the hardware
|
2011-09-19 11:22:14 -06:00
|
|
|
*
|
|
|
|
* When a register map is marked as cache only writes to the register
|
|
|
|
* map API will only update the register cache, they will not cause
|
|
|
|
* any hardware changes. This is useful for allowing portions of
|
|
|
|
* drivers to act as though the device were functioning as normal when
|
|
|
|
* it is disabled for power saving reasons.
|
|
|
|
*/
|
|
|
|
void regcache_cache_only(struct regmap *map, bool enable)
|
|
|
|
{
|
2013-05-23 07:06:15 -06:00
|
|
|
map->lock(map->lock_arg);
|
2011-09-29 07:36:28 -06:00
|
|
|
WARN_ON(map->cache_bypass && enable);
|
2011-09-19 11:22:14 -06:00
|
|
|
map->cache_only = enable;
|
2015-03-09 05:20:13 -06:00
|
|
|
trace_regmap_cache_only(map, enable);
|
2013-05-23 07:06:15 -06:00
|
|
|
map->unlock(map->lock_arg);
|
2011-09-19 11:22:14 -06:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(regcache_cache_only);
|
|
|
|
|
2011-10-26 02:34:22 -06:00
|
|
|
/**
|
2017-01-12 04:17:39 -07:00
|
|
|
* regcache_mark_dirty - Indicate that HW registers were reset to default values
|
2011-10-26 02:34:22 -06:00
|
|
|
*
|
|
|
|
* @map: map to mark
|
|
|
|
*
|
2015-05-05 16:14:14 -06:00
|
|
|
* Inform regcache that the device has been powered down or reset, so that
|
|
|
|
* on resume, regcache_sync() knows to write out all non-default values
|
|
|
|
* stored in the cache.
|
|
|
|
*
|
|
|
|
* If this function is not called, regcache_sync() will assume that
|
|
|
|
* the hardware state still matches the cache state, modulo any writes that
|
|
|
|
* happened when cache_only was true.
|
2011-10-26 02:34:22 -06:00
|
|
|
*/
|
|
|
|
void regcache_mark_dirty(struct regmap *map)
|
|
|
|
{
|
2013-05-23 07:06:15 -06:00
|
|
|
map->lock(map->lock_arg);
|
2011-10-26 02:34:22 -06:00
|
|
|
map->cache_dirty = true;
|
2015-05-05 16:14:14 -06:00
|
|
|
map->no_sync_defaults = true;
|
2013-05-23 07:06:15 -06:00
|
|
|
map->unlock(map->lock_arg);
|
2011-10-26 02:34:22 -06:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(regcache_mark_dirty);
|
|
|
|
|
2011-09-29 07:36:27 -06:00
|
|
|
/**
|
2017-01-12 04:17:39 -07:00
|
|
|
* regcache_cache_bypass - Put a register map into cache bypass mode
|
2011-09-29 07:36:27 -06:00
|
|
|
*
|
|
|
|
* @map: map to configure
|
2017-01-12 04:17:39 -07:00
|
|
|
* @enable: flag if changes should not be written to the cache
|
2011-09-29 07:36:27 -06:00
|
|
|
*
|
|
|
|
* When a register map is marked with the cache bypass option, writes
|
|
|
|
* to the register map API will only update the hardware and not the
|
|
|
|
* the cache directly. This is useful when syncing the cache back to
|
|
|
|
* the hardware.
|
|
|
|
*/
|
|
|
|
void regcache_cache_bypass(struct regmap *map, bool enable)
|
|
|
|
{
|
2013-05-23 07:06:15 -06:00
|
|
|
map->lock(map->lock_arg);
|
2011-09-29 07:36:28 -06:00
|
|
|
WARN_ON(map->cache_only && enable);
|
2011-09-29 07:36:27 -06:00
|
|
|
map->cache_bypass = enable;
|
2015-03-09 05:20:13 -06:00
|
|
|
trace_regmap_cache_bypass(map, enable);
|
2013-05-23 07:06:15 -06:00
|
|
|
map->unlock(map->lock_arg);
|
2011-09-29 07:36:27 -06:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(regcache_cache_bypass);
|
|
|
|
|
2013-02-21 11:03:13 -07:00
|
|
|
bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
|
|
|
|
unsigned int val)
|
2011-09-19 07:34:00 -06:00
|
|
|
{
|
2013-02-21 11:07:01 -07:00
|
|
|
if (regcache_get_val(map, base, idx) == val)
|
|
|
|
return true;
|
|
|
|
|
2013-02-21 11:39:47 -07:00
|
|
|
/* Use device native format if possible */
|
|
|
|
if (map->format.format_val) {
|
|
|
|
map->format.format_val(base + (map->cache_word_size * idx),
|
|
|
|
val, 0);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-02-21 11:03:13 -07:00
|
|
|
switch (map->cache_word_size) {
|
2011-09-19 07:34:00 -06:00
|
|
|
case 1: {
|
|
|
|
u8 *cache = base;
|
2015-12-08 22:09:06 -07:00
|
|
|
|
2011-09-19 07:34:00 -06:00
|
|
|
cache[idx] = val;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: {
|
|
|
|
u16 *cache = base;
|
2015-12-08 22:09:06 -07:00
|
|
|
|
2011-09-19 07:34:00 -06:00
|
|
|
cache[idx] = val;
|
|
|
|
break;
|
|
|
|
}
|
2012-02-17 16:58:25 -07:00
|
|
|
case 4: {
|
|
|
|
u32 *cache = base;
|
2015-12-08 22:09:06 -07:00
|
|
|
|
2012-02-17 16:58:25 -07:00
|
|
|
cache[idx] = val;
|
|
|
|
break;
|
|
|
|
}
|
2015-12-08 22:09:07 -07:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
case 8: {
|
|
|
|
u64 *cache = base;
|
|
|
|
|
2012-02-17 16:58:25 -07:00
|
|
|
cache[idx] = val;
|
|
|
|
break;
|
|
|
|
}
|
2015-12-08 22:09:07 -07:00
|
|
|
#endif
|
2011-09-19 07:34:00 -06:00
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-02-21 11:03:13 -07:00
|
|
|
unsigned int regcache_get_val(struct regmap *map, const void *base,
|
|
|
|
unsigned int idx)
|
2011-09-19 07:34:00 -06:00
|
|
|
{
|
|
|
|
if (!base)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2013-02-21 11:39:47 -07:00
|
|
|
/* Use device native format if possible */
|
|
|
|
if (map->format.parse_val)
|
2013-03-13 13:29:36 -06:00
|
|
|
return map->format.parse_val(regcache_get_val_addr(map, base,
|
|
|
|
idx));
|
2013-02-21 11:39:47 -07:00
|
|
|
|
2013-02-21 11:03:13 -07:00
|
|
|
switch (map->cache_word_size) {
|
2011-09-19 07:34:00 -06:00
|
|
|
case 1: {
|
|
|
|
const u8 *cache = base;
|
2015-12-08 22:09:06 -07:00
|
|
|
|
2011-09-19 07:34:00 -06:00
|
|
|
return cache[idx];
|
|
|
|
}
|
|
|
|
case 2: {
|
|
|
|
const u16 *cache = base;
|
2015-12-08 22:09:06 -07:00
|
|
|
|
2011-09-19 07:34:00 -06:00
|
|
|
return cache[idx];
|
|
|
|
}
|
2012-02-17 16:58:25 -07:00
|
|
|
case 4: {
|
|
|
|
const u32 *cache = base;
|
2015-12-08 22:09:06 -07:00
|
|
|
|
2012-02-17 16:58:25 -07:00
|
|
|
return cache[idx];
|
|
|
|
}
|
2015-12-08 22:09:07 -07:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
case 8: {
|
|
|
|
const u64 *cache = base;
|
|
|
|
|
2012-02-17 16:58:25 -07:00
|
|
|
return cache[idx];
|
|
|
|
}
|
2015-12-08 22:09:07 -07:00
|
|
|
#endif
|
2011-09-19 07:34:00 -06:00
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
/* unreachable */
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2011-10-04 15:05:47 -06:00
|
|
|
static int regcache_default_cmp(const void *a, const void *b)
|
2011-10-03 03:50:14 -06:00
|
|
|
{
|
|
|
|
const struct reg_default *_a = a;
|
|
|
|
const struct reg_default *_b = b;
|
|
|
|
|
|
|
|
return _a->reg - _b->reg;
|
|
|
|
}
|
|
|
|
|
2011-10-04 15:05:47 -06:00
|
|
|
int regcache_lookup_reg(struct regmap *map, unsigned int reg)
|
|
|
|
{
|
|
|
|
struct reg_default key;
|
|
|
|
struct reg_default *r;
|
|
|
|
|
|
|
|
key.reg = reg;
|
|
|
|
key.def = 0;
|
|
|
|
|
|
|
|
r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
|
|
|
|
sizeof(struct reg_default), regcache_default_cmp);
|
|
|
|
|
|
|
|
if (r)
|
|
|
|
return r - map->reg_defaults;
|
|
|
|
else
|
2011-10-09 06:23:31 -06:00
|
|
|
return -ENOENT;
|
2011-10-04 15:05:47 -06:00
|
|
|
}
|
2013-03-29 13:32:28 -06:00
|
|
|
|
2013-08-29 02:26:34 -06:00
|
|
|
static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
|
|
|
|
{
|
|
|
|
if (!cache_present)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return test_bit(idx, cache_present);
|
|
|
|
}
|
|
|
|
|
2013-03-29 14:12:21 -06:00
|
|
|
static int regcache_sync_block_single(struct regmap *map, void *block,
|
2013-08-29 02:26:34 -06:00
|
|
|
unsigned long *cache_present,
|
2013-03-29 14:12:21 -06:00
|
|
|
unsigned int block_base,
|
|
|
|
unsigned int start, unsigned int end)
|
|
|
|
{
|
|
|
|
unsigned int i, regtmp, val;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
for (i = start; i < end; i++) {
|
|
|
|
regtmp = block_base + (i * map->reg_stride);
|
|
|
|
|
2015-03-04 07:29:17 -07:00
|
|
|
if (!regcache_reg_present(cache_present, i) ||
|
|
|
|
!regmap_writeable(map, regtmp))
|
2013-03-29 14:12:21 -06:00
|
|
|
continue;
|
|
|
|
|
|
|
|
val = regcache_get_val(map, block, i);
|
2015-05-05 16:14:13 -06:00
|
|
|
if (!regcache_reg_needs_sync(map, regtmp, val))
|
2013-03-29 14:12:21 -06:00
|
|
|
continue;
|
|
|
|
|
2015-09-26 16:04:07 -06:00
|
|
|
map->cache_bypass = true;
|
2013-03-29 14:12:21 -06:00
|
|
|
|
|
|
|
ret = _regmap_write(map, regtmp, val);
|
|
|
|
|
2015-09-26 16:04:07 -06:00
|
|
|
map->cache_bypass = false;
|
2014-09-16 05:04:14 -06:00
|
|
|
if (ret != 0) {
|
|
|
|
dev_err(map->dev, "Unable to sync register %#x. %d\n",
|
|
|
|
regtmp, ret);
|
2013-03-29 14:12:21 -06:00
|
|
|
return ret;
|
2014-09-16 05:04:14 -06:00
|
|
|
}
|
2013-03-29 14:12:21 -06:00
|
|
|
dev_dbg(map->dev, "Synced register %#x, value %#x\n",
|
|
|
|
regtmp, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-03-29 14:50:07 -06:00
|
|
|
static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
|
|
|
|
unsigned int base, unsigned int cur)
|
|
|
|
{
|
|
|
|
size_t val_bytes = map->format.val_bytes;
|
|
|
|
int ret, count;
|
|
|
|
|
|
|
|
if (*data == NULL)
|
|
|
|
return 0;
|
|
|
|
|
2014-01-24 16:40:39 -07:00
|
|
|
count = (cur - base) / map->reg_stride;
|
2013-03-29 14:50:07 -06:00
|
|
|
|
2013-04-04 10:40:45 -06:00
|
|
|
dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
|
2014-01-24 16:40:39 -07:00
|
|
|
count * val_bytes, count, base, cur - map->reg_stride);
|
2013-03-29 14:50:07 -06:00
|
|
|
|
2015-09-26 16:04:07 -06:00
|
|
|
map->cache_bypass = true;
|
2013-03-29 14:50:07 -06:00
|
|
|
|
2013-10-09 05:28:52 -06:00
|
|
|
ret = _regmap_raw_write(map, base, *data, count * val_bytes);
|
2014-09-16 05:04:14 -06:00
|
|
|
if (ret)
|
|
|
|
dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
|
|
|
|
base, cur - map->reg_stride, ret);
|
2013-03-29 14:50:07 -06:00
|
|
|
|
2015-09-26 16:04:07 -06:00
|
|
|
map->cache_bypass = false;
|
2013-03-29 14:50:07 -06:00
|
|
|
|
|
|
|
*data = NULL;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-04-04 03:06:18 -06:00
|
|
|
static int regcache_sync_block_raw(struct regmap *map, void *block,
|
2013-08-29 02:26:34 -06:00
|
|
|
unsigned long *cache_present,
|
2013-03-29 14:12:21 -06:00
|
|
|
unsigned int block_base, unsigned int start,
|
|
|
|
unsigned int end)
|
2013-03-29 13:32:28 -06:00
|
|
|
{
|
2013-03-29 14:50:07 -06:00
|
|
|
unsigned int i, val;
|
|
|
|
unsigned int regtmp = 0;
|
|
|
|
unsigned int base = 0;
|
|
|
|
const void *data = NULL;
|
2013-03-29 13:32:28 -06:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
for (i = start; i < end; i++) {
|
|
|
|
regtmp = block_base + (i * map->reg_stride);
|
|
|
|
|
2015-03-04 07:29:17 -07:00
|
|
|
if (!regcache_reg_present(cache_present, i) ||
|
|
|
|
!regmap_writeable(map, regtmp)) {
|
2013-03-29 14:50:07 -06:00
|
|
|
ret = regcache_sync_block_raw_flush(map, &data,
|
|
|
|
base, regtmp);
|
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
2013-03-29 13:32:28 -06:00
|
|
|
continue;
|
2013-03-29 14:50:07 -06:00
|
|
|
}
|
2013-03-29 13:32:28 -06:00
|
|
|
|
|
|
|
val = regcache_get_val(map, block, i);
|
2015-05-05 16:14:13 -06:00
|
|
|
if (!regcache_reg_needs_sync(map, regtmp, val)) {
|
2013-03-29 14:50:07 -06:00
|
|
|
ret = regcache_sync_block_raw_flush(map, &data,
|
|
|
|
base, regtmp);
|
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
2013-03-29 13:32:28 -06:00
|
|
|
continue;
|
2013-03-29 14:50:07 -06:00
|
|
|
}
|
2013-03-29 13:32:28 -06:00
|
|
|
|
2013-03-29 14:50:07 -06:00
|
|
|
if (!data) {
|
|
|
|
data = regcache_get_val_addr(map, block, i);
|
|
|
|
base = regtmp;
|
|
|
|
}
|
2013-03-29 13:32:28 -06:00
|
|
|
}
|
|
|
|
|
2013-08-05 03:21:29 -06:00
|
|
|
return regcache_sync_block_raw_flush(map, &data, base, regtmp +
|
|
|
|
map->reg_stride);
|
2013-03-29 13:32:28 -06:00
|
|
|
}
|
2013-03-29 14:12:21 -06:00
|
|
|
|
|
|
|
int regcache_sync_block(struct regmap *map, void *block,
|
2013-08-29 02:26:34 -06:00
|
|
|
unsigned long *cache_present,
|
2013-03-29 14:12:21 -06:00
|
|
|
unsigned int block_base, unsigned int start,
|
|
|
|
unsigned int end)
|
|
|
|
{
|
2015-08-21 02:26:42 -06:00
|
|
|
if (regmap_can_raw_write(map) && !map->use_single_write)
|
2013-08-29 02:26:34 -06:00
|
|
|
return regcache_sync_block_raw(map, block, cache_present,
|
|
|
|
block_base, start, end);
|
2013-03-29 14:12:21 -06:00
|
|
|
else
|
2013-08-29 02:26:34 -06:00
|
|
|
return regcache_sync_block_single(map, block, cache_present,
|
|
|
|
block_base, start, end);
|
2013-03-29 14:12:21 -06:00
|
|
|
}
|