2018-05-09 12:06:04 -06:00
|
|
|
// SPDX-License-Identifier: GPL-2.0
|
|
|
|
/*
|
|
|
|
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
|
2014-11-03 11:07:35 -07:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/types.h>
|
|
|
|
#include <linux/device.h>
|
|
|
|
#include <linux/io.h>
|
|
|
|
#include <linux/err.h>
|
|
|
|
#include <linux/export.h>
|
|
|
|
#include <linux/slab.h>
|
2019-01-31 11:47:10 -07:00
|
|
|
#include <linux/stringhash.h>
|
2014-11-03 11:07:35 -07:00
|
|
|
#include <linux/mutex.h>
|
|
|
|
#include <linux/clk.h>
|
|
|
|
#include <linux/coresight.h>
|
|
|
|
#include <linux/of_platform.h>
|
|
|
|
#include <linux/delay.h>
|
2016-02-17 17:51:47 -07:00
|
|
|
#include <linux/pm_runtime.h>
|
2014-11-03 11:07:35 -07:00
|
|
|
|
coresight: perf: Add "sinks" group to PMU directory
Add a "sinks" directory entry so that users can see all the sinks
available in the system in a single place. Individual sink are added
as they are registered with the coresight bus.
Committer tests:
Test built on a ubuntu 18.04 container with a cross build environment to
arm64, the new field is there, need to find a machine with this feature
to do further testing in the future.
root@d15263e5734a:/git/perf# grep CORESIGHT /tmp/build/v5.0-rc2+/.config
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINKS_AND_SINKS=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_CATU=y
CONFIG_CORESIGHT_SINK_TPIU=y
CONFIG_CORESIGHT_SINK_ETBV10=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CPU_DEBUG=m
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# file /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/*.o
.../coresight/coresight-catu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.mod.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-dynamic-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etb10.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm-perf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x-sysfs.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-funnel.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-stm.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etr.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tpiu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/of_coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# pahole -C coresight_device /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/coresight.o
struct coresight_device {
struct coresight_connection * conns; /* 0 8 */
int nr_inport; /* 8 4 */
int nr_outport; /* 12 4 */
enum coresight_dev_type type; /* 16 4 */
union coresight_dev_subtype subtype; /* 20 8 */
/* XXX 4 bytes hole, try to pack */
const struct coresight_ops * ops; /* 32 8 */
struct device dev; /* 40 1408 */
/* XXX last struct has 7 bytes of padding */
/* --- cacheline 22 boundary (1408 bytes) was 40 bytes ago --- */
atomic_t * refcnt; /* 1448 8 */
bool orphan; /* 1456 1 */
bool enable; /* 1457 1 */
bool activated; /* 1458 1 */
/* XXX 5 bytes hole, try to pack */
struct dev_ext_attribute * ea; /* 1464 8 */
/* size: 1472, cachelines: 23, members: 12 */
/* sum members: 1463, holes: 2, sum holes: 9 */
/* paddings: 1, sum paddings: 7 */
};
root@d15263e5734a:/git/perf#
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Link: http://lkml.kernel.org/r/20190131184714.20388-3-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-01-31 11:47:09 -07:00
|
|
|
#include "coresight-etm-perf.h"
|
2014-11-03 11:07:35 -07:00
|
|
|
#include "coresight-priv.h"
|
|
|
|
|
|
|
|
static DEFINE_MUTEX(coresight_mutex);
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
/**
|
|
|
|
* struct coresight_node - elements of a path, from source to sink
|
|
|
|
* @csdev: Address of an element.
|
|
|
|
* @link: hook to the list.
|
|
|
|
*/
|
|
|
|
struct coresight_node {
|
|
|
|
struct coresight_device *csdev;
|
|
|
|
struct list_head link;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When operating Coresight drivers from the sysFS interface, only a single
|
|
|
|
* path can exist from a tracer (associated to a CPU) to a sink.
|
|
|
|
*/
|
2016-05-03 11:33:38 -06:00
|
|
|
static DEFINE_PER_CPU(struct list_head *, tracer_path);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* As of this writing only a single STM can be found in CS topologies. Since
|
|
|
|
* there is no way to know if we'll ever see more and what kind of
|
|
|
|
* configuration they will enact, for the time being only define a single path
|
|
|
|
* for STM.
|
|
|
|
*/
|
|
|
|
static struct list_head *stm_path;
|
2016-02-17 17:51:45 -07:00
|
|
|
|
2017-08-02 10:21:57 -06:00
|
|
|
/*
|
|
|
|
* When losing synchronisation a new barrier packet needs to be inserted at the
|
|
|
|
* beginning of the data collected in a buffer. That way the decoder knows that
|
|
|
|
* it needs to look for another sync sequence.
|
|
|
|
*/
|
2018-07-11 13:40:18 -06:00
|
|
|
const u32 barrier_pkt[4] = {0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff};
|
2017-08-02 10:21:57 -06:00
|
|
|
|
2014-11-03 11:07:35 -07:00
|
|
|
static int coresight_id_match(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
int trace_id, i_trace_id;
|
|
|
|
struct coresight_device *csdev, *i_csdev;
|
|
|
|
|
|
|
|
csdev = data;
|
|
|
|
i_csdev = to_coresight_device(dev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* No need to care about oneself and components that are not
|
|
|
|
* sources or not enabled
|
|
|
|
*/
|
|
|
|
if (i_csdev == csdev || !i_csdev->enable ||
|
|
|
|
i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Get the source ID for both compoment */
|
|
|
|
trace_id = source_ops(csdev)->trace_id(csdev);
|
|
|
|
i_trace_id = source_ops(i_csdev)->trace_id(i_csdev);
|
|
|
|
|
|
|
|
/* All you need is one */
|
|
|
|
if (trace_id == i_trace_id)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int coresight_source_is_unique(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
int trace_id = source_ops(csdev)->trace_id(csdev);
|
|
|
|
|
|
|
|
/* this shouldn't happen */
|
|
|
|
if (trace_id < 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return !bus_for_each_dev(&coresight_bustype, NULL,
|
|
|
|
csdev, coresight_id_match);
|
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
static int coresight_find_link_inport(struct coresight_device *csdev,
|
|
|
|
struct coresight_device *parent)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct coresight_connection *conn;
|
|
|
|
|
|
|
|
for (i = 0; i < parent->nr_outport; i++) {
|
|
|
|
conn = &parent->conns[i];
|
|
|
|
if (conn->child_dev == csdev)
|
|
|
|
return conn->child_port;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_err(&csdev->dev, "couldn't find inport, parent: %s, child: %s\n",
|
|
|
|
dev_name(&parent->dev), dev_name(&csdev->dev));
|
|
|
|
|
2018-07-11 13:40:28 -06:00
|
|
|
return -ENODEV;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
static int coresight_find_link_outport(struct coresight_device *csdev,
|
|
|
|
struct coresight_device *child)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct coresight_connection *conn;
|
|
|
|
|
|
|
|
for (i = 0; i < csdev->nr_outport; i++) {
|
|
|
|
conn = &csdev->conns[i];
|
|
|
|
if (conn->child_dev == child)
|
|
|
|
return conn->outport;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_err(&csdev->dev, "couldn't find outport, parent: %s, child: %s\n",
|
|
|
|
dev_name(&csdev->dev), dev_name(&child->dev));
|
|
|
|
|
2018-07-11 13:40:28 -06:00
|
|
|
return -ENODEV;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
2018-09-20 13:18:11 -06:00
|
|
|
static inline u32 coresight_read_claim_tags(void __iomem *base)
|
|
|
|
{
|
|
|
|
return readl_relaxed(base + CORESIGHT_CLAIMCLR);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool coresight_is_claimed_self_hosted(void __iomem *base)
|
|
|
|
{
|
|
|
|
return coresight_read_claim_tags(base) == CORESIGHT_CLAIM_SELF_HOSTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool coresight_is_claimed_any(void __iomem *base)
|
|
|
|
{
|
|
|
|
return coresight_read_claim_tags(base) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void coresight_set_claim_tags(void __iomem *base)
|
|
|
|
{
|
|
|
|
writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMSET);
|
|
|
|
isb();
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void coresight_clear_claim_tags(void __iomem *base)
|
|
|
|
{
|
|
|
|
writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMCLR);
|
|
|
|
isb();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* coresight_claim_device_unlocked : Claim the device for self-hosted usage
|
|
|
|
* to prevent an external tool from touching this device. As per PSCI
|
|
|
|
* standards, section "Preserving the execution context" => "Debug and Trace
|
|
|
|
* save and Restore", DBGCLAIM[1] is reserved for Self-hosted debug/trace and
|
|
|
|
* DBGCLAIM[0] is reserved for external tools.
|
|
|
|
*
|
|
|
|
* Called with CS_UNLOCKed for the component.
|
|
|
|
* Returns : 0 on success
|
|
|
|
*/
|
|
|
|
int coresight_claim_device_unlocked(void __iomem *base)
|
|
|
|
{
|
|
|
|
if (coresight_is_claimed_any(base))
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
coresight_set_claim_tags(base);
|
|
|
|
if (coresight_is_claimed_self_hosted(base))
|
|
|
|
return 0;
|
|
|
|
/* There was a race setting the tags, clean up and fail */
|
|
|
|
coresight_clear_claim_tags(base);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
int coresight_claim_device(void __iomem *base)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
CS_UNLOCK(base);
|
|
|
|
rc = coresight_claim_device_unlocked(base);
|
|
|
|
CS_LOCK(base);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* coresight_disclaim_device_unlocked : Clear the claim tags for the device.
|
|
|
|
* Called with CS_UNLOCKed for the component.
|
|
|
|
*/
|
|
|
|
void coresight_disclaim_device_unlocked(void __iomem *base)
|
|
|
|
{
|
|
|
|
|
|
|
|
if (coresight_is_claimed_self_hosted(base))
|
|
|
|
coresight_clear_claim_tags(base);
|
|
|
|
else
|
|
|
|
/*
|
|
|
|
* The external agent may have not honoured our claim
|
|
|
|
* and has manipulated it. Or something else has seriously
|
|
|
|
* gone wrong in our driver.
|
|
|
|
*/
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void coresight_disclaim_device(void __iomem *base)
|
|
|
|
{
|
|
|
|
CS_UNLOCK(base);
|
|
|
|
coresight_disclaim_device_unlocked(base);
|
|
|
|
CS_LOCK(base);
|
|
|
|
}
|
|
|
|
|
2018-09-20 13:17:56 -06:00
|
|
|
static int coresight_enable_sink(struct coresight_device *csdev,
|
|
|
|
u32 mode, void *data)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2018-09-20 13:17:45 -06:00
|
|
|
/*
|
|
|
|
* We need to make sure the "new" session is compatible with the
|
|
|
|
* existing "mode" of operation.
|
|
|
|
*/
|
|
|
|
if (sink_ops(csdev)->enable) {
|
2018-09-20 13:17:56 -06:00
|
|
|
ret = sink_ops(csdev)->enable(csdev, mode, data);
|
2018-09-20 13:17:45 -06:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-11-03 11:07:35 -07:00
|
|
|
csdev->enable = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
atomic_inc(csdev->refcnt);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void coresight_disable_sink(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
if (atomic_dec_return(csdev->refcnt) == 0) {
|
|
|
|
if (sink_ops(csdev)->disable) {
|
|
|
|
sink_ops(csdev)->disable(csdev);
|
|
|
|
csdev->enable = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
static int coresight_enable_link(struct coresight_device *csdev,
|
|
|
|
struct coresight_device *parent,
|
|
|
|
struct coresight_device *child)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int link_subtype;
|
|
|
|
int refport, inport, outport;
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
if (!parent || !child)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
inport = coresight_find_link_inport(csdev, parent);
|
|
|
|
outport = coresight_find_link_outport(csdev, child);
|
2014-11-03 11:07:35 -07:00
|
|
|
link_subtype = csdev->subtype.link_subtype;
|
|
|
|
|
|
|
|
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG)
|
|
|
|
refport = inport;
|
|
|
|
else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT)
|
|
|
|
refport = outport;
|
|
|
|
else
|
|
|
|
refport = 0;
|
|
|
|
|
2018-07-11 13:40:28 -06:00
|
|
|
if (refport < 0)
|
|
|
|
return refport;
|
|
|
|
|
2014-11-03 11:07:35 -07:00
|
|
|
if (atomic_inc_return(&csdev->refcnt[refport]) == 1) {
|
|
|
|
if (link_ops(csdev)->enable) {
|
|
|
|
ret = link_ops(csdev)->enable(csdev, inport, outport);
|
coresight: Handle failures in enabling a trace path
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-20 13:18:03 -06:00
|
|
|
if (ret) {
|
|
|
|
atomic_dec(&csdev->refcnt[refport]);
|
2014-11-03 11:07:35 -07:00
|
|
|
return ret;
|
coresight: Handle failures in enabling a trace path
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-20 13:18:03 -06:00
|
|
|
}
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
csdev->enable = true;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
static void coresight_disable_link(struct coresight_device *csdev,
|
|
|
|
struct coresight_device *parent,
|
|
|
|
struct coresight_device *child)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
|
|
|
int i, nr_conns;
|
|
|
|
int link_subtype;
|
|
|
|
int refport, inport, outport;
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
if (!parent || !child)
|
|
|
|
return;
|
|
|
|
|
|
|
|
inport = coresight_find_link_inport(csdev, parent);
|
|
|
|
outport = coresight_find_link_outport(csdev, child);
|
2014-11-03 11:07:35 -07:00
|
|
|
link_subtype = csdev->subtype.link_subtype;
|
|
|
|
|
|
|
|
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG) {
|
|
|
|
refport = inport;
|
|
|
|
nr_conns = csdev->nr_inport;
|
|
|
|
} else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT) {
|
|
|
|
refport = outport;
|
|
|
|
nr_conns = csdev->nr_outport;
|
|
|
|
} else {
|
|
|
|
refport = 0;
|
|
|
|
nr_conns = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (atomic_dec_return(&csdev->refcnt[refport]) == 0) {
|
|
|
|
if (link_ops(csdev)->disable)
|
|
|
|
link_ops(csdev)->disable(csdev, inport, outport);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < nr_conns; i++)
|
|
|
|
if (atomic_read(&csdev->refcnt[i]) != 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
csdev->enable = false;
|
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:52 -07:00
|
|
|
static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!coresight_source_is_unique(csdev)) {
|
|
|
|
dev_warn(&csdev->dev, "traceID %d not unique\n",
|
|
|
|
source_ops(csdev)->trace_id(csdev));
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!csdev->enable) {
|
|
|
|
if (source_ops(csdev)->enable) {
|
2016-02-17 17:51:57 -07:00
|
|
|
ret = source_ops(csdev)->enable(csdev, NULL, mode);
|
2014-11-03 11:07:35 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
csdev->enable = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
atomic_inc(csdev->refcnt);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-06-05 14:15:02 -06:00
|
|
|
/**
|
|
|
|
* coresight_disable_source - Drop the reference count by 1 and disable
|
|
|
|
* the device if there are no users left.
|
|
|
|
*
|
|
|
|
* @csdev - The coresight device to disable
|
|
|
|
*
|
|
|
|
* Returns true if the device has been disabled.
|
|
|
|
*/
|
|
|
|
static bool coresight_disable_source(struct coresight_device *csdev)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
|
|
|
if (atomic_dec_return(csdev->refcnt) == 0) {
|
2017-06-05 14:15:02 -06:00
|
|
|
if (source_ops(csdev)->disable)
|
2016-08-25 15:19:10 -06:00
|
|
|
source_ops(csdev)->disable(csdev, NULL);
|
2017-06-05 14:15:02 -06:00
|
|
|
csdev->enable = false;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
2017-06-05 14:15:02 -06:00
|
|
|
return !csdev->enable;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
coresight: Handle failures in enabling a trace path
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-20 13:18:03 -06:00
|
|
|
/*
|
|
|
|
* coresight_disable_path_from : Disable components in the given path beyond
|
|
|
|
* @nd in the list. If @nd is NULL, all the components, except the SOURCE are
|
|
|
|
* disabled.
|
|
|
|
*/
|
|
|
|
static void coresight_disable_path_from(struct list_head *path,
|
|
|
|
struct coresight_node *nd)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
2016-05-03 11:34:00 -06:00
|
|
|
u32 type;
|
2016-02-17 17:51:45 -07:00
|
|
|
struct coresight_device *csdev, *parent, *child;
|
|
|
|
|
coresight: Handle failures in enabling a trace path
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-20 13:18:03 -06:00
|
|
|
if (!nd)
|
|
|
|
nd = list_first_entry(path, struct coresight_node, link);
|
|
|
|
|
|
|
|
list_for_each_entry_continue(nd, path, link) {
|
2016-02-17 17:51:45 -07:00
|
|
|
csdev = nd->csdev;
|
2016-05-03 11:34:00 -06:00
|
|
|
type = csdev->type;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ETF devices are tricky... They can be a link or a sink,
|
|
|
|
* depending on how they are configured. If an ETF has been
|
|
|
|
* "activated" it will be configured as a sink, otherwise
|
|
|
|
* go ahead with the link configuration.
|
|
|
|
*/
|
|
|
|
if (type == CORESIGHT_DEV_TYPE_LINKSINK)
|
|
|
|
type = (csdev == coresight_get_sink(path)) ?
|
|
|
|
CORESIGHT_DEV_TYPE_SINK :
|
|
|
|
CORESIGHT_DEV_TYPE_LINK;
|
|
|
|
|
|
|
|
switch (type) {
|
2016-02-17 17:51:45 -07:00
|
|
|
case CORESIGHT_DEV_TYPE_SINK:
|
|
|
|
coresight_disable_sink(csdev);
|
|
|
|
break;
|
|
|
|
case CORESIGHT_DEV_TYPE_SOURCE:
|
coresight: Handle failures in enabling a trace path
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-20 13:18:03 -06:00
|
|
|
/*
|
|
|
|
* We skip the first node in the path assuming that it
|
|
|
|
* is the source. So we don't expect a source device in
|
|
|
|
* the middle of a path.
|
|
|
|
*/
|
|
|
|
WARN_ON(1);
|
2016-02-17 17:51:45 -07:00
|
|
|
break;
|
|
|
|
case CORESIGHT_DEV_TYPE_LINK:
|
|
|
|
parent = list_prev_entry(nd, link)->csdev;
|
|
|
|
child = list_next_entry(nd, link)->csdev;
|
|
|
|
coresight_disable_link(csdev, parent, child);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
}
|
2016-02-17 17:51:45 -07:00
|
|
|
}
|
2014-11-03 11:07:35 -07:00
|
|
|
|
coresight: Handle failures in enabling a trace path
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-20 13:18:03 -06:00
|
|
|
void coresight_disable_path(struct list_head *path)
|
|
|
|
{
|
|
|
|
coresight_disable_path_from(path, NULL);
|
|
|
|
}
|
|
|
|
|
2018-09-20 13:17:56 -06:00
|
|
|
int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data)
|
2016-02-17 17:51:45 -07:00
|
|
|
{
|
|
|
|
|
|
|
|
int ret = 0;
|
2016-05-03 11:34:00 -06:00
|
|
|
u32 type;
|
2016-02-17 17:51:45 -07:00
|
|
|
struct coresight_node *nd;
|
|
|
|
struct coresight_device *csdev, *parent, *child;
|
|
|
|
|
|
|
|
list_for_each_entry_reverse(nd, path, link) {
|
|
|
|
csdev = nd->csdev;
|
2016-05-03 11:34:00 -06:00
|
|
|
type = csdev->type;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ETF devices are tricky... They can be a link or a sink,
|
|
|
|
* depending on how they are configured. If an ETF has been
|
|
|
|
* "activated" it will be configured as a sink, otherwise
|
|
|
|
* go ahead with the link configuration.
|
|
|
|
*/
|
|
|
|
if (type == CORESIGHT_DEV_TYPE_LINKSINK)
|
|
|
|
type = (csdev == coresight_get_sink(path)) ?
|
|
|
|
CORESIGHT_DEV_TYPE_SINK :
|
|
|
|
CORESIGHT_DEV_TYPE_LINK;
|
|
|
|
|
|
|
|
switch (type) {
|
2016-02-17 17:51:45 -07:00
|
|
|
case CORESIGHT_DEV_TYPE_SINK:
|
2018-09-20 13:17:56 -06:00
|
|
|
ret = coresight_enable_sink(csdev, mode, sink_data);
|
2018-09-20 13:17:45 -06:00
|
|
|
/*
|
|
|
|
* Sink is the first component turned on. If we
|
|
|
|
* failed to enable the sink, there are no components
|
|
|
|
* that need disabling. Disabling the path here
|
|
|
|
* would mean we could disrupt an existing session.
|
|
|
|
*/
|
2016-02-17 17:51:45 -07:00
|
|
|
if (ret)
|
2018-09-20 13:17:45 -06:00
|
|
|
goto out;
|
2016-02-17 17:51:45 -07:00
|
|
|
break;
|
|
|
|
case CORESIGHT_DEV_TYPE_SOURCE:
|
|
|
|
/* sources are enabled from either sysFS or Perf */
|
|
|
|
break;
|
|
|
|
case CORESIGHT_DEV_TYPE_LINK:
|
|
|
|
parent = list_prev_entry(nd, link)->csdev;
|
|
|
|
child = list_next_entry(nd, link)->csdev;
|
|
|
|
ret = coresight_enable_link(csdev, parent, child);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
goto err;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
out:
|
2014-11-03 11:07:35 -07:00
|
|
|
return ret;
|
2016-02-17 17:51:45 -07:00
|
|
|
err:
|
coresight: Handle failures in enabling a trace path
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the component, we simply disable
all the components in the given path irrespective of whether
we enabled some of the components in the enable iteration.
This could interfere with another trace session if one of the
link devices is turned off (e.g, TMC-ETF). So, we need to
make sure that we only disable those components which were
actually enabled from the iteration.
This patch achieves the same by refactoring the coresight_disable_path
to accept a "node" to start from in the forward order, which can
then be used from the error path of coresight_enable_path().
With this change, we don't issue a disable call back for a component
which didn't get enabled. This change of behavior triggers
a bug in coresight_enable_link(), where we leave the refcount
on the device and will prevent the device from being enabled
forever. So, we also drop the refcount in the coresight_enable_link()
if the operation failed.
Also, with the refactoring, we always start after the first node (which
is the "SOURCE" device) for disabling the entire path. This implies,
we must not find a "SOURCE" in the middle of the path. Hence, added
a WARN_ON() to make sure the paths we get are sane, rather than
simply ignoring them.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-20 13:18:03 -06:00
|
|
|
coresight_disable_path_from(path, nd);
|
2016-02-17 17:51:45 -07:00
|
|
|
goto out;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:46 -07:00
|
|
|
struct coresight_device *coresight_get_sink(struct list_head *path)
|
|
|
|
{
|
|
|
|
struct coresight_device *csdev;
|
|
|
|
|
|
|
|
if (!path)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
csdev = list_last_entry(path, struct coresight_node, link)->csdev;
|
|
|
|
if (csdev->type != CORESIGHT_DEV_TYPE_SINK &&
|
|
|
|
csdev->type != CORESIGHT_DEV_TYPE_LINKSINK)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return csdev;
|
|
|
|
}
|
|
|
|
|
2016-11-29 09:47:14 -07:00
|
|
|
static int coresight_enabled_sink(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
bool *reset = data;
|
|
|
|
struct coresight_device *csdev = to_coresight_device(dev);
|
|
|
|
|
|
|
|
if ((csdev->type == CORESIGHT_DEV_TYPE_SINK ||
|
|
|
|
csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) &&
|
|
|
|
csdev->activated) {
|
|
|
|
/*
|
|
|
|
* Now that we have a handle on the sink for this session,
|
|
|
|
* disable the sysFS "enable_sink" flag so that possible
|
|
|
|
* concurrent perf session that wish to use another sink don't
|
|
|
|
* trip on it. Doing so has no ramification for the current
|
|
|
|
* session.
|
|
|
|
*/
|
|
|
|
if (*reset)
|
|
|
|
csdev->activated = false;
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* coresight_get_enabled_sink - returns the first enabled sink found on the bus
|
|
|
|
* @deactivate: Whether the 'enable_sink' flag should be reset
|
|
|
|
*
|
|
|
|
* When operated from perf the deactivate parameter should be set to 'true'.
|
|
|
|
* That way the "enabled_sink" flag of the sink that was selected can be reset,
|
|
|
|
* allowing for other concurrent perf sessions to choose a different sink.
|
|
|
|
*
|
|
|
|
* When operated from sysFS users have full control and as such the deactivate
|
|
|
|
* parameter should be set to 'false', hence mandating users to explicitly
|
|
|
|
* clear the flag.
|
|
|
|
*/
|
|
|
|
struct coresight_device *coresight_get_enabled_sink(bool deactivate)
|
|
|
|
{
|
|
|
|
struct device *dev = NULL;
|
|
|
|
|
|
|
|
dev = bus_find_device(&coresight_bustype, NULL, &deactivate,
|
|
|
|
coresight_enabled_sink);
|
|
|
|
|
|
|
|
return dev ? to_coresight_device(dev) : NULL;
|
|
|
|
}
|
|
|
|
|
2019-01-31 11:47:10 -07:00
|
|
|
static int coresight_sink_by_id(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
struct coresight_device *csdev = to_coresight_device(dev);
|
|
|
|
unsigned long hash;
|
|
|
|
|
|
|
|
if (csdev->type == CORESIGHT_DEV_TYPE_SINK ||
|
|
|
|
csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) {
|
|
|
|
|
|
|
|
if (!csdev->ea)
|
|
|
|
return 0;
|
|
|
|
/*
|
|
|
|
* See function etm_perf_add_symlink_sink() to know where
|
|
|
|
* this comes from.
|
|
|
|
*/
|
|
|
|
hash = (unsigned long)csdev->ea->var;
|
|
|
|
|
|
|
|
if ((u32)hash == *(u32 *)data)
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* coresight_get_sink_by_id - returns the sink that matches the id
|
|
|
|
* @id: Id of the sink to match
|
|
|
|
*
|
|
|
|
* The name of a sink is unique, whether it is found on the AMBA bus or
|
|
|
|
* otherwise. As such the hash of that name can easily be used to identify
|
|
|
|
* a sink.
|
|
|
|
*/
|
|
|
|
struct coresight_device *coresight_get_sink_by_id(u32 id)
|
|
|
|
{
|
|
|
|
struct device *dev = NULL;
|
|
|
|
|
|
|
|
dev = bus_find_device(&coresight_bustype, NULL, &id,
|
|
|
|
coresight_sink_by_id);
|
|
|
|
|
|
|
|
return dev ? to_coresight_device(dev) : NULL;
|
|
|
|
}
|
|
|
|
|
coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-11 13:40:30 -06:00
|
|
|
/*
|
|
|
|
* coresight_grab_device - Power up this device and any of the helper
|
|
|
|
* devices connected to it for trace operation. Since the helper devices
|
|
|
|
* don't appear on the trace path, they should be handled along with the
|
|
|
|
* the master device.
|
|
|
|
*/
|
|
|
|
static void coresight_grab_device(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < csdev->nr_outport; i++) {
|
|
|
|
struct coresight_device *child = csdev->conns[i].child_dev;
|
|
|
|
|
|
|
|
if (child && child->type == CORESIGHT_DEV_TYPE_HELPER)
|
|
|
|
pm_runtime_get_sync(child->dev.parent);
|
|
|
|
}
|
|
|
|
pm_runtime_get_sync(csdev->dev.parent);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* coresight_drop_device - Release this device and any of the helper
|
|
|
|
* devices connected to it.
|
|
|
|
*/
|
|
|
|
static void coresight_drop_device(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
pm_runtime_put(csdev->dev.parent);
|
|
|
|
for (i = 0; i < csdev->nr_outport; i++) {
|
|
|
|
struct coresight_device *child = csdev->conns[i].child_dev;
|
|
|
|
|
|
|
|
if (child && child->type == CORESIGHT_DEV_TYPE_HELPER)
|
|
|
|
pm_runtime_put(child->dev.parent);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
/**
|
|
|
|
* _coresight_build_path - recursively build a path from a @csdev to a sink.
|
|
|
|
* @csdev: The device to start from.
|
|
|
|
* @path: The list to add devices to.
|
|
|
|
*
|
|
|
|
* The tree of Coresight device is traversed until an activated sink is
|
|
|
|
* found. From there the sink is added to the list along with all the
|
|
|
|
* devices that led to that point - the end result is a list from source
|
|
|
|
* to sink. In that list the source is the first device and the sink the
|
|
|
|
* last one.
|
|
|
|
*/
|
|
|
|
static int _coresight_build_path(struct coresight_device *csdev,
|
2016-11-29 09:47:14 -07:00
|
|
|
struct coresight_device *sink,
|
2016-02-17 17:51:45 -07:00
|
|
|
struct list_head *path)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
2016-02-17 17:51:45 -07:00
|
|
|
int i;
|
|
|
|
bool found = false;
|
|
|
|
struct coresight_node *node;
|
|
|
|
|
|
|
|
/* An activated sink has been found. Enqueue the element */
|
2016-11-29 09:47:14 -07:00
|
|
|
if (csdev == sink)
|
2016-02-17 17:51:45 -07:00
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* Not a sink - recursively explore each port found on this element */
|
|
|
|
for (i = 0; i < csdev->nr_outport; i++) {
|
2016-06-14 11:17:12 -06:00
|
|
|
struct coresight_device *child_dev = csdev->conns[i].child_dev;
|
|
|
|
|
2016-11-29 09:47:14 -07:00
|
|
|
if (child_dev &&
|
|
|
|
_coresight_build_path(child_dev, sink, path) == 0) {
|
2016-02-17 17:51:45 -07:00
|
|
|
found = true;
|
|
|
|
break;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
if (!found)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
out:
|
|
|
|
/*
|
|
|
|
* A path from this element to a sink has been found. The elements
|
|
|
|
* leading to the sink are already enqueued, all that is left to do
|
2016-02-17 17:51:47 -07:00
|
|
|
* is tell the PM runtime core we need this element and add a node
|
|
|
|
* for it.
|
2016-02-17 17:51:45 -07:00
|
|
|
*/
|
|
|
|
node = kzalloc(sizeof(struct coresight_node), GFP_KERNEL);
|
|
|
|
if (!node)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-11 13:40:30 -06:00
|
|
|
coresight_grab_device(csdev);
|
2016-02-17 17:51:45 -07:00
|
|
|
node->csdev = csdev;
|
|
|
|
list_add(&node->link, path);
|
|
|
|
|
2014-11-03 11:07:35 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-29 09:47:14 -07:00
|
|
|
struct list_head *coresight_build_path(struct coresight_device *source,
|
|
|
|
struct coresight_device *sink)
|
2014-11-03 11:07:35 -07:00
|
|
|
{
|
2016-02-17 17:51:45 -07:00
|
|
|
struct list_head *path;
|
2016-05-06 08:35:50 -06:00
|
|
|
int rc;
|
2014-11-03 11:07:35 -07:00
|
|
|
|
2016-11-29 09:47:14 -07:00
|
|
|
if (!sink)
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
path = kzalloc(sizeof(struct list_head), GFP_KERNEL);
|
|
|
|
if (!path)
|
2016-09-08 16:50:38 -06:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2014-11-03 11:07:35 -07:00
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
INIT_LIST_HEAD(path);
|
|
|
|
|
2016-11-29 09:47:14 -07:00
|
|
|
rc = _coresight_build_path(source, sink, path);
|
2016-05-06 08:35:50 -06:00
|
|
|
if (rc) {
|
2016-02-17 17:51:45 -07:00
|
|
|
kfree(path);
|
2016-05-06 08:35:50 -06:00
|
|
|
return ERR_PTR(rc);
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
return path;
|
|
|
|
}
|
2014-11-03 11:07:35 -07:00
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
/**
|
|
|
|
* coresight_release_path - release a previously built path.
|
|
|
|
* @path: the path to release.
|
|
|
|
*
|
|
|
|
* Go through all the elements of a path and 1) removed it from the list and
|
|
|
|
* 2) free the memory allocated for each node.
|
|
|
|
*/
|
|
|
|
void coresight_release_path(struct list_head *path)
|
|
|
|
{
|
2016-02-17 17:51:47 -07:00
|
|
|
struct coresight_device *csdev;
|
2016-02-17 17:51:45 -07:00
|
|
|
struct coresight_node *nd, *next;
|
2014-11-03 11:07:35 -07:00
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
list_for_each_entry_safe(nd, next, path, link) {
|
2016-02-17 17:51:47 -07:00
|
|
|
csdev = nd->csdev;
|
|
|
|
|
coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-11 13:40:30 -06:00
|
|
|
coresight_drop_device(csdev);
|
2016-02-17 17:51:45 -07:00
|
|
|
list_del(&nd->link);
|
|
|
|
kfree(nd);
|
|
|
|
}
|
|
|
|
|
|
|
|
kfree(path);
|
|
|
|
path = NULL;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
2016-05-03 11:33:38 -06:00
|
|
|
/** coresight_validate_source - make sure a source has the right credentials
|
|
|
|
* @csdev: the device structure for a source.
|
|
|
|
* @function: the function this was called from.
|
|
|
|
*
|
|
|
|
* Assumes the coresight_mutex is held.
|
|
|
|
*/
|
|
|
|
static int coresight_validate_source(struct coresight_device *csdev,
|
|
|
|
const char *function)
|
|
|
|
{
|
|
|
|
u32 type, subtype;
|
|
|
|
|
|
|
|
type = csdev->type;
|
|
|
|
subtype = csdev->subtype.source_subtype;
|
|
|
|
|
|
|
|
if (type != CORESIGHT_DEV_TYPE_SOURCE) {
|
|
|
|
dev_err(&csdev->dev, "wrong device type in %s\n", function);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &&
|
|
|
|
subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) {
|
|
|
|
dev_err(&csdev->dev, "wrong device subtype in %s\n", function);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-03 11:07:35 -07:00
|
|
|
int coresight_enable(struct coresight_device *csdev)
|
|
|
|
{
|
2016-05-03 11:33:38 -06:00
|
|
|
int cpu, ret = 0;
|
2016-11-29 09:47:14 -07:00
|
|
|
struct coresight_device *sink;
|
2016-02-17 17:51:45 -07:00
|
|
|
struct list_head *path;
|
2017-06-05 14:15:03 -06:00
|
|
|
enum coresight_dev_subtype_source subtype;
|
|
|
|
|
|
|
|
subtype = csdev->subtype.source_subtype;
|
2014-11-03 11:07:35 -07:00
|
|
|
|
|
|
|
mutex_lock(&coresight_mutex);
|
2016-05-03 11:33:38 -06:00
|
|
|
|
|
|
|
ret = coresight_validate_source(csdev, __func__);
|
|
|
|
if (ret)
|
2014-11-03 11:07:35 -07:00
|
|
|
goto out;
|
2016-05-03 11:33:38 -06:00
|
|
|
|
2017-06-05 14:15:03 -06:00
|
|
|
if (csdev->enable) {
|
|
|
|
/*
|
|
|
|
* There could be multiple applications driving the software
|
|
|
|
* source. So keep the refcount for each such user when the
|
|
|
|
* source is already enabled.
|
|
|
|
*/
|
|
|
|
if (subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE)
|
|
|
|
atomic_inc(csdev->refcnt);
|
2014-11-03 11:07:35 -07:00
|
|
|
goto out;
|
2017-06-05 14:15:03 -06:00
|
|
|
}
|
2014-11-03 11:07:35 -07:00
|
|
|
|
2016-11-29 09:47:14 -07:00
|
|
|
/*
|
|
|
|
* Search for a valid sink for this session but don't reset the
|
|
|
|
* "enable_sink" flag in sysFS. Users get to do that explicitly.
|
|
|
|
*/
|
|
|
|
sink = coresight_get_enabled_sink(false);
|
|
|
|
if (!sink) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
path = coresight_build_path(csdev, sink);
|
2016-05-06 08:35:50 -06:00
|
|
|
if (IS_ERR(path)) {
|
2016-02-17 17:51:45 -07:00
|
|
|
pr_err("building path(s) failed\n");
|
2016-05-06 08:35:50 -06:00
|
|
|
ret = PTR_ERR(path);
|
2014-11-03 11:07:35 -07:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2018-09-20 13:17:56 -06:00
|
|
|
ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL);
|
2016-02-17 17:51:45 -07:00
|
|
|
if (ret)
|
|
|
|
goto err_path;
|
|
|
|
|
2016-02-17 17:51:52 -07:00
|
|
|
ret = coresight_enable_source(csdev, CS_MODE_SYSFS);
|
2016-02-17 17:51:45 -07:00
|
|
|
if (ret)
|
|
|
|
goto err_source;
|
|
|
|
|
2017-06-05 14:15:03 -06:00
|
|
|
switch (subtype) {
|
2016-05-03 11:33:38 -06:00
|
|
|
case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
|
|
|
|
/*
|
|
|
|
* When working from sysFS it is important to keep track
|
|
|
|
* of the paths that were created so that they can be
|
|
|
|
* undone in 'coresight_disable()'. Since there can only
|
|
|
|
* be a single session per tracer (when working from sysFS)
|
|
|
|
* a per-cpu variable will do just fine.
|
|
|
|
*/
|
|
|
|
cpu = source_ops(csdev)->cpu_id(csdev);
|
|
|
|
per_cpu(tracer_path, cpu) = path;
|
|
|
|
break;
|
|
|
|
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
|
|
|
|
stm_path = path;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* We can't be here */
|
|
|
|
break;
|
|
|
|
}
|
2016-02-17 17:51:45 -07:00
|
|
|
|
2014-11-03 11:07:35 -07:00
|
|
|
out:
|
|
|
|
mutex_unlock(&coresight_mutex);
|
|
|
|
return ret;
|
2016-02-17 17:51:45 -07:00
|
|
|
|
|
|
|
err_source:
|
|
|
|
coresight_disable_path(path);
|
|
|
|
|
|
|
|
err_path:
|
|
|
|
coresight_release_path(path);
|
|
|
|
goto out;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(coresight_enable);
|
|
|
|
|
|
|
|
void coresight_disable(struct coresight_device *csdev)
|
|
|
|
{
|
2016-05-03 11:33:38 -06:00
|
|
|
int cpu, ret;
|
|
|
|
struct list_head *path = NULL;
|
2014-11-03 11:07:35 -07:00
|
|
|
|
|
|
|
mutex_lock(&coresight_mutex);
|
2016-05-03 11:33:38 -06:00
|
|
|
|
|
|
|
ret = coresight_validate_source(csdev, __func__);
|
|
|
|
if (ret)
|
2014-11-03 11:07:35 -07:00
|
|
|
goto out;
|
2016-05-03 11:33:38 -06:00
|
|
|
|
2017-06-05 14:15:02 -06:00
|
|
|
if (!csdev->enable || !coresight_disable_source(csdev))
|
2014-11-03 11:07:35 -07:00
|
|
|
goto out;
|
|
|
|
|
2016-05-03 11:33:38 -06:00
|
|
|
switch (csdev->subtype.source_subtype) {
|
|
|
|
case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
|
|
|
|
cpu = source_ops(csdev)->cpu_id(csdev);
|
|
|
|
path = per_cpu(tracer_path, cpu);
|
|
|
|
per_cpu(tracer_path, cpu) = NULL;
|
|
|
|
break;
|
|
|
|
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
|
|
|
|
path = stm_path;
|
|
|
|
stm_path = NULL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* We can't be here */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-02-17 17:51:45 -07:00
|
|
|
coresight_disable_path(path);
|
|
|
|
coresight_release_path(path);
|
2014-11-03 11:07:35 -07:00
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&coresight_mutex);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(coresight_disable);
|
|
|
|
|
|
|
|
static ssize_t enable_sink_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct coresight_device *csdev = to_coresight_device(dev);
|
|
|
|
|
2016-05-03 11:33:35 -06:00
|
|
|
return scnprintf(buf, PAGE_SIZE, "%u\n", csdev->activated);
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t enable_sink_store(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
unsigned long val;
|
|
|
|
struct coresight_device *csdev = to_coresight_device(dev);
|
|
|
|
|
|
|
|
ret = kstrtoul(buf, 10, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (val)
|
|
|
|
csdev->activated = true;
|
|
|
|
else
|
|
|
|
csdev->activated = false;
|
|
|
|
|
|
|
|
return size;
|
|
|
|
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(enable_sink);
|
|
|
|
|
|
|
|
static ssize_t enable_source_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct coresight_device *csdev = to_coresight_device(dev);
|
|
|
|
|
2016-05-03 11:33:35 -06:00
|
|
|
return scnprintf(buf, PAGE_SIZE, "%u\n", csdev->enable);
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t enable_source_store(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
unsigned long val;
|
|
|
|
struct coresight_device *csdev = to_coresight_device(dev);
|
|
|
|
|
|
|
|
ret = kstrtoul(buf, 10, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (val) {
|
|
|
|
ret = coresight_enable(csdev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
} else {
|
|
|
|
coresight_disable(csdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(enable_source);
|
|
|
|
|
|
|
|
static struct attribute *coresight_sink_attrs[] = {
|
|
|
|
&dev_attr_enable_sink.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
ATTRIBUTE_GROUPS(coresight_sink);
|
|
|
|
|
|
|
|
static struct attribute *coresight_source_attrs[] = {
|
|
|
|
&dev_attr_enable_source.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
ATTRIBUTE_GROUPS(coresight_source);
|
|
|
|
|
|
|
|
static struct device_type coresight_dev_type[] = {
|
|
|
|
{
|
|
|
|
.name = "none",
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "sink",
|
|
|
|
.groups = coresight_sink_groups,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "link",
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "linksink",
|
|
|
|
.groups = coresight_sink_groups,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "source",
|
|
|
|
.groups = coresight_source_groups,
|
|
|
|
},
|
coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-11 13:40:30 -06:00
|
|
|
{
|
|
|
|
.name = "helper",
|
|
|
|
},
|
2014-11-03 11:07:35 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static void coresight_device_release(struct device *dev)
|
|
|
|
{
|
|
|
|
struct coresight_device *csdev = to_coresight_device(dev);
|
|
|
|
|
2016-02-02 14:13:57 -07:00
|
|
|
kfree(csdev->conns);
|
|
|
|
kfree(csdev->refcnt);
|
2014-11-03 11:07:35 -07:00
|
|
|
kfree(csdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int coresight_orphan_match(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
bool still_orphan = false;
|
|
|
|
struct coresight_device *csdev, *i_csdev;
|
|
|
|
struct coresight_connection *conn;
|
|
|
|
|
|
|
|
csdev = data;
|
|
|
|
i_csdev = to_coresight_device(dev);
|
|
|
|
|
|
|
|
/* No need to check oneself */
|
|
|
|
if (csdev == i_csdev)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Move on to another component if no connection is orphan */
|
|
|
|
if (!i_csdev->orphan)
|
|
|
|
return 0;
|
|
|
|
/*
|
|
|
|
* Circle throuch all the connection of that component. If we find
|
|
|
|
* an orphan connection whose name matches @csdev, link it.
|
|
|
|
*/
|
2015-01-26 09:22:20 -07:00
|
|
|
for (i = 0; i < i_csdev->nr_outport; i++) {
|
2014-11-03 11:07:35 -07:00
|
|
|
conn = &i_csdev->conns[i];
|
|
|
|
|
|
|
|
/* We have found at least one orphan connection */
|
|
|
|
if (conn->child_dev == NULL) {
|
|
|
|
/* Does it match this newly added device? */
|
2016-08-25 15:18:51 -06:00
|
|
|
if (conn->child_name &&
|
|
|
|
!strcmp(dev_name(&csdev->dev), conn->child_name)) {
|
2014-11-03 11:07:35 -07:00
|
|
|
conn->child_dev = csdev;
|
2015-01-26 09:22:19 -07:00
|
|
|
} else {
|
|
|
|
/* This component still has an orphan */
|
|
|
|
still_orphan = true;
|
|
|
|
}
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
i_csdev->orphan = still_orphan;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Returning '0' ensures that all known component on the
|
|
|
|
* bus will be checked.
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void coresight_fixup_orphan_conns(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* No need to check for a return value as orphan connection(s)
|
|
|
|
* are hooked-up with each newly added component.
|
|
|
|
*/
|
|
|
|
bus_for_each_dev(&coresight_bustype, NULL,
|
2016-02-02 14:13:55 -07:00
|
|
|
csdev, coresight_orphan_match);
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void coresight_fixup_device_conns(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < csdev->nr_outport; i++) {
|
2017-12-18 11:05:42 -07:00
|
|
|
struct coresight_connection *conn = &csdev->conns[i];
|
|
|
|
struct device *dev = NULL;
|
2014-11-03 11:07:35 -07:00
|
|
|
|
2017-12-18 11:05:42 -07:00
|
|
|
if (conn->child_name)
|
|
|
|
dev = bus_find_device_by_name(&coresight_bustype, NULL,
|
|
|
|
conn->child_name);
|
2014-11-03 11:07:35 -07:00
|
|
|
if (dev) {
|
|
|
|
conn->child_dev = to_coresight_device(dev);
|
2016-02-02 14:13:58 -07:00
|
|
|
/* and put reference from 'bus_find_device()' */
|
|
|
|
put_device(dev);
|
2014-11-03 11:07:35 -07:00
|
|
|
} else {
|
|
|
|
csdev->orphan = true;
|
|
|
|
conn->child_dev = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-02 14:13:59 -07:00
|
|
|
static int coresight_remove_match(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct coresight_device *csdev, *iterator;
|
|
|
|
struct coresight_connection *conn;
|
|
|
|
|
|
|
|
csdev = data;
|
|
|
|
iterator = to_coresight_device(dev);
|
|
|
|
|
|
|
|
/* No need to check oneself */
|
|
|
|
if (csdev == iterator)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Circle throuch all the connection of that component. If we find
|
|
|
|
* a connection whose name matches @csdev, remove it.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < iterator->nr_outport; i++) {
|
|
|
|
conn = &iterator->conns[i];
|
|
|
|
|
|
|
|
if (conn->child_dev == NULL)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!strcmp(dev_name(&csdev->dev), conn->child_name)) {
|
|
|
|
iterator->orphan = true;
|
|
|
|
conn->child_dev = NULL;
|
|
|
|
/* No need to continue */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Returning '0' ensures that all known component on the
|
|
|
|
* bus will be checked.
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void coresight_remove_conns(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
bus_for_each_dev(&coresight_bustype, NULL,
|
|
|
|
csdev, coresight_remove_match);
|
|
|
|
}
|
|
|
|
|
2014-11-03 11:07:35 -07:00
|
|
|
/**
|
|
|
|
* coresight_timeout - loop until a bit has changed to a specific state.
|
|
|
|
* @addr: base address of the area of interest.
|
|
|
|
* @offset: address of a register, starting from @addr.
|
|
|
|
* @position: the position of the bit of interest.
|
|
|
|
* @value: the value the bit should have.
|
|
|
|
*
|
|
|
|
* Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
|
|
|
|
* TIMEOUT_US has elapsed, which ever happens first.
|
|
|
|
*/
|
|
|
|
|
|
|
|
int coresight_timeout(void __iomem *addr, u32 offset, int position, int value)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
for (i = TIMEOUT_US; i > 0; i--) {
|
|
|
|
val = __raw_readl(addr + offset);
|
|
|
|
/* waiting on the bit to go from 0 to 1 */
|
|
|
|
if (value) {
|
|
|
|
if (val & BIT(position))
|
|
|
|
return 0;
|
|
|
|
/* waiting on the bit to go from 1 to 0 */
|
|
|
|
} else {
|
|
|
|
if (!(val & BIT(position)))
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Delay is arbitrary - the specification doesn't say how long
|
|
|
|
* we are expected to wait. Extra check required to make sure
|
|
|
|
* we don't wait needlessly on the last iteration.
|
|
|
|
*/
|
|
|
|
if (i - 1)
|
|
|
|
udelay(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct bus_type coresight_bustype = {
|
|
|
|
.name = "coresight",
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init coresight_init(void)
|
|
|
|
{
|
|
|
|
return bus_register(&coresight_bustype);
|
|
|
|
}
|
|
|
|
postcore_initcall(coresight_init);
|
|
|
|
|
|
|
|
struct coresight_device *coresight_register(struct coresight_desc *desc)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int link_subtype;
|
|
|
|
int nr_refcnts = 1;
|
|
|
|
atomic_t *refcnts = NULL;
|
|
|
|
struct coresight_device *csdev;
|
|
|
|
|
|
|
|
csdev = kzalloc(sizeof(*csdev), GFP_KERNEL);
|
|
|
|
if (!csdev) {
|
|
|
|
ret = -ENOMEM;
|
2018-09-20 13:17:36 -06:00
|
|
|
goto err_out;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (desc->type == CORESIGHT_DEV_TYPE_LINK ||
|
|
|
|
desc->type == CORESIGHT_DEV_TYPE_LINKSINK) {
|
|
|
|
link_subtype = desc->subtype.link_subtype;
|
|
|
|
|
|
|
|
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG)
|
|
|
|
nr_refcnts = desc->pdata->nr_inport;
|
|
|
|
else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT)
|
|
|
|
nr_refcnts = desc->pdata->nr_outport;
|
|
|
|
}
|
|
|
|
|
|
|
|
refcnts = kcalloc(nr_refcnts, sizeof(*refcnts), GFP_KERNEL);
|
|
|
|
if (!refcnts) {
|
|
|
|
ret = -ENOMEM;
|
2018-09-20 13:17:36 -06:00
|
|
|
goto err_free_csdev;
|
2014-11-03 11:07:35 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
csdev->refcnt = refcnts;
|
|
|
|
|
|
|
|
csdev->nr_inport = desc->pdata->nr_inport;
|
|
|
|
csdev->nr_outport = desc->pdata->nr_outport;
|
|
|
|
|
2018-09-20 13:17:42 -06:00
|
|
|
csdev->conns = desc->pdata->conns;
|
2014-11-03 11:07:35 -07:00
|
|
|
|
|
|
|
csdev->type = desc->type;
|
|
|
|
csdev->subtype = desc->subtype;
|
|
|
|
csdev->ops = desc->ops;
|
|
|
|
csdev->orphan = false;
|
|
|
|
|
|
|
|
csdev->dev.type = &coresight_dev_type[desc->type];
|
|
|
|
csdev->dev.groups = desc->groups;
|
|
|
|
csdev->dev.parent = desc->dev;
|
|
|
|
csdev->dev.release = coresight_device_release;
|
|
|
|
csdev->dev.bus = &coresight_bustype;
|
|
|
|
dev_set_name(&csdev->dev, "%s", desc->pdata->name);
|
|
|
|
|
|
|
|
ret = device_register(&csdev->dev);
|
2018-05-09 12:06:03 -06:00
|
|
|
if (ret) {
|
|
|
|
put_device(&csdev->dev);
|
2018-09-20 13:17:36 -06:00
|
|
|
/*
|
|
|
|
* All resources are free'd explicitly via
|
|
|
|
* coresight_device_release(), triggered from put_device().
|
|
|
|
*/
|
|
|
|
goto err_out;
|
2018-05-09 12:06:03 -06:00
|
|
|
}
|
2014-11-03 11:07:35 -07:00
|
|
|
|
coresight: perf: Add "sinks" group to PMU directory
Add a "sinks" directory entry so that users can see all the sinks
available in the system in a single place. Individual sink are added
as they are registered with the coresight bus.
Committer tests:
Test built on a ubuntu 18.04 container with a cross build environment to
arm64, the new field is there, need to find a machine with this feature
to do further testing in the future.
root@d15263e5734a:/git/perf# grep CORESIGHT /tmp/build/v5.0-rc2+/.config
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINKS_AND_SINKS=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_CATU=y
CONFIG_CORESIGHT_SINK_TPIU=y
CONFIG_CORESIGHT_SINK_ETBV10=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CPU_DEBUG=m
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# file /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/*.o
.../coresight/coresight-catu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.mod.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-dynamic-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etb10.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm-perf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x-sysfs.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-funnel.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-stm.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etr.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tpiu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/of_coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# pahole -C coresight_device /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/coresight.o
struct coresight_device {
struct coresight_connection * conns; /* 0 8 */
int nr_inport; /* 8 4 */
int nr_outport; /* 12 4 */
enum coresight_dev_type type; /* 16 4 */
union coresight_dev_subtype subtype; /* 20 8 */
/* XXX 4 bytes hole, try to pack */
const struct coresight_ops * ops; /* 32 8 */
struct device dev; /* 40 1408 */
/* XXX last struct has 7 bytes of padding */
/* --- cacheline 22 boundary (1408 bytes) was 40 bytes ago --- */
atomic_t * refcnt; /* 1448 8 */
bool orphan; /* 1456 1 */
bool enable; /* 1457 1 */
bool activated; /* 1458 1 */
/* XXX 5 bytes hole, try to pack */
struct dev_ext_attribute * ea; /* 1464 8 */
/* size: 1472, cachelines: 23, members: 12 */
/* sum members: 1463, holes: 2, sum holes: 9 */
/* paddings: 1, sum paddings: 7 */
};
root@d15263e5734a:/git/perf#
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Link: http://lkml.kernel.org/r/20190131184714.20388-3-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-01-31 11:47:09 -07:00
|
|
|
if (csdev->type == CORESIGHT_DEV_TYPE_SINK ||
|
|
|
|
csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) {
|
|
|
|
ret = etm_perf_add_symlink_sink(csdev);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
device_unregister(&csdev->dev);
|
|
|
|
/*
|
|
|
|
* As with the above, all resources are free'd
|
|
|
|
* explicitly via coresight_device_release() triggered
|
|
|
|
* from put_device(), which is in turn called from
|
|
|
|
* function device_unregister().
|
|
|
|
*/
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-03 11:07:35 -07:00
|
|
|
mutex_lock(&coresight_mutex);
|
|
|
|
|
|
|
|
coresight_fixup_device_conns(csdev);
|
|
|
|
coresight_fixup_orphan_conns(csdev);
|
|
|
|
|
|
|
|
mutex_unlock(&coresight_mutex);
|
|
|
|
|
|
|
|
return csdev;
|
|
|
|
|
2018-09-20 13:17:36 -06:00
|
|
|
err_free_csdev:
|
2014-11-03 11:07:35 -07:00
|
|
|
kfree(csdev);
|
2018-09-20 13:17:36 -06:00
|
|
|
err_out:
|
2014-11-03 11:07:35 -07:00
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(coresight_register);
|
|
|
|
|
|
|
|
void coresight_unregister(struct coresight_device *csdev)
|
|
|
|
{
|
coresight: perf: Add "sinks" group to PMU directory
Add a "sinks" directory entry so that users can see all the sinks
available in the system in a single place. Individual sink are added
as they are registered with the coresight bus.
Committer tests:
Test built on a ubuntu 18.04 container with a cross build environment to
arm64, the new field is there, need to find a machine with this feature
to do further testing in the future.
root@d15263e5734a:/git/perf# grep CORESIGHT /tmp/build/v5.0-rc2+/.config
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINKS_AND_SINKS=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_CATU=y
CONFIG_CORESIGHT_SINK_TPIU=y
CONFIG_CORESIGHT_SINK_ETBV10=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CPU_DEBUG=m
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# file /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/*.o
.../coresight/coresight-catu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.mod.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-dynamic-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etb10.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm-perf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x-sysfs.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-funnel.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-stm.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etr.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tpiu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/of_coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# pahole -C coresight_device /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/coresight.o
struct coresight_device {
struct coresight_connection * conns; /* 0 8 */
int nr_inport; /* 8 4 */
int nr_outport; /* 12 4 */
enum coresight_dev_type type; /* 16 4 */
union coresight_dev_subtype subtype; /* 20 8 */
/* XXX 4 bytes hole, try to pack */
const struct coresight_ops * ops; /* 32 8 */
struct device dev; /* 40 1408 */
/* XXX last struct has 7 bytes of padding */
/* --- cacheline 22 boundary (1408 bytes) was 40 bytes ago --- */
atomic_t * refcnt; /* 1448 8 */
bool orphan; /* 1456 1 */
bool enable; /* 1457 1 */
bool activated; /* 1458 1 */
/* XXX 5 bytes hole, try to pack */
struct dev_ext_attribute * ea; /* 1464 8 */
/* size: 1472, cachelines: 23, members: 12 */
/* sum members: 1463, holes: 2, sum holes: 9 */
/* paddings: 1, sum paddings: 7 */
};
root@d15263e5734a:/git/perf#
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Link: http://lkml.kernel.org/r/20190131184714.20388-3-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-01-31 11:47:09 -07:00
|
|
|
etm_perf_del_symlink_sink(csdev);
|
2016-02-02 14:13:59 -07:00
|
|
|
/* Remove references of that device in the topology */
|
|
|
|
coresight_remove_conns(csdev);
|
2014-11-03 11:07:35 -07:00
|
|
|
device_unregister(&csdev->dev);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(coresight_unregister);
|