2019-02-15 15:39:22 -07:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2016-2019 HabanaLabs, Ltd.
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* All Rights Reserved.
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*/
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#include "habanalabs.h"
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#include "include/hw_ip/mmu/mmu_general.h"
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#include <linux/genalloc.h>
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#include <linux/slab.h>
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static struct pgt_info *get_pgt_info(struct hl_ctx *ctx, u64 addr)
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{
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struct pgt_info *pgt_info = NULL;
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hash_for_each_possible(ctx->mmu_hash, pgt_info, node,
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(unsigned long) addr)
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if (addr == pgt_info->addr)
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break;
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return pgt_info;
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}
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static void free_hop(struct hl_ctx *ctx, u64 hop_addr)
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{
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struct pgt_info *pgt_info = get_pgt_info(ctx, hop_addr);
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gen_pool_free(pgt_info->ctx->hdev->mmu_pgt_pool, pgt_info->addr,
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ctx->hdev->asic_prop.mmu_hop_table_size);
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hash_del(&pgt_info->node);
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kfree(pgt_info);
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}
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static u64 alloc_hop(struct hl_ctx *ctx)
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{
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struct hl_device *hdev = ctx->hdev;
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struct pgt_info *pgt_info;
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u64 addr;
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pgt_info = kmalloc(sizeof(*pgt_info), GFP_KERNEL);
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if (!pgt_info)
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return ULLONG_MAX;
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addr = (u64) gen_pool_alloc(hdev->mmu_pgt_pool,
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hdev->asic_prop.mmu_hop_table_size);
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if (!addr) {
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dev_err(hdev->dev, "failed to allocate page\n");
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kfree(pgt_info);
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return ULLONG_MAX;
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}
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pgt_info->addr = addr;
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pgt_info->ctx = ctx;
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pgt_info->num_of_ptes = 0;
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hash_add(ctx->mmu_hash, &pgt_info->node, addr);
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return addr;
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}
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static inline void clear_pte(struct hl_device *hdev, u64 pte_addr)
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{
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/* clear the last and present bits */
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hdev->asic_funcs->write_pte(hdev, pte_addr, 0);
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}
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static inline void get_pte(struct hl_ctx *ctx, u64 hop_addr)
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{
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get_pgt_info(ctx, hop_addr)->num_of_ptes++;
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}
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/*
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* put_pte - decrement the num of ptes and free the hop if possible
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*
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* @ctx: pointer to the context structure
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* @hop_addr: addr of the hop
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*
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* This function returns the number of ptes left on this hop. If the number is
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* 0, it means the pte was freed.
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*/
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static inline int put_pte(struct hl_ctx *ctx, u64 hop_addr)
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{
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struct pgt_info *pgt_info = get_pgt_info(ctx, hop_addr);
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int num_of_ptes_left;
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pgt_info->num_of_ptes--;
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/*
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* Need to save the number of ptes left because free_hop might free
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* the pgt_info
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*/
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num_of_ptes_left = pgt_info->num_of_ptes;
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if (!num_of_ptes_left)
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free_hop(ctx, hop_addr);
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return num_of_ptes_left;
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}
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static inline u64 get_hop0_addr(struct hl_ctx *ctx)
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{
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return ctx->hdev->asic_prop.mmu_pgt_addr +
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(ctx->asid * ctx->hdev->asic_prop.mmu_hop_table_size);
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}
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static inline u64 get_hopN_pte_addr(struct hl_ctx *ctx, u64 hop_addr,
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u64 virt_addr, u64 mask, u64 shift)
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{
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return hop_addr + ctx->hdev->asic_prop.mmu_pte_size *
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((virt_addr & mask) >> shift);
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}
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static inline u64 get_hop0_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr)
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{
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return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP0_MASK, HOP0_SHIFT);
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}
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static inline u64 get_hop1_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr)
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{
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return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP1_MASK, HOP1_SHIFT);
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}
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static inline u64 get_hop2_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr)
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{
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return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP2_MASK, HOP2_SHIFT);
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}
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static inline u64 get_hop3_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr)
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{
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return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP3_MASK, HOP3_SHIFT);
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}
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static inline u64 get_hop4_pte_addr(struct hl_ctx *ctx, u64 hop_addr, u64 vaddr)
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{
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return get_hopN_pte_addr(ctx, hop_addr, vaddr, HOP4_MASK, HOP4_SHIFT);
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}
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static inline u64 get_next_hop_addr(u64 curr_pte)
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{
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if (curr_pte & PAGE_PRESENT_MASK)
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return curr_pte & PHYS_ADDR_MASK;
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else
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return ULLONG_MAX;
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}
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static inline u64 get_alloc_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte,
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bool *is_new_hop)
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{
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u64 hop_addr = get_next_hop_addr(curr_pte);
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if (hop_addr == ULLONG_MAX) {
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hop_addr = alloc_hop(ctx);
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2019-02-28 01:46:11 -07:00
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*is_new_hop = (hop_addr != ULLONG_MAX);
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2019-02-15 15:39:22 -07:00
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}
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return hop_addr;
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}
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/*
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* hl_mmu_init - init the mmu module
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*
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* @hdev: pointer to the habanalabs device structure
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*
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* This function does the following:
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* - Allocate max_asid zeroed hop0 pgts so no mapping is available
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* - Enable mmu in hw
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* - Invalidate the mmu cache
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* - Create a pool of pages for pgts
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* - Returns 0 on success
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*
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* This function depends on DMA QMAN to be working!
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*/
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int hl_mmu_init(struct hl_device *hdev)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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int rc;
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if (!hdev->mmu_enable)
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return 0;
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/* MMU HW init was already done in device hw_init() */
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mutex_init(&hdev->mmu_cache_lock);
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hdev->mmu_pgt_pool =
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gen_pool_create(__ffs(prop->mmu_hop_table_size), -1);
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if (!hdev->mmu_pgt_pool) {
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dev_err(hdev->dev, "Failed to create page gen pool\n");
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rc = -ENOMEM;
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goto err_pool_create;
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}
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rc = gen_pool_add(hdev->mmu_pgt_pool, prop->mmu_pgt_addr +
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prop->mmu_hop0_tables_total_size,
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prop->mmu_pgt_size - prop->mmu_hop0_tables_total_size,
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-1);
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if (rc) {
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dev_err(hdev->dev, "Failed to add memory to page gen pool\n");
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goto err_pool_add;
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}
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return 0;
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err_pool_add:
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gen_pool_destroy(hdev->mmu_pgt_pool);
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err_pool_create:
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mutex_destroy(&hdev->mmu_cache_lock);
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return rc;
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}
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/*
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* hl_mmu_fini - release the mmu module.
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*
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* @hdev: pointer to the habanalabs device structure
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*
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* This function does the following:
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* - Disable mmu in hw
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* - free the pgts pool
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*
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* All ctxs should be freed before calling this func
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*/
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void hl_mmu_fini(struct hl_device *hdev)
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{
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if (!hdev->mmu_enable)
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return;
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gen_pool_destroy(hdev->mmu_pgt_pool);
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mutex_destroy(&hdev->mmu_cache_lock);
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/* MMU HW fini will be done in device hw_fini() */
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}
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2019-02-28 01:46:11 -07:00
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/**
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* hl_mmu_ctx_init() - initialize a context for using the MMU module.
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* @ctx: pointer to the context structure to initialize.
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2019-02-15 15:39:22 -07:00
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*
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2019-02-28 01:46:11 -07:00
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* Initialize a mutex to protect the concurrent mapping flow, a hash to hold all
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* page tables hops related to this context and an optional DRAM default page
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* mapping.
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* Return: 0 on success, non-zero otherwise.
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2019-02-15 15:39:22 -07:00
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*/
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2019-02-28 01:46:11 -07:00
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int hl_mmu_ctx_init(struct hl_ctx *ctx)
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2019-02-15 15:39:22 -07:00
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{
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2019-02-28 01:46:11 -07:00
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struct hl_device *hdev = ctx->hdev;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 num_of_hop3, total_hops, hop1_addr, hop2_addr, hop2_pte_addr,
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hop3_pte_addr, pte_val;
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int rc, i, j, hop3_allocated = 0;
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if (!hdev->mmu_enable)
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return 0;
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2019-02-15 15:39:22 -07:00
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mutex_init(&ctx->mmu_lock);
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hash_init(ctx->mmu_hash);
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2019-02-28 01:46:11 -07:00
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if (!hdev->dram_supports_virtual_memory ||
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!hdev->dram_default_page_mapping)
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return 0;
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2019-03-01 05:21:11 -07:00
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num_of_hop3 = prop->dram_size_for_default_page_mapping;
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do_div(num_of_hop3, prop->dram_page_size);
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do_div(num_of_hop3, PTE_ENTRIES_IN_HOP);
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2019-02-28 01:46:11 -07:00
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/* add hop1 and hop2 */
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total_hops = num_of_hop3 + 2;
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ctx->dram_default_hops = kzalloc(HL_PTE_SIZE * total_hops, GFP_KERNEL);
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if (!ctx->dram_default_hops) {
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rc = -ENOMEM;
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goto alloc_err;
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}
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hop1_addr = alloc_hop(ctx);
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if (hop1_addr == ULLONG_MAX) {
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dev_err(hdev->dev, "failed to alloc hop 1\n");
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rc = -ENOMEM;
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goto hop1_err;
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}
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ctx->dram_default_hops[total_hops - 1] = hop1_addr;
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hop2_addr = alloc_hop(ctx);
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if (hop2_addr == ULLONG_MAX) {
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dev_err(hdev->dev, "failed to alloc hop 2\n");
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rc = -ENOMEM;
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goto hop2_err;
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}
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ctx->dram_default_hops[total_hops - 2] = hop2_addr;
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for (i = 0 ; i < num_of_hop3 ; i++) {
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ctx->dram_default_hops[i] = alloc_hop(ctx);
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if (ctx->dram_default_hops[i] == ULLONG_MAX) {
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dev_err(hdev->dev, "failed to alloc hop 3, i: %d\n", i);
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rc = -ENOMEM;
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goto hop3_err;
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}
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hop3_allocated++;
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}
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/* need only pte 0 in hops 0 and 1 */
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pte_val = (hop1_addr & PTE_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
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hdev->asic_funcs->write_pte(hdev, get_hop0_addr(ctx), pte_val);
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pte_val = (hop2_addr & PTE_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
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hdev->asic_funcs->write_pte(hdev, hop1_addr, pte_val);
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get_pte(ctx, hop1_addr);
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hop2_pte_addr = hop2_addr;
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for (i = 0 ; i < num_of_hop3 ; i++) {
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pte_val = (ctx->dram_default_hops[i] & PTE_PHYS_ADDR_MASK) |
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PAGE_PRESENT_MASK;
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hdev->asic_funcs->write_pte(hdev, hop2_pte_addr, pte_val);
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get_pte(ctx, hop2_addr);
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hop2_pte_addr += HL_PTE_SIZE;
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}
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pte_val = (prop->mmu_dram_default_page_addr & PTE_PHYS_ADDR_MASK) |
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LAST_MASK | PAGE_PRESENT_MASK;
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for (i = 0 ; i < num_of_hop3 ; i++) {
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hop3_pte_addr = ctx->dram_default_hops[i];
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for (j = 0 ; j < PTE_ENTRIES_IN_HOP ; j++) {
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hdev->asic_funcs->write_pte(hdev, hop3_pte_addr,
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pte_val);
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get_pte(ctx, ctx->dram_default_hops[i]);
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hop3_pte_addr += HL_PTE_SIZE;
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}
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}
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/* flush all writes to reach PCI */
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mb();
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hdev->asic_funcs->read_pte(hdev, hop2_addr);
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return 0;
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hop3_err:
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for (i = 0 ; i < hop3_allocated ; i++)
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free_hop(ctx, ctx->dram_default_hops[i]);
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free_hop(ctx, hop2_addr);
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hop2_err:
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free_hop(ctx, hop1_addr);
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hop1_err:
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kfree(ctx->dram_default_hops);
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alloc_err:
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mutex_destroy(&ctx->mmu_lock);
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|
|
|
|
|
|
return rc;
|
2019-02-15 15:39:22 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_mmu_ctx_fini - disable a ctx from using the mmu module
|
|
|
|
*
|
|
|
|
* @ctx: pointer to the context structure
|
|
|
|
*
|
|
|
|
* This function does the following:
|
|
|
|
* - Free any pgts which were not freed yet
|
|
|
|
* - Free the mutex
|
2019-02-28 01:46:11 -07:00
|
|
|
* - Free DRAM default page mapping hops
|
2019-02-15 15:39:22 -07:00
|
|
|
*/
|
|
|
|
void hl_mmu_ctx_fini(struct hl_ctx *ctx)
|
|
|
|
{
|
2019-02-28 01:46:11 -07:00
|
|
|
struct hl_device *hdev = ctx->hdev;
|
|
|
|
struct asic_fixed_properties *prop = &hdev->asic_prop;
|
2019-02-15 15:39:22 -07:00
|
|
|
struct pgt_info *pgt_info;
|
|
|
|
struct hlist_node *tmp;
|
2019-02-28 01:46:11 -07:00
|
|
|
u64 num_of_hop3, total_hops, hop1_addr, hop2_addr, hop2_pte_addr,
|
|
|
|
hop3_pte_addr;
|
|
|
|
int i, j;
|
2019-02-15 15:39:22 -07:00
|
|
|
|
|
|
|
if (!ctx->hdev->mmu_enable)
|
|
|
|
return;
|
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
if (hdev->dram_supports_virtual_memory &&
|
|
|
|
hdev->dram_default_page_mapping) {
|
|
|
|
|
2019-03-01 05:21:11 -07:00
|
|
|
num_of_hop3 = prop->dram_size_for_default_page_mapping;
|
|
|
|
do_div(num_of_hop3, prop->dram_page_size);
|
|
|
|
do_div(num_of_hop3, PTE_ENTRIES_IN_HOP);
|
2019-02-28 01:46:11 -07:00
|
|
|
|
|
|
|
/* add hop1 and hop2 */
|
|
|
|
total_hops = num_of_hop3 + 2;
|
|
|
|
hop1_addr = ctx->dram_default_hops[total_hops - 1];
|
|
|
|
hop2_addr = ctx->dram_default_hops[total_hops - 2];
|
|
|
|
|
|
|
|
for (i = 0 ; i < num_of_hop3 ; i++) {
|
|
|
|
hop3_pte_addr = ctx->dram_default_hops[i];
|
|
|
|
for (j = 0 ; j < PTE_ENTRIES_IN_HOP ; j++) {
|
|
|
|
clear_pte(hdev, hop3_pte_addr);
|
|
|
|
put_pte(ctx, ctx->dram_default_hops[i]);
|
|
|
|
hop3_pte_addr += HL_PTE_SIZE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
hop2_pte_addr = hop2_addr;
|
|
|
|
for (i = 0 ; i < num_of_hop3 ; i++) {
|
|
|
|
clear_pte(hdev, hop2_pte_addr);
|
|
|
|
put_pte(ctx, hop2_addr);
|
|
|
|
hop2_pte_addr += HL_PTE_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
clear_pte(hdev, hop1_addr);
|
|
|
|
put_pte(ctx, hop1_addr);
|
|
|
|
clear_pte(hdev, get_hop0_addr(ctx));
|
|
|
|
|
|
|
|
kfree(ctx->dram_default_hops);
|
|
|
|
|
|
|
|
/* flush all writes to reach PCI */
|
|
|
|
mb();
|
|
|
|
hdev->asic_funcs->read_pte(hdev, hop2_addr);
|
|
|
|
}
|
|
|
|
|
2019-02-15 15:39:22 -07:00
|
|
|
if (!hash_empty(ctx->mmu_hash))
|
2019-02-28 01:46:11 -07:00
|
|
|
dev_err(hdev->dev, "ctx is freed while it has pgts in use\n");
|
2019-02-15 15:39:22 -07:00
|
|
|
|
|
|
|
hash_for_each_safe(ctx->mmu_hash, i, tmp, pgt_info, node) {
|
2019-02-28 01:46:11 -07:00
|
|
|
dev_err(hdev->dev,
|
2019-02-15 15:39:22 -07:00
|
|
|
"pgt_info of addr 0x%llx of asid %d was not destroyed, num_ptes: %d\n",
|
|
|
|
pgt_info->addr, ctx->asid, pgt_info->num_of_ptes);
|
|
|
|
free_hop(ctx, pgt_info->addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_destroy(&ctx->mmu_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int _hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr)
|
|
|
|
{
|
|
|
|
struct hl_device *hdev = ctx->hdev;
|
2019-02-28 01:46:11 -07:00
|
|
|
struct asic_fixed_properties *prop = &hdev->asic_prop;
|
2019-02-15 15:39:22 -07:00
|
|
|
u64 hop0_addr = 0, hop0_pte_addr = 0,
|
|
|
|
hop1_addr = 0, hop1_pte_addr = 0,
|
|
|
|
hop2_addr = 0, hop2_pte_addr = 0,
|
|
|
|
hop3_addr = 0, hop3_pte_addr = 0,
|
|
|
|
hop4_addr = 0, hop4_pte_addr = 0,
|
|
|
|
curr_pte;
|
|
|
|
int clear_hop3 = 1;
|
2019-02-28 01:46:11 -07:00
|
|
|
bool is_dram_addr, is_huge, is_dram_default_page_mapping;
|
|
|
|
|
|
|
|
is_dram_addr = hl_mem_area_inside_range(virt_addr, PAGE_SIZE_2MB,
|
|
|
|
prop->va_space_dram_start_address,
|
|
|
|
prop->va_space_dram_end_address);
|
2019-02-15 15:39:22 -07:00
|
|
|
|
|
|
|
hop0_addr = get_hop0_addr(ctx);
|
|
|
|
|
|
|
|
hop0_pte_addr = get_hop0_pte_addr(ctx, hop0_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop0_pte_addr);
|
|
|
|
|
|
|
|
hop1_addr = get_next_hop_addr(curr_pte);
|
|
|
|
|
|
|
|
if (hop1_addr == ULLONG_MAX)
|
|
|
|
goto not_mapped;
|
|
|
|
|
|
|
|
hop1_pte_addr = get_hop1_pte_addr(ctx, hop1_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop1_pte_addr);
|
|
|
|
|
|
|
|
hop2_addr = get_next_hop_addr(curr_pte);
|
|
|
|
|
|
|
|
if (hop2_addr == ULLONG_MAX)
|
|
|
|
goto not_mapped;
|
|
|
|
|
|
|
|
hop2_pte_addr = get_hop2_pte_addr(ctx, hop2_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop2_pte_addr);
|
|
|
|
|
|
|
|
hop3_addr = get_next_hop_addr(curr_pte);
|
|
|
|
|
|
|
|
if (hop3_addr == ULLONG_MAX)
|
|
|
|
goto not_mapped;
|
|
|
|
|
|
|
|
hop3_pte_addr = get_hop3_pte_addr(ctx, hop3_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop3_pte_addr);
|
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
is_huge = curr_pte & LAST_MASK;
|
|
|
|
|
|
|
|
if (is_dram_addr && !is_huge) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"DRAM unmapping should use huge pages only\n");
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
is_dram_default_page_mapping =
|
|
|
|
hdev->dram_default_page_mapping && is_dram_addr;
|
|
|
|
|
|
|
|
if (!is_huge) {
|
2019-02-15 15:39:22 -07:00
|
|
|
hop4_addr = get_next_hop_addr(curr_pte);
|
|
|
|
|
|
|
|
if (hop4_addr == ULLONG_MAX)
|
|
|
|
goto not_mapped;
|
|
|
|
|
|
|
|
hop4_pte_addr = get_hop4_pte_addr(ctx, hop4_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop4_pte_addr);
|
|
|
|
|
|
|
|
clear_hop3 = 0;
|
|
|
|
}
|
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
if (is_dram_default_page_mapping) {
|
|
|
|
u64 zero_pte = (prop->mmu_dram_default_page_addr &
|
|
|
|
PTE_PHYS_ADDR_MASK) | LAST_MASK |
|
|
|
|
PAGE_PRESENT_MASK;
|
|
|
|
if (curr_pte == zero_pte) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"DRAM: hop3 PTE points to zero page, can't unmap, va: 0x%llx\n",
|
|
|
|
virt_addr);
|
|
|
|
goto not_mapped;
|
|
|
|
}
|
2019-02-15 15:39:22 -07:00
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
if (!(curr_pte & PAGE_PRESENT_MASK)) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"DRAM: hop3 PTE is cleared! can't unmap, va: 0x%llx\n",
|
|
|
|
virt_addr);
|
|
|
|
goto not_mapped;
|
|
|
|
}
|
|
|
|
|
|
|
|
hdev->asic_funcs->write_pte(hdev, hop3_pte_addr, zero_pte);
|
|
|
|
put_pte(ctx, hop3_addr);
|
|
|
|
} else {
|
|
|
|
if (!(curr_pte & PAGE_PRESENT_MASK))
|
|
|
|
goto not_mapped;
|
2019-02-15 15:39:22 -07:00
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
clear_pte(hdev, hop4_addr ? hop4_pte_addr : hop3_pte_addr);
|
2019-02-15 15:39:22 -07:00
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
if (hop4_addr && !put_pte(ctx, hop4_addr))
|
|
|
|
clear_hop3 = 1;
|
2019-02-15 15:39:22 -07:00
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
if (!clear_hop3)
|
|
|
|
goto flush;
|
|
|
|
clear_pte(hdev, hop3_pte_addr);
|
2019-02-15 15:39:22 -07:00
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
if (put_pte(ctx, hop3_addr))
|
|
|
|
goto flush;
|
|
|
|
clear_pte(hdev, hop2_pte_addr);
|
2019-02-15 15:39:22 -07:00
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
if (put_pte(ctx, hop2_addr))
|
|
|
|
goto flush;
|
|
|
|
clear_pte(hdev, hop1_pte_addr);
|
|
|
|
|
|
|
|
if (put_pte(ctx, hop1_addr))
|
|
|
|
goto flush;
|
|
|
|
clear_pte(hdev, hop0_pte_addr);
|
|
|
|
}
|
2019-02-15 15:39:22 -07:00
|
|
|
|
|
|
|
flush:
|
|
|
|
/* flush all writes from all cores to reach PCI */
|
|
|
|
mb();
|
|
|
|
|
|
|
|
hdev->asic_funcs->read_pte(hdev,
|
|
|
|
hop4_addr ? hop4_pte_addr : hop3_pte_addr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
not_mapped:
|
|
|
|
dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n",
|
|
|
|
virt_addr);
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_mmu_unmap - unmaps a virtual addr
|
|
|
|
*
|
|
|
|
* @ctx: pointer to the context structure
|
|
|
|
* @virt_addr: virt addr to map from
|
|
|
|
* @page_size: size of the page to unmap
|
|
|
|
*
|
|
|
|
* This function does the following:
|
|
|
|
* - Check that the virt addr is mapped
|
|
|
|
* - Unmap the virt addr and frees pgts if possible
|
|
|
|
* - Returns 0 on success, -EINVAL if the given addr is not mapped
|
|
|
|
*
|
|
|
|
* Because this function changes the page tables in the device and because it
|
|
|
|
* changes the MMU hash, it must be protected by a lock.
|
|
|
|
* However, because it maps only a single page, the lock should be implemented
|
|
|
|
* in a higher level in order to protect the entire mapping of the memory area
|
|
|
|
*/
|
|
|
|
int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size)
|
|
|
|
{
|
|
|
|
struct hl_device *hdev = ctx->hdev;
|
|
|
|
u64 real_virt_addr;
|
|
|
|
u32 real_page_size, npages;
|
|
|
|
int i, rc;
|
|
|
|
|
|
|
|
if (!hdev->mmu_enable)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The H/W handles mapping of 4KB/2MB page. Hence if the host page size
|
|
|
|
* is bigger, we break it to sub-pages and unmap them separately.
|
|
|
|
*/
|
|
|
|
if ((page_size % PAGE_SIZE_2MB) == 0) {
|
|
|
|
real_page_size = PAGE_SIZE_2MB;
|
|
|
|
} else if ((page_size % PAGE_SIZE_4KB) == 0) {
|
|
|
|
real_page_size = PAGE_SIZE_4KB;
|
|
|
|
} else {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"page size of %u is not 4KB nor 2MB aligned, can't unmap\n",
|
|
|
|
page_size);
|
|
|
|
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
npages = page_size / real_page_size;
|
|
|
|
real_virt_addr = virt_addr;
|
|
|
|
|
|
|
|
for (i = 0 ; i < npages ; i++) {
|
|
|
|
rc = _hl_mmu_unmap(ctx, real_virt_addr);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
real_virt_addr += real_page_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int _hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
|
|
|
|
u32 page_size)
|
|
|
|
{
|
|
|
|
struct hl_device *hdev = ctx->hdev;
|
2019-02-28 01:46:11 -07:00
|
|
|
struct asic_fixed_properties *prop = &hdev->asic_prop;
|
2019-02-15 15:39:22 -07:00
|
|
|
u64 hop0_addr = 0, hop0_pte_addr = 0,
|
|
|
|
hop1_addr = 0, hop1_pte_addr = 0,
|
|
|
|
hop2_addr = 0, hop2_pte_addr = 0,
|
|
|
|
hop3_addr = 0, hop3_pte_addr = 0,
|
|
|
|
hop4_addr = 0, hop4_pte_addr = 0,
|
|
|
|
curr_pte = 0;
|
|
|
|
bool hop1_new = false, hop2_new = false, hop3_new = false,
|
2019-02-28 01:46:11 -07:00
|
|
|
hop4_new = false, is_huge, is_dram_addr,
|
|
|
|
is_dram_default_page_mapping;
|
2019-02-15 15:39:22 -07:00
|
|
|
int rc = -ENOMEM;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This mapping function can map a 4KB/2MB page. For 2MB page there are
|
|
|
|
* only 3 hops rather than 4. Currently the DRAM allocation uses 2MB
|
|
|
|
* pages only but user memory could have been allocated with one of the
|
|
|
|
* two page sizes. Since this is a common code for all the three cases,
|
|
|
|
* we need this hugs page check.
|
|
|
|
*/
|
|
|
|
is_huge = page_size == PAGE_SIZE_2MB;
|
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
is_dram_addr = hl_mem_area_inside_range(virt_addr, page_size,
|
|
|
|
prop->va_space_dram_start_address,
|
|
|
|
prop->va_space_dram_end_address);
|
|
|
|
|
|
|
|
if (is_dram_addr && !is_huge) {
|
|
|
|
dev_err(hdev->dev, "DRAM mapping should use huge pages only\n");
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
is_dram_default_page_mapping =
|
|
|
|
hdev->dram_default_page_mapping && is_dram_addr;
|
|
|
|
|
2019-02-15 15:39:22 -07:00
|
|
|
hop0_addr = get_hop0_addr(ctx);
|
|
|
|
|
|
|
|
hop0_pte_addr = get_hop0_pte_addr(ctx, hop0_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop0_pte_addr);
|
|
|
|
|
|
|
|
hop1_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop1_new);
|
|
|
|
|
|
|
|
if (hop1_addr == ULLONG_MAX)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
hop1_pte_addr = get_hop1_pte_addr(ctx, hop1_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop1_pte_addr);
|
|
|
|
|
|
|
|
hop2_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop2_new);
|
|
|
|
|
|
|
|
if (hop2_addr == ULLONG_MAX)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
hop2_pte_addr = get_hop2_pte_addr(ctx, hop2_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop2_pte_addr);
|
|
|
|
|
|
|
|
hop3_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop3_new);
|
|
|
|
|
|
|
|
if (hop3_addr == ULLONG_MAX)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
hop3_pte_addr = get_hop3_pte_addr(ctx, hop3_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop3_pte_addr);
|
|
|
|
|
|
|
|
if (!is_huge) {
|
|
|
|
hop4_addr = get_alloc_next_hop_addr(ctx, curr_pte, &hop4_new);
|
|
|
|
|
|
|
|
if (hop4_addr == ULLONG_MAX)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
hop4_pte_addr = get_hop4_pte_addr(ctx, hop4_addr, virt_addr);
|
|
|
|
|
|
|
|
curr_pte = hdev->asic_funcs->read_pte(hdev, hop4_pte_addr);
|
|
|
|
}
|
|
|
|
|
2019-02-28 01:46:11 -07:00
|
|
|
if (is_dram_default_page_mapping) {
|
|
|
|
u64 zero_pte = (prop->mmu_dram_default_page_addr &
|
|
|
|
PTE_PHYS_ADDR_MASK) | LAST_MASK |
|
|
|
|
PAGE_PRESENT_MASK;
|
|
|
|
|
|
|
|
if (curr_pte != zero_pte) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"DRAM: mapping already exists for virt_addr 0x%llx\n",
|
|
|
|
virt_addr);
|
2019-02-28 01:46:18 -07:00
|
|
|
rc = -EINVAL;
|
2019-02-28 01:46:11 -07:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hop1_new || hop2_new || hop3_new || hop4_new) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"DRAM mapping should not allocate more hops\n");
|
|
|
|
rc = -EFAULT;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
} else if (curr_pte & PAGE_PRESENT_MASK) {
|
2019-02-15 15:39:22 -07:00
|
|
|
dev_err(hdev->dev,
|
|
|
|
"mapping already exists for virt_addr 0x%llx\n",
|
|
|
|
virt_addr);
|
|
|
|
|
|
|
|
dev_dbg(hdev->dev, "hop0 pte: 0x%llx (0x%llx)\n",
|
|
|
|
hdev->asic_funcs->read_pte(hdev, hop0_pte_addr),
|
|
|
|
hop0_pte_addr);
|
|
|
|
dev_dbg(hdev->dev, "hop1 pte: 0x%llx (0x%llx)\n",
|
|
|
|
hdev->asic_funcs->read_pte(hdev, hop1_pte_addr),
|
|
|
|
hop1_pte_addr);
|
|
|
|
dev_dbg(hdev->dev, "hop2 pte: 0x%llx (0x%llx)\n",
|
|
|
|
hdev->asic_funcs->read_pte(hdev, hop2_pte_addr),
|
|
|
|
hop2_pte_addr);
|
|
|
|
dev_dbg(hdev->dev, "hop3 pte: 0x%llx (0x%llx)\n",
|
|
|
|
hdev->asic_funcs->read_pte(hdev, hop3_pte_addr),
|
|
|
|
hop3_pte_addr);
|
|
|
|
|
|
|
|
if (!is_huge)
|
|
|
|
dev_dbg(hdev->dev, "hop4 pte: 0x%llx (0x%llx)\n",
|
|
|
|
hdev->asic_funcs->read_pte(hdev,
|
|
|
|
hop4_pte_addr),
|
|
|
|
hop4_pte_addr);
|
|
|
|
|
2019-02-28 01:46:18 -07:00
|
|
|
rc = -EINVAL;
|
2019-02-15 15:39:22 -07:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
curr_pte = (phys_addr & PTE_PHYS_ADDR_MASK) | LAST_MASK
|
|
|
|
| PAGE_PRESENT_MASK;
|
|
|
|
|
|
|
|
hdev->asic_funcs->write_pte(hdev,
|
|
|
|
is_huge ? hop3_pte_addr : hop4_pte_addr,
|
|
|
|
curr_pte);
|
|
|
|
|
|
|
|
if (hop1_new) {
|
|
|
|
curr_pte = (hop1_addr & PTE_PHYS_ADDR_MASK) |
|
|
|
|
PAGE_PRESENT_MASK;
|
|
|
|
ctx->hdev->asic_funcs->write_pte(ctx->hdev, hop0_pte_addr,
|
|
|
|
curr_pte);
|
|
|
|
}
|
|
|
|
if (hop2_new) {
|
|
|
|
curr_pte = (hop2_addr & PTE_PHYS_ADDR_MASK) |
|
|
|
|
PAGE_PRESENT_MASK;
|
|
|
|
ctx->hdev->asic_funcs->write_pte(ctx->hdev, hop1_pte_addr,
|
|
|
|
curr_pte);
|
|
|
|
get_pte(ctx, hop1_addr);
|
|
|
|
}
|
|
|
|
if (hop3_new) {
|
|
|
|
curr_pte = (hop3_addr & PTE_PHYS_ADDR_MASK) |
|
|
|
|
PAGE_PRESENT_MASK;
|
|
|
|
ctx->hdev->asic_funcs->write_pte(ctx->hdev, hop2_pte_addr,
|
|
|
|
curr_pte);
|
|
|
|
get_pte(ctx, hop2_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!is_huge) {
|
|
|
|
if (hop4_new) {
|
|
|
|
curr_pte = (hop4_addr & PTE_PHYS_ADDR_MASK) |
|
|
|
|
PAGE_PRESENT_MASK;
|
|
|
|
ctx->hdev->asic_funcs->write_pte(ctx->hdev,
|
|
|
|
hop3_pte_addr, curr_pte);
|
|
|
|
get_pte(ctx, hop3_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
get_pte(ctx, hop4_addr);
|
|
|
|
} else {
|
|
|
|
get_pte(ctx, hop3_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* flush all writes from all cores to reach PCI */
|
|
|
|
mb();
|
|
|
|
|
|
|
|
hdev->asic_funcs->read_pte(hdev,
|
|
|
|
is_huge ? hop3_pte_addr : hop4_pte_addr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
|
|
|
if (hop4_new)
|
|
|
|
free_hop(ctx, hop4_addr);
|
|
|
|
if (hop3_new)
|
|
|
|
free_hop(ctx, hop3_addr);
|
|
|
|
if (hop2_new)
|
|
|
|
free_hop(ctx, hop2_addr);
|
|
|
|
if (hop1_new)
|
|
|
|
free_hop(ctx, hop1_addr);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_mmu_map - maps a virtual addr to physical addr
|
|
|
|
*
|
|
|
|
* @ctx: pointer to the context structure
|
|
|
|
* @virt_addr: virt addr to map from
|
|
|
|
* @phys_addr: phys addr to map to
|
|
|
|
* @page_size: physical page size
|
|
|
|
*
|
|
|
|
* This function does the following:
|
|
|
|
* - Check that the virt addr is not mapped
|
|
|
|
* - Allocate pgts as necessary in order to map the virt addr to the phys
|
|
|
|
* - Returns 0 on success, -EINVAL if addr is already mapped, or -ENOMEM.
|
|
|
|
*
|
|
|
|
* Because this function changes the page tables in the device and because it
|
|
|
|
* changes the MMU hash, it must be protected by a lock.
|
|
|
|
* However, because it maps only a single page, the lock should be implemented
|
|
|
|
* in a higher level in order to protect the entire mapping of the memory area
|
|
|
|
*/
|
|
|
|
int hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size)
|
|
|
|
{
|
|
|
|
struct hl_device *hdev = ctx->hdev;
|
2019-03-14 08:54:45 -06:00
|
|
|
u64 real_virt_addr, real_phys_addr;
|
2019-02-15 15:39:22 -07:00
|
|
|
u32 real_page_size, npages;
|
|
|
|
int i, rc, mapped_cnt = 0;
|
|
|
|
|
|
|
|
if (!hdev->mmu_enable)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The H/W handles mapping of 4KB/2MB page. Hence if the host page size
|
|
|
|
* is bigger, we break it to sub-pages and map them separately.
|
|
|
|
*/
|
|
|
|
if ((page_size % PAGE_SIZE_2MB) == 0) {
|
|
|
|
real_page_size = PAGE_SIZE_2MB;
|
|
|
|
} else if ((page_size % PAGE_SIZE_4KB) == 0) {
|
|
|
|
real_page_size = PAGE_SIZE_4KB;
|
|
|
|
} else {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"page size of %u is not 4KB nor 2MB aligned, can't map\n",
|
|
|
|
page_size);
|
|
|
|
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
npages = page_size / real_page_size;
|
|
|
|
real_virt_addr = virt_addr;
|
2019-03-14 08:54:45 -06:00
|
|
|
real_phys_addr = phys_addr;
|
2019-02-15 15:39:22 -07:00
|
|
|
|
|
|
|
for (i = 0 ; i < npages ; i++) {
|
2019-03-14 08:54:45 -06:00
|
|
|
rc = _hl_mmu_map(ctx, real_virt_addr, real_phys_addr,
|
2019-02-15 15:39:22 -07:00
|
|
|
real_page_size);
|
|
|
|
if (rc)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
real_virt_addr += real_page_size;
|
2019-03-14 08:54:45 -06:00
|
|
|
real_phys_addr += real_page_size;
|
2019-02-15 15:39:22 -07:00
|
|
|
mapped_cnt++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
|
|
|
real_virt_addr = virt_addr;
|
|
|
|
for (i = 0 ; i < mapped_cnt ; i++) {
|
|
|
|
if (_hl_mmu_unmap(ctx, real_virt_addr))
|
|
|
|
dev_warn_ratelimited(hdev->dev,
|
|
|
|
"failed to unmap va: 0x%llx\n", real_virt_addr);
|
|
|
|
|
|
|
|
real_virt_addr += real_page_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_mmu_swap_out - marks all mapping of the given ctx as swapped out
|
|
|
|
*
|
|
|
|
* @ctx: pointer to the context structure
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
void hl_mmu_swap_out(struct hl_ctx *ctx)
|
|
|
|
{
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_mmu_swap_in - marks all mapping of the given ctx as swapped in
|
|
|
|
*
|
|
|
|
* @ctx: pointer to the context structure
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
void hl_mmu_swap_in(struct hl_ctx *ctx)
|
|
|
|
{
|
|
|
|
|
|
|
|
}
|