2005-04-16 16:20:36 -06:00
|
|
|
/*
|
2013-11-01 17:47:05 -06:00
|
|
|
* Atomic operations that C can't guarantee us. Useful for
|
2005-04-16 16:20:36 -06:00
|
|
|
* resource counting etc..
|
|
|
|
|
*
|
|
|
|
|
* But use these as seldom as possible since they are much more slower
|
|
|
|
|
* than regular operations.
|
|
|
|
|
*
|
|
|
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
|
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
|
|
|
* for more details.
|
|
|
|
|
*
|
2006-11-29 18:14:50 -07:00
|
|
|
* Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
|
|
|
|
#ifndef _ASM_ATOMIC_H
|
|
|
|
|
#define _ASM_ATOMIC_H
|
|
|
|
|
|
2006-07-07 07:07:18 -06:00
|
|
|
#include <linux/irqflags.h>
|
2009-01-06 15:40:39 -07:00
|
|
|
#include <linux/types.h>
|
2006-10-30 20:45:07 -07:00
|
|
|
#include <asm/barrier.h>
|
2014-11-15 15:08:48 -07:00
|
|
|
#include <asm/compiler.h>
|
2005-04-16 16:20:36 -06:00
|
|
|
#include <asm/cpu-features.h>
|
2012-03-28 11:30:02 -06:00
|
|
|
#include <asm/cmpxchg.h>
|
2005-04-16 16:20:36 -06:00
|
|
|
#include <asm/war.h>
|
|
|
|
|
|
2017-11-18 21:00:51 -07:00
|
|
|
/*
|
|
|
|
|
* Using a branch-likely instruction to check the result of an sc instruction
|
|
|
|
|
* works around a bug present in R10000 CPUs prior to revision 3.0 that could
|
|
|
|
|
* cause ll-sc sequences to execute non-atomically.
|
|
|
|
|
*/
|
|
|
|
|
#if R10000_LLSC_WAR
|
|
|
|
|
# define __scbeqz "beqzl"
|
|
|
|
|
#else
|
|
|
|
|
# define __scbeqz "beqz"
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-01-22 04:59:30 -07:00
|
|
|
#define ATOMIC_INIT(i) { (i) }
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* atomic_read - read atomic variable
|
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
|
*
|
|
|
|
|
* Atomically reads the value of @v.
|
|
|
|
|
*/
|
2015-09-18 03:13:10 -06:00
|
|
|
#define atomic_read(v) READ_ONCE((v)->counter)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* atomic_set - set atomic variable
|
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
|
* @i: required value
|
|
|
|
|
*
|
|
|
|
|
* Atomically sets the value of @v to @i.
|
|
|
|
|
*/
|
2015-09-18 03:13:10 -06:00
|
|
|
#define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2014-11-15 15:09:54 -07:00
|
|
|
#define ATOMIC_OP(op, c_op, asm_op) \
|
|
|
|
|
static __inline__ void atomic_##op(int i, atomic_t * v) \
|
|
|
|
|
{ \
|
2017-11-18 21:00:51 -07:00
|
|
|
if (kernel_uses_llsc) { \
|
2014-11-15 15:09:54 -07:00
|
|
|
int temp; \
|
|
|
|
|
\
|
MIPS: Loongson: Introduce and use loongson_llsc_mb()
On the Loongson-2G/2H/3A/3B there is a hardware flaw that ll/sc and
lld/scd is very weak ordering. We should add sync instructions "before
each ll/lld" and "at the branch-target between ll/sc" to workaround.
Otherwise, this flaw will cause deadlock occasionally (e.g. when doing
heavy load test with LTP).
Below is the explaination of CPU designer:
"For Loongson 3 family, when a memory access instruction (load, store,
or prefetch)'s executing occurs between the execution of LL and SC, the
success or failure of SC is not predictable. Although programmer would
not insert memory access instructions between LL and SC, the memory
instructions before LL in program-order, may dynamically executed
between the execution of LL/SC, so a memory fence (SYNC) is needed
before LL/LLD to avoid this situation.
Since Loongson-3A R2 (3A2000), we have improved our hardware design to
handle this case. But we later deduce a rarely circumstance that some
speculatively executed memory instructions due to branch misprediction
between LL/SC still fall into the above case, so a memory fence (SYNC)
at branch-target (if its target is not between LL/SC) is needed for
Loongson 3A1000, 3B1500, 3A2000 and 3A3000.
Our processor is continually evolving and we aim to to remove all these
workaround-SYNCs around LL/SC for new-come processor."
Here is an example:
Both cpu1 and cpu2 simutaneously run atomic_add by 1 on same atomic var,
this bug cause both 'sc' run by two cpus (in atomic_add) succeed at same
time('sc' return 1), and the variable is only *added by 1*, sometimes,
which is wrong and unacceptable(it should be added by 2).
Why disable fix-loongson3-llsc in compiler?
Because compiler fix will cause problems in kernel's __ex_table section.
This patch fix all the cases in kernel, but:
+. the fix at the end of futex_atomic_cmpxchg_inatomic is for branch-target
of 'bne', there other cases which smp_mb__before_llsc() and smp_llsc_mb() fix
the ll and branch-target coincidently such as atomic_sub_if_positive/
cmpxchg/xchg, just like this one.
+. Loongson 3 does support CONFIG_EDAC_ATOMIC_SCRUB, so no need to touch
edac.h
+. local_ops and cmpxchg_local should not be affected by this bug since
only the owner can write.
+. mips_atomic_set for syscall.c is deprecated and rarely used, just let
it go
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huang Pei <huangpei@loongson.cn>
[paul.burton@mips.com:
- Simplify the addition of -mno-fix-loongson3-llsc to cflags, and add
a comment describing why it's there.
- Make loongson_llsc_mb() a no-op when
CONFIG_CPU_LOONGSON3_WORKAROUNDS=n, rather than a compiler memory
barrier.
- Add a comment describing the bug & how loongson_llsc_mb() helps
in asm/barrier.h.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: ambrosehua@gmail.com
Cc: Steven J . Hill <Steven.Hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Li Xuefeng <lixuefeng@loongson.cn>
Cc: Xu Chenghua <xuchenghua@loongson.cn>
2019-01-15 01:04:54 -07:00
|
|
|
loongson_llsc_mb(); \
|
2014-11-15 15:09:54 -07:00
|
|
|
__asm__ __volatile__( \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n" \
|
2014-11-15 15:09:54 -07:00
|
|
|
"1: ll %0, %1 # atomic_" #op " \n" \
|
|
|
|
|
" " #asm_op " %0, %2 \n" \
|
|
|
|
|
" sc %0, %1 \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
"\t" __scbeqz " %0, 1b \n" \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n" \
|
2015-01-26 05:44:11 -07:00
|
|
|
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
|
2014-11-15 15:09:54 -07:00
|
|
|
: "Ir" (i)); \
|
|
|
|
|
} else { \
|
|
|
|
|
unsigned long flags; \
|
|
|
|
|
\
|
|
|
|
|
raw_local_irq_save(flags); \
|
|
|
|
|
v->counter c_op i; \
|
|
|
|
|
raw_local_irq_restore(flags); \
|
|
|
|
|
} \
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
2014-11-15 15:09:54 -07:00
|
|
|
#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
|
2016-04-17 17:15:25 -06:00
|
|
|
static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
|
2014-11-15 15:09:54 -07:00
|
|
|
{ \
|
|
|
|
|
int result; \
|
|
|
|
|
\
|
2017-11-18 21:00:51 -07:00
|
|
|
if (kernel_uses_llsc) { \
|
2014-11-15 15:09:54 -07:00
|
|
|
int temp; \
|
|
|
|
|
\
|
MIPS: Loongson: Introduce and use loongson_llsc_mb()
On the Loongson-2G/2H/3A/3B there is a hardware flaw that ll/sc and
lld/scd is very weak ordering. We should add sync instructions "before
each ll/lld" and "at the branch-target between ll/sc" to workaround.
Otherwise, this flaw will cause deadlock occasionally (e.g. when doing
heavy load test with LTP).
Below is the explaination of CPU designer:
"For Loongson 3 family, when a memory access instruction (load, store,
or prefetch)'s executing occurs between the execution of LL and SC, the
success or failure of SC is not predictable. Although programmer would
not insert memory access instructions between LL and SC, the memory
instructions before LL in program-order, may dynamically executed
between the execution of LL/SC, so a memory fence (SYNC) is needed
before LL/LLD to avoid this situation.
Since Loongson-3A R2 (3A2000), we have improved our hardware design to
handle this case. But we later deduce a rarely circumstance that some
speculatively executed memory instructions due to branch misprediction
between LL/SC still fall into the above case, so a memory fence (SYNC)
at branch-target (if its target is not between LL/SC) is needed for
Loongson 3A1000, 3B1500, 3A2000 and 3A3000.
Our processor is continually evolving and we aim to to remove all these
workaround-SYNCs around LL/SC for new-come processor."
Here is an example:
Both cpu1 and cpu2 simutaneously run atomic_add by 1 on same atomic var,
this bug cause both 'sc' run by two cpus (in atomic_add) succeed at same
time('sc' return 1), and the variable is only *added by 1*, sometimes,
which is wrong and unacceptable(it should be added by 2).
Why disable fix-loongson3-llsc in compiler?
Because compiler fix will cause problems in kernel's __ex_table section.
This patch fix all the cases in kernel, but:
+. the fix at the end of futex_atomic_cmpxchg_inatomic is for branch-target
of 'bne', there other cases which smp_mb__before_llsc() and smp_llsc_mb() fix
the ll and branch-target coincidently such as atomic_sub_if_positive/
cmpxchg/xchg, just like this one.
+. Loongson 3 does support CONFIG_EDAC_ATOMIC_SCRUB, so no need to touch
edac.h
+. local_ops and cmpxchg_local should not be affected by this bug since
only the owner can write.
+. mips_atomic_set for syscall.c is deprecated and rarely used, just let
it go
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huang Pei <huangpei@loongson.cn>
[paul.burton@mips.com:
- Simplify the addition of -mno-fix-loongson3-llsc to cflags, and add
a comment describing why it's there.
- Make loongson_llsc_mb() a no-op when
CONFIG_CPU_LOONGSON3_WORKAROUNDS=n, rather than a compiler memory
barrier.
- Add a comment describing the bug & how loongson_llsc_mb() helps
in asm/barrier.h.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: ambrosehua@gmail.com
Cc: Steven J . Hill <Steven.Hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Li Xuefeng <lixuefeng@loongson.cn>
Cc: Xu Chenghua <xuchenghua@loongson.cn>
2019-01-15 01:04:54 -07:00
|
|
|
loongson_llsc_mb(); \
|
2014-11-15 15:09:54 -07:00
|
|
|
__asm__ __volatile__( \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n" \
|
2014-11-15 15:09:54 -07:00
|
|
|
"1: ll %1, %2 # atomic_" #op "_return \n" \
|
|
|
|
|
" " #asm_op " %0, %1, %3 \n" \
|
|
|
|
|
" sc %0, %2 \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
"\t" __scbeqz " %0, 1b \n" \
|
2014-11-15 15:09:54 -07:00
|
|
|
" " #asm_op " %0, %1, %3 \n" \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n" \
|
2014-11-15 15:09:54 -07:00
|
|
|
: "=&r" (result), "=&r" (temp), \
|
2015-01-26 05:44:11 -07:00
|
|
|
"+" GCC_OFF_SMALL_ASM() (v->counter) \
|
2014-11-15 15:09:54 -07:00
|
|
|
: "Ir" (i)); \
|
|
|
|
|
} else { \
|
|
|
|
|
unsigned long flags; \
|
|
|
|
|
\
|
|
|
|
|
raw_local_irq_save(flags); \
|
|
|
|
|
result = v->counter; \
|
|
|
|
|
result c_op i; \
|
|
|
|
|
v->counter = result; \
|
|
|
|
|
raw_local_irq_restore(flags); \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
return result; \
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-17 17:16:06 -06:00
|
|
|
#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
|
2016-04-17 17:15:25 -06:00
|
|
|
static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
|
2016-04-17 17:16:06 -06:00
|
|
|
{ \
|
|
|
|
|
int result; \
|
|
|
|
|
\
|
2017-11-18 21:00:51 -07:00
|
|
|
if (kernel_uses_llsc) { \
|
2016-04-17 17:16:06 -06:00
|
|
|
int temp; \
|
|
|
|
|
\
|
MIPS: Loongson: Introduce and use loongson_llsc_mb()
On the Loongson-2G/2H/3A/3B there is a hardware flaw that ll/sc and
lld/scd is very weak ordering. We should add sync instructions "before
each ll/lld" and "at the branch-target between ll/sc" to workaround.
Otherwise, this flaw will cause deadlock occasionally (e.g. when doing
heavy load test with LTP).
Below is the explaination of CPU designer:
"For Loongson 3 family, when a memory access instruction (load, store,
or prefetch)'s executing occurs between the execution of LL and SC, the
success or failure of SC is not predictable. Although programmer would
not insert memory access instructions between LL and SC, the memory
instructions before LL in program-order, may dynamically executed
between the execution of LL/SC, so a memory fence (SYNC) is needed
before LL/LLD to avoid this situation.
Since Loongson-3A R2 (3A2000), we have improved our hardware design to
handle this case. But we later deduce a rarely circumstance that some
speculatively executed memory instructions due to branch misprediction
between LL/SC still fall into the above case, so a memory fence (SYNC)
at branch-target (if its target is not between LL/SC) is needed for
Loongson 3A1000, 3B1500, 3A2000 and 3A3000.
Our processor is continually evolving and we aim to to remove all these
workaround-SYNCs around LL/SC for new-come processor."
Here is an example:
Both cpu1 and cpu2 simutaneously run atomic_add by 1 on same atomic var,
this bug cause both 'sc' run by two cpus (in atomic_add) succeed at same
time('sc' return 1), and the variable is only *added by 1*, sometimes,
which is wrong and unacceptable(it should be added by 2).
Why disable fix-loongson3-llsc in compiler?
Because compiler fix will cause problems in kernel's __ex_table section.
This patch fix all the cases in kernel, but:
+. the fix at the end of futex_atomic_cmpxchg_inatomic is for branch-target
of 'bne', there other cases which smp_mb__before_llsc() and smp_llsc_mb() fix
the ll and branch-target coincidently such as atomic_sub_if_positive/
cmpxchg/xchg, just like this one.
+. Loongson 3 does support CONFIG_EDAC_ATOMIC_SCRUB, so no need to touch
edac.h
+. local_ops and cmpxchg_local should not be affected by this bug since
only the owner can write.
+. mips_atomic_set for syscall.c is deprecated and rarely used, just let
it go
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huang Pei <huangpei@loongson.cn>
[paul.burton@mips.com:
- Simplify the addition of -mno-fix-loongson3-llsc to cflags, and add
a comment describing why it's there.
- Make loongson_llsc_mb() a no-op when
CONFIG_CPU_LOONGSON3_WORKAROUNDS=n, rather than a compiler memory
barrier.
- Add a comment describing the bug & how loongson_llsc_mb() helps
in asm/barrier.h.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: ambrosehua@gmail.com
Cc: Steven J . Hill <Steven.Hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Li Xuefeng <lixuefeng@loongson.cn>
Cc: Xu Chenghua <xuchenghua@loongson.cn>
2019-01-15 01:04:54 -07:00
|
|
|
loongson_llsc_mb(); \
|
2016-04-17 17:16:06 -06:00
|
|
|
__asm__ __volatile__( \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n" \
|
2016-04-17 17:16:06 -06:00
|
|
|
"1: ll %1, %2 # atomic_fetch_" #op " \n" \
|
|
|
|
|
" " #asm_op " %0, %1, %3 \n" \
|
|
|
|
|
" sc %0, %2 \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
"\t" __scbeqz " %0, 1b \n" \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n" \
|
2018-08-17 16:36:24 -06:00
|
|
|
" move %0, %1 \n" \
|
2016-04-17 17:16:06 -06:00
|
|
|
: "=&r" (result), "=&r" (temp), \
|
|
|
|
|
"+" GCC_OFF_SMALL_ASM() (v->counter) \
|
|
|
|
|
: "Ir" (i)); \
|
|
|
|
|
} else { \
|
|
|
|
|
unsigned long flags; \
|
|
|
|
|
\
|
|
|
|
|
raw_local_irq_save(flags); \
|
|
|
|
|
result = v->counter; \
|
|
|
|
|
v->counter c_op i; \
|
|
|
|
|
raw_local_irq_restore(flags); \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
return result; \
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-15 15:09:54 -07:00
|
|
|
#define ATOMIC_OPS(op, c_op, asm_op) \
|
|
|
|
|
ATOMIC_OP(op, c_op, asm_op) \
|
2016-04-17 17:16:06 -06:00
|
|
|
ATOMIC_OP_RETURN(op, c_op, asm_op) \
|
|
|
|
|
ATOMIC_FETCH_OP(op, c_op, asm_op)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2014-03-26 10:56:43 -06:00
|
|
|
ATOMIC_OPS(add, +=, addu)
|
|
|
|
|
ATOMIC_OPS(sub, -=, subu)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2016-04-17 17:15:25 -06:00
|
|
|
#define atomic_add_return_relaxed atomic_add_return_relaxed
|
|
|
|
|
#define atomic_sub_return_relaxed atomic_sub_return_relaxed
|
|
|
|
|
#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
|
|
|
|
|
#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
|
|
|
|
|
|
2016-04-17 17:16:06 -06:00
|
|
|
#undef ATOMIC_OPS
|
|
|
|
|
#define ATOMIC_OPS(op, c_op, asm_op) \
|
|
|
|
|
ATOMIC_OP(op, c_op, asm_op) \
|
|
|
|
|
ATOMIC_FETCH_OP(op, c_op, asm_op)
|
|
|
|
|
|
|
|
|
|
ATOMIC_OPS(and, &=, and)
|
|
|
|
|
ATOMIC_OPS(or, |=, or)
|
|
|
|
|
ATOMIC_OPS(xor, ^=, xor)
|
2014-04-23 11:51:36 -06:00
|
|
|
|
2016-04-17 17:15:25 -06:00
|
|
|
#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
|
|
|
|
|
#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
|
|
|
|
|
#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
|
|
|
|
|
|
2014-03-26 10:56:43 -06:00
|
|
|
#undef ATOMIC_OPS
|
2016-04-17 17:16:06 -06:00
|
|
|
#undef ATOMIC_FETCH_OP
|
2014-03-26 10:56:43 -06:00
|
|
|
#undef ATOMIC_OP_RETURN
|
|
|
|
|
#undef ATOMIC_OP
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
/*
|
2005-11-12 16:38:18 -07:00
|
|
|
* atomic_sub_if_positive - conditionally subtract integer from atomic variable
|
|
|
|
|
* @i: integer value to subtract
|
2005-04-16 16:20:36 -06:00
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
|
*
|
2005-11-12 16:38:18 -07:00
|
|
|
* Atomically test @v and subtract @i if @v is greater or equal than @i.
|
|
|
|
|
* The function returns the old value of @v minus @i.
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
|
|
|
|
static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
|
|
|
|
|
{
|
2009-01-11 17:52:18 -07:00
|
|
|
int result;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2010-01-08 18:17:43 -07:00
|
|
|
smp_mb__before_llsc();
|
2006-10-30 20:45:07 -07:00
|
|
|
|
2017-11-18 21:00:51 -07:00
|
|
|
if (kernel_uses_llsc) {
|
2009-01-11 17:52:18 -07:00
|
|
|
int temp;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
__asm__ __volatile__(
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n"
|
2015-01-06 04:09:24 -07:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n"
|
2005-04-16 16:20:36 -06:00
|
|
|
"1: ll %1, %2 # atomic_sub_if_positive\n"
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n"
|
2005-04-16 16:20:36 -06:00
|
|
|
" subu %0, %1, %3 \n"
|
2017-11-18 20:29:56 -07:00
|
|
|
" move %1, %0 \n"
|
2005-04-16 16:20:36 -06:00
|
|
|
" bltz %0, 1f \n"
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n"
|
2018-08-17 16:36:24 -06:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n"
|
2017-11-18 20:29:56 -07:00
|
|
|
" sc %1, %2 \n"
|
2017-11-18 21:00:51 -07:00
|
|
|
"\t" __scbeqz " %1, 1b \n"
|
2008-07-03 16:28:35 -06:00
|
|
|
"1: \n"
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n"
|
2014-11-15 15:08:48 -07:00
|
|
|
: "=&r" (result), "=&r" (temp),
|
2015-01-26 05:44:11 -07:00
|
|
|
"+" GCC_OFF_SMALL_ASM() (v->counter)
|
2012-06-24 19:01:34 -06:00
|
|
|
: "Ir" (i));
|
2005-04-16 16:20:36 -06:00
|
|
|
} else {
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
2007-03-16 10:10:36 -06:00
|
|
|
raw_local_irq_save(flags);
|
2005-04-16 16:20:36 -06:00
|
|
|
result = v->counter;
|
|
|
|
|
result -= i;
|
|
|
|
|
if (result >= 0)
|
|
|
|
|
v->counter = result;
|
2007-03-16 10:10:36 -06:00
|
|
|
raw_local_irq_restore(flags);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
2007-07-14 06:24:05 -06:00
|
|
|
smp_llsc_mb();
|
2006-10-30 20:45:07 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
2007-05-08 01:34:24 -06:00
|
|
|
#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
|
|
|
|
|
#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
|
2005-11-13 17:07:24 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/*
|
|
|
|
|
* atomic_dec_if_positive - decrement by 1 if old value positive
|
|
|
|
|
* @v: pointer of type atomic_t
|
|
|
|
|
*/
|
|
|
|
|
#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
|
|
|
|
|
|
2005-09-03 16:56:16 -06:00
|
|
|
#ifdef CONFIG_64BIT
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
#define ATOMIC64_INIT(i) { (i) }
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* atomic64_read - read atomic variable
|
|
|
|
|
* @v: pointer of type atomic64_t
|
|
|
|
|
*
|
|
|
|
|
*/
|
2015-09-18 03:13:10 -06:00
|
|
|
#define atomic64_read(v) READ_ONCE((v)->counter)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* atomic64_set - set atomic variable
|
|
|
|
|
* @v: pointer of type atomic64_t
|
|
|
|
|
* @i: required value
|
|
|
|
|
*/
|
2015-09-18 03:13:10 -06:00
|
|
|
#define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2014-11-15 15:09:54 -07:00
|
|
|
#define ATOMIC64_OP(op, c_op, asm_op) \
|
|
|
|
|
static __inline__ void atomic64_##op(long i, atomic64_t * v) \
|
|
|
|
|
{ \
|
2017-11-18 21:00:51 -07:00
|
|
|
if (kernel_uses_llsc) { \
|
2014-11-15 15:09:54 -07:00
|
|
|
long temp; \
|
|
|
|
|
\
|
MIPS: Loongson: Introduce and use loongson_llsc_mb()
On the Loongson-2G/2H/3A/3B there is a hardware flaw that ll/sc and
lld/scd is very weak ordering. We should add sync instructions "before
each ll/lld" and "at the branch-target between ll/sc" to workaround.
Otherwise, this flaw will cause deadlock occasionally (e.g. when doing
heavy load test with LTP).
Below is the explaination of CPU designer:
"For Loongson 3 family, when a memory access instruction (load, store,
or prefetch)'s executing occurs between the execution of LL and SC, the
success or failure of SC is not predictable. Although programmer would
not insert memory access instructions between LL and SC, the memory
instructions before LL in program-order, may dynamically executed
between the execution of LL/SC, so a memory fence (SYNC) is needed
before LL/LLD to avoid this situation.
Since Loongson-3A R2 (3A2000), we have improved our hardware design to
handle this case. But we later deduce a rarely circumstance that some
speculatively executed memory instructions due to branch misprediction
between LL/SC still fall into the above case, so a memory fence (SYNC)
at branch-target (if its target is not between LL/SC) is needed for
Loongson 3A1000, 3B1500, 3A2000 and 3A3000.
Our processor is continually evolving and we aim to to remove all these
workaround-SYNCs around LL/SC for new-come processor."
Here is an example:
Both cpu1 and cpu2 simutaneously run atomic_add by 1 on same atomic var,
this bug cause both 'sc' run by two cpus (in atomic_add) succeed at same
time('sc' return 1), and the variable is only *added by 1*, sometimes,
which is wrong and unacceptable(it should be added by 2).
Why disable fix-loongson3-llsc in compiler?
Because compiler fix will cause problems in kernel's __ex_table section.
This patch fix all the cases in kernel, but:
+. the fix at the end of futex_atomic_cmpxchg_inatomic is for branch-target
of 'bne', there other cases which smp_mb__before_llsc() and smp_llsc_mb() fix
the ll and branch-target coincidently such as atomic_sub_if_positive/
cmpxchg/xchg, just like this one.
+. Loongson 3 does support CONFIG_EDAC_ATOMIC_SCRUB, so no need to touch
edac.h
+. local_ops and cmpxchg_local should not be affected by this bug since
only the owner can write.
+. mips_atomic_set for syscall.c is deprecated and rarely used, just let
it go
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huang Pei <huangpei@loongson.cn>
[paul.burton@mips.com:
- Simplify the addition of -mno-fix-loongson3-llsc to cflags, and add
a comment describing why it's there.
- Make loongson_llsc_mb() a no-op when
CONFIG_CPU_LOONGSON3_WORKAROUNDS=n, rather than a compiler memory
barrier.
- Add a comment describing the bug & how loongson_llsc_mb() helps
in asm/barrier.h.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: ambrosehua@gmail.com
Cc: Steven J . Hill <Steven.Hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Li Xuefeng <lixuefeng@loongson.cn>
Cc: Xu Chenghua <xuchenghua@loongson.cn>
2019-01-15 01:04:54 -07:00
|
|
|
loongson_llsc_mb(); \
|
2014-11-15 15:09:54 -07:00
|
|
|
__asm__ __volatile__( \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n" \
|
2014-11-15 15:09:54 -07:00
|
|
|
"1: lld %0, %1 # atomic64_" #op " \n" \
|
|
|
|
|
" " #asm_op " %0, %2 \n" \
|
|
|
|
|
" scd %0, %1 \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
"\t" __scbeqz " %0, 1b \n" \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n" \
|
2015-01-26 05:44:11 -07:00
|
|
|
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
|
2014-11-15 15:09:54 -07:00
|
|
|
: "Ir" (i)); \
|
|
|
|
|
} else { \
|
|
|
|
|
unsigned long flags; \
|
|
|
|
|
\
|
|
|
|
|
raw_local_irq_save(flags); \
|
|
|
|
|
v->counter c_op i; \
|
|
|
|
|
raw_local_irq_restore(flags); \
|
|
|
|
|
} \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define ATOMIC64_OP_RETURN(op, c_op, asm_op) \
|
2016-04-17 17:15:25 -06:00
|
|
|
static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \
|
2014-11-15 15:09:54 -07:00
|
|
|
{ \
|
|
|
|
|
long result; \
|
|
|
|
|
\
|
2017-11-18 21:00:51 -07:00
|
|
|
if (kernel_uses_llsc) { \
|
2014-11-15 15:09:54 -07:00
|
|
|
long temp; \
|
|
|
|
|
\
|
MIPS: Loongson: Introduce and use loongson_llsc_mb()
On the Loongson-2G/2H/3A/3B there is a hardware flaw that ll/sc and
lld/scd is very weak ordering. We should add sync instructions "before
each ll/lld" and "at the branch-target between ll/sc" to workaround.
Otherwise, this flaw will cause deadlock occasionally (e.g. when doing
heavy load test with LTP).
Below is the explaination of CPU designer:
"For Loongson 3 family, when a memory access instruction (load, store,
or prefetch)'s executing occurs between the execution of LL and SC, the
success or failure of SC is not predictable. Although programmer would
not insert memory access instructions between LL and SC, the memory
instructions before LL in program-order, may dynamically executed
between the execution of LL/SC, so a memory fence (SYNC) is needed
before LL/LLD to avoid this situation.
Since Loongson-3A R2 (3A2000), we have improved our hardware design to
handle this case. But we later deduce a rarely circumstance that some
speculatively executed memory instructions due to branch misprediction
between LL/SC still fall into the above case, so a memory fence (SYNC)
at branch-target (if its target is not between LL/SC) is needed for
Loongson 3A1000, 3B1500, 3A2000 and 3A3000.
Our processor is continually evolving and we aim to to remove all these
workaround-SYNCs around LL/SC for new-come processor."
Here is an example:
Both cpu1 and cpu2 simutaneously run atomic_add by 1 on same atomic var,
this bug cause both 'sc' run by two cpus (in atomic_add) succeed at same
time('sc' return 1), and the variable is only *added by 1*, sometimes,
which is wrong and unacceptable(it should be added by 2).
Why disable fix-loongson3-llsc in compiler?
Because compiler fix will cause problems in kernel's __ex_table section.
This patch fix all the cases in kernel, but:
+. the fix at the end of futex_atomic_cmpxchg_inatomic is for branch-target
of 'bne', there other cases which smp_mb__before_llsc() and smp_llsc_mb() fix
the ll and branch-target coincidently such as atomic_sub_if_positive/
cmpxchg/xchg, just like this one.
+. Loongson 3 does support CONFIG_EDAC_ATOMIC_SCRUB, so no need to touch
edac.h
+. local_ops and cmpxchg_local should not be affected by this bug since
only the owner can write.
+. mips_atomic_set for syscall.c is deprecated and rarely used, just let
it go
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huang Pei <huangpei@loongson.cn>
[paul.burton@mips.com:
- Simplify the addition of -mno-fix-loongson3-llsc to cflags, and add
a comment describing why it's there.
- Make loongson_llsc_mb() a no-op when
CONFIG_CPU_LOONGSON3_WORKAROUNDS=n, rather than a compiler memory
barrier.
- Add a comment describing the bug & how loongson_llsc_mb() helps
in asm/barrier.h.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: ambrosehua@gmail.com
Cc: Steven J . Hill <Steven.Hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Li Xuefeng <lixuefeng@loongson.cn>
Cc: Xu Chenghua <xuchenghua@loongson.cn>
2019-01-15 01:04:54 -07:00
|
|
|
loongson_llsc_mb(); \
|
2014-11-15 15:09:54 -07:00
|
|
|
__asm__ __volatile__( \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n" \
|
2014-11-15 15:09:54 -07:00
|
|
|
"1: lld %1, %2 # atomic64_" #op "_return\n" \
|
|
|
|
|
" " #asm_op " %0, %1, %3 \n" \
|
|
|
|
|
" scd %0, %2 \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
"\t" __scbeqz " %0, 1b \n" \
|
2014-11-15 15:09:54 -07:00
|
|
|
" " #asm_op " %0, %1, %3 \n" \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n" \
|
2014-11-15 15:09:54 -07:00
|
|
|
: "=&r" (result), "=&r" (temp), \
|
2015-01-26 05:44:11 -07:00
|
|
|
"+" GCC_OFF_SMALL_ASM() (v->counter) \
|
2014-11-15 15:09:54 -07:00
|
|
|
: "Ir" (i)); \
|
|
|
|
|
} else { \
|
|
|
|
|
unsigned long flags; \
|
|
|
|
|
\
|
|
|
|
|
raw_local_irq_save(flags); \
|
|
|
|
|
result = v->counter; \
|
|
|
|
|
result c_op i; \
|
|
|
|
|
v->counter = result; \
|
|
|
|
|
raw_local_irq_restore(flags); \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
return result; \
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
2016-04-17 17:16:06 -06:00
|
|
|
#define ATOMIC64_FETCH_OP(op, c_op, asm_op) \
|
2016-04-17 17:15:25 -06:00
|
|
|
static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \
|
2016-04-17 17:16:06 -06:00
|
|
|
{ \
|
|
|
|
|
long result; \
|
|
|
|
|
\
|
2018-12-24 17:51:01 -07:00
|
|
|
if (kernel_uses_llsc) { \
|
2016-04-17 17:16:06 -06:00
|
|
|
long temp; \
|
|
|
|
|
\
|
MIPS: Loongson: Introduce and use loongson_llsc_mb()
On the Loongson-2G/2H/3A/3B there is a hardware flaw that ll/sc and
lld/scd is very weak ordering. We should add sync instructions "before
each ll/lld" and "at the branch-target between ll/sc" to workaround.
Otherwise, this flaw will cause deadlock occasionally (e.g. when doing
heavy load test with LTP).
Below is the explaination of CPU designer:
"For Loongson 3 family, when a memory access instruction (load, store,
or prefetch)'s executing occurs between the execution of LL and SC, the
success or failure of SC is not predictable. Although programmer would
not insert memory access instructions between LL and SC, the memory
instructions before LL in program-order, may dynamically executed
between the execution of LL/SC, so a memory fence (SYNC) is needed
before LL/LLD to avoid this situation.
Since Loongson-3A R2 (3A2000), we have improved our hardware design to
handle this case. But we later deduce a rarely circumstance that some
speculatively executed memory instructions due to branch misprediction
between LL/SC still fall into the above case, so a memory fence (SYNC)
at branch-target (if its target is not between LL/SC) is needed for
Loongson 3A1000, 3B1500, 3A2000 and 3A3000.
Our processor is continually evolving and we aim to to remove all these
workaround-SYNCs around LL/SC for new-come processor."
Here is an example:
Both cpu1 and cpu2 simutaneously run atomic_add by 1 on same atomic var,
this bug cause both 'sc' run by two cpus (in atomic_add) succeed at same
time('sc' return 1), and the variable is only *added by 1*, sometimes,
which is wrong and unacceptable(it should be added by 2).
Why disable fix-loongson3-llsc in compiler?
Because compiler fix will cause problems in kernel's __ex_table section.
This patch fix all the cases in kernel, but:
+. the fix at the end of futex_atomic_cmpxchg_inatomic is for branch-target
of 'bne', there other cases which smp_mb__before_llsc() and smp_llsc_mb() fix
the ll and branch-target coincidently such as atomic_sub_if_positive/
cmpxchg/xchg, just like this one.
+. Loongson 3 does support CONFIG_EDAC_ATOMIC_SCRUB, so no need to touch
edac.h
+. local_ops and cmpxchg_local should not be affected by this bug since
only the owner can write.
+. mips_atomic_set for syscall.c is deprecated and rarely used, just let
it go
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huang Pei <huangpei@loongson.cn>
[paul.burton@mips.com:
- Simplify the addition of -mno-fix-loongson3-llsc to cflags, and add
a comment describing why it's there.
- Make loongson_llsc_mb() a no-op when
CONFIG_CPU_LOONGSON3_WORKAROUNDS=n, rather than a compiler memory
barrier.
- Add a comment describing the bug & how loongson_llsc_mb() helps
in asm/barrier.h.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: ambrosehua@gmail.com
Cc: Steven J . Hill <Steven.Hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Li Xuefeng <lixuefeng@loongson.cn>
Cc: Xu Chenghua <xuchenghua@loongson.cn>
2019-01-15 01:04:54 -07:00
|
|
|
loongson_llsc_mb(); \
|
2016-04-17 17:16:06 -06:00
|
|
|
__asm__ __volatile__( \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n" \
|
2016-04-17 17:16:06 -06:00
|
|
|
"1: lld %1, %2 # atomic64_fetch_" #op "\n" \
|
|
|
|
|
" " #asm_op " %0, %1, %3 \n" \
|
|
|
|
|
" scd %0, %2 \n" \
|
2017-11-18 21:00:51 -07:00
|
|
|
"\t" __scbeqz " %0, 1b \n" \
|
2016-04-17 17:16:06 -06:00
|
|
|
" move %0, %1 \n" \
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n" \
|
2016-04-17 17:16:06 -06:00
|
|
|
: "=&r" (result), "=&r" (temp), \
|
|
|
|
|
"+" GCC_OFF_SMALL_ASM() (v->counter) \
|
|
|
|
|
: "Ir" (i)); \
|
|
|
|
|
} else { \
|
|
|
|
|
unsigned long flags; \
|
|
|
|
|
\
|
|
|
|
|
raw_local_irq_save(flags); \
|
|
|
|
|
result = v->counter; \
|
|
|
|
|
v->counter c_op i; \
|
|
|
|
|
raw_local_irq_restore(flags); \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
return result; \
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-15 15:09:54 -07:00
|
|
|
#define ATOMIC64_OPS(op, c_op, asm_op) \
|
|
|
|
|
ATOMIC64_OP(op, c_op, asm_op) \
|
2016-04-17 17:16:06 -06:00
|
|
|
ATOMIC64_OP_RETURN(op, c_op, asm_op) \
|
|
|
|
|
ATOMIC64_FETCH_OP(op, c_op, asm_op)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2014-03-26 10:56:43 -06:00
|
|
|
ATOMIC64_OPS(add, +=, daddu)
|
|
|
|
|
ATOMIC64_OPS(sub, -=, dsubu)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2016-04-17 17:15:25 -06:00
|
|
|
#define atomic64_add_return_relaxed atomic64_add_return_relaxed
|
|
|
|
|
#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
|
|
|
|
|
#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
|
|
|
|
|
#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
|
|
|
|
|
|
2014-03-26 10:56:43 -06:00
|
|
|
#undef ATOMIC64_OPS
|
2016-04-17 17:16:06 -06:00
|
|
|
#define ATOMIC64_OPS(op, c_op, asm_op) \
|
|
|
|
|
ATOMIC64_OP(op, c_op, asm_op) \
|
|
|
|
|
ATOMIC64_FETCH_OP(op, c_op, asm_op)
|
|
|
|
|
|
|
|
|
|
ATOMIC64_OPS(and, &=, and)
|
|
|
|
|
ATOMIC64_OPS(or, |=, or)
|
|
|
|
|
ATOMIC64_OPS(xor, ^=, xor)
|
|
|
|
|
|
2016-04-17 17:15:25 -06:00
|
|
|
#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
|
|
|
|
|
#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
|
|
|
|
|
#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
|
|
|
|
|
|
2016-04-17 17:16:06 -06:00
|
|
|
#undef ATOMIC64_OPS
|
|
|
|
|
#undef ATOMIC64_FETCH_OP
|
2014-03-26 10:56:43 -06:00
|
|
|
#undef ATOMIC64_OP_RETURN
|
|
|
|
|
#undef ATOMIC64_OP
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
/*
|
2014-11-15 15:09:54 -07:00
|
|
|
* atomic64_sub_if_positive - conditionally subtract integer from atomic
|
|
|
|
|
* variable
|
2005-11-12 16:38:18 -07:00
|
|
|
* @i: integer value to subtract
|
2005-04-16 16:20:36 -06:00
|
|
|
* @v: pointer of type atomic64_t
|
|
|
|
|
*
|
2005-11-12 16:38:18 -07:00
|
|
|
* Atomically test @v and subtract @i if @v is greater or equal than @i.
|
|
|
|
|
* The function returns the old value of @v minus @i.
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
|
|
|
|
static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
|
|
|
|
|
{
|
2009-01-11 17:52:18 -07:00
|
|
|
long result;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2010-01-08 18:17:43 -07:00
|
|
|
smp_mb__before_llsc();
|
2006-10-30 20:45:07 -07:00
|
|
|
|
2017-11-18 21:00:51 -07:00
|
|
|
if (kernel_uses_llsc) {
|
2009-01-11 17:52:18 -07:00
|
|
|
long temp;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
__asm__ __volatile__(
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set push \n"
|
2015-01-06 04:09:24 -07:00
|
|
|
" .set "MIPS_ISA_LEVEL" \n"
|
2005-04-16 16:20:36 -06:00
|
|
|
"1: lld %1, %2 # atomic64_sub_if_positive\n"
|
|
|
|
|
" dsubu %0, %1, %3 \n"
|
2017-11-18 20:29:56 -07:00
|
|
|
" move %1, %0 \n"
|
2005-04-16 16:20:36 -06:00
|
|
|
" bltz %0, 1f \n"
|
2017-11-18 20:29:56 -07:00
|
|
|
" scd %1, %2 \n"
|
2017-11-18 21:00:51 -07:00
|
|
|
"\t" __scbeqz " %1, 1b \n"
|
2008-07-03 16:28:35 -06:00
|
|
|
"1: \n"
|
2018-11-08 13:14:38 -07:00
|
|
|
" .set pop \n"
|
2014-11-15 15:08:48 -07:00
|
|
|
: "=&r" (result), "=&r" (temp),
|
2015-01-26 05:44:11 -07:00
|
|
|
"+" GCC_OFF_SMALL_ASM() (v->counter)
|
2012-06-24 19:01:34 -06:00
|
|
|
: "Ir" (i));
|
2005-04-16 16:20:36 -06:00
|
|
|
} else {
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
2007-03-16 10:10:36 -06:00
|
|
|
raw_local_irq_save(flags);
|
2005-04-16 16:20:36 -06:00
|
|
|
result = v->counter;
|
|
|
|
|
result -= i;
|
|
|
|
|
if (result >= 0)
|
|
|
|
|
v->counter = result;
|
2007-03-16 10:10:36 -06:00
|
|
|
raw_local_irq_restore(flags);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
2007-07-14 06:24:05 -06:00
|
|
|
smp_llsc_mb();
|
2006-10-30 20:45:07 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
2007-05-08 01:34:24 -06:00
|
|
|
#define atomic64_cmpxchg(v, o, n) \
|
2007-05-10 08:47:45 -06:00
|
|
|
((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
|
2007-05-08 01:34:24 -06:00
|
|
|
#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
|
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/*
|
|
|
|
|
* atomic64_dec_if_positive - decrement by 1 if old value positive
|
|
|
|
|
* @v: pointer of type atomic64_t
|
|
|
|
|
*/
|
|
|
|
|
#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
|
|
|
|
|
|
2005-09-03 16:56:16 -06:00
|
|
|
#endif /* CONFIG_64BIT */
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
#endif /* _ASM_ATOMIC_H */
|