2005-11-10 07:26:51 -07:00
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/*
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2006-10-03 15:01:26 -06:00
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* linux/arch/arm/mach-omap2/irq.c
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2005-11-10 07:26:51 -07:00
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*
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* Interrupt handler for OMAP2 boards.
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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2011-11-30 11:21:07 -07:00
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#include <linux/module.h>
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2005-11-10 07:26:51 -07:00
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#include <linux/init.h>
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#include <linux/interrupt.h>
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2008-10-09 08:51:28 -06:00
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#include <linux/io.h>
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2012-02-24 11:34:35 -07:00
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2011-09-06 02:56:17 -06:00
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#include <asm/exception.h>
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2005-11-10 07:26:51 -07:00
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#include <asm/mach/irq.h>
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2011-11-30 11:21:07 -07:00
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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2012-06-05 05:01:06 -06:00
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#include <linux/of_irq.h>
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2005-11-10 07:26:51 -07:00
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2012-08-31 11:59:07 -06:00
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#include "soc.h"
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2012-02-24 11:34:35 -07:00
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#include "iomap.h"
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2012-04-13 06:34:26 -06:00
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#include "common.h"
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2008-10-09 08:51:28 -06:00
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/* selected INTC register offsets */
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#define INTC_REVISION 0x0000
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#define INTC_SYSCONFIG 0x0010
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#define INTC_SYSSTATUS 0x0014
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2008-12-10 18:36:52 -07:00
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#define INTC_SIR 0x0040
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2008-10-09 08:51:28 -06:00
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#define INTC_CONTROL 0x0048
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2008-09-26 06:18:20 -06:00
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#define INTC_PROTECTION 0x004C
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#define INTC_IDLE 0x0050
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#define INTC_THRESHOLD 0x0068
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#define INTC_MIR0 0x0084
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2008-10-09 08:51:28 -06:00
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#define INTC_MIR_CLEAR0 0x0088
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#define INTC_MIR_SET0 0x008c
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#define INTC_PENDING_IRQ0 0x0098
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2014-09-08 18:54:32 -06:00
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#define INTC_ILR0 0x0100
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2005-11-10 07:26:51 -07:00
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2011-09-06 02:56:17 -06:00
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#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
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#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
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#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
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#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
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2014-09-08 18:54:35 -06:00
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#define INTCPS_NR_ILR_REGS 128
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2012-09-04 18:43:29 -06:00
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#define INTCPS_NR_MIR_REGS 3
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2011-09-06 02:56:17 -06:00
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2005-11-10 07:26:51 -07:00
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/*
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* OMAP2 has a number of different interrupt controllers, each interrupt
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* controller is identified as its own "bank". Register definitions are
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* fairly consistent for each bank, but not all registers are implemented
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* for each bank.. when in doubt, consult the TRM.
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*/
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2011-11-30 11:21:07 -07:00
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static struct irq_domain *domain;
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2014-09-08 18:54:31 -06:00
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static void __iomem *omap_irq_base;
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2014-09-08 18:54:34 -06:00
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static int omap_nr_irqs = 96;
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2011-11-30 11:21:07 -07:00
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2008-09-26 06:18:20 -06:00
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/* Structure to save interrupt controller context */
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struct omap3_intc_regs {
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u32 sysconfig;
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u32 protection;
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u32 idle;
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u32 threshold;
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2014-09-08 18:54:35 -06:00
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u32 ilr[INTCPS_NR_ILR_REGS];
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2008-09-26 06:18:20 -06:00
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u32 mir[INTCPS_NR_MIR_REGS];
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};
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2008-10-09 08:51:28 -06:00
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/* INTC bank register get/set */
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2014-09-08 18:54:32 -06:00
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static void intc_writel(u32 reg, u32 val)
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2008-10-09 08:51:28 -06:00
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{
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2014-09-08 18:54:32 -06:00
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writel_relaxed(val, omap_irq_base + reg);
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2008-10-09 08:51:28 -06:00
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}
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2014-09-08 18:54:32 -06:00
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static u32 intc_readl(u32 reg)
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2008-10-09 08:51:28 -06:00
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{
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2014-09-08 18:54:32 -06:00
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return readl_relaxed(omap_irq_base + reg);
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2008-10-09 08:51:28 -06:00
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}
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2005-11-10 07:26:51 -07:00
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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2010-11-29 02:39:59 -07:00
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static void omap_ack_irq(struct irq_data *d)
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2005-11-10 07:26:51 -07:00
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{
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2014-09-08 18:54:32 -06:00
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intc_writel(INTC_CONTROL, 0x1);
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2005-11-10 07:26:51 -07:00
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}
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2010-11-29 02:39:59 -07:00
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static void omap_mask_ack_irq(struct irq_data *d)
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2005-11-10 07:26:51 -07:00
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{
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2011-05-16 03:07:38 -06:00
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irq_gc_mask_disable_reg(d);
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2010-11-29 02:39:59 -07:00
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omap_ack_irq(d);
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2005-11-10 07:26:51 -07:00
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}
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2014-09-08 18:54:35 -06:00
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static void __init omap_irq_soft_reset(void)
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2005-11-10 07:26:51 -07:00
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{
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unsigned long tmp;
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2014-09-08 18:54:32 -06:00
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tmp = intc_readl(INTC_REVISION) & 0xff;
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2014-09-08 18:54:35 -06:00
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2012-07-26 00:54:26 -06:00
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pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
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2014-09-08 18:54:35 -06:00
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omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
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2005-11-10 07:26:51 -07:00
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2014-09-08 18:54:32 -06:00
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tmp = intc_readl(INTC_SYSCONFIG);
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2005-11-10 07:26:51 -07:00
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tmp |= 1 << 1; /* soft reset */
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2014-09-08 18:54:32 -06:00
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intc_writel(INTC_SYSCONFIG, tmp);
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2005-11-10 07:26:51 -07:00
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2014-09-08 18:54:32 -06:00
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while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
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2005-11-10 07:26:51 -07:00
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/* Wait for reset to complete */;
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2006-12-06 18:13:50 -07:00
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/* Enable autoidle */
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2014-09-08 18:54:32 -06:00
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intc_writel(INTC_SYSCONFIG, 1 << 0);
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2005-11-10 07:26:51 -07:00
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}
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2009-02-03 16:49:04 -07:00
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int omap_irq_pending(void)
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{
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2014-09-08 18:54:35 -06:00
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int irq;
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2009-02-03 16:49:04 -07:00
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2014-09-08 18:54:35 -06:00
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for (irq = 0; irq < omap_nr_irqs; irq += 32)
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if (intc_readl(INTC_PENDING_IRQ0 +
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((irq >> 5) << 5)))
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return 1;
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2009-02-03 16:49:04 -07:00
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return 0;
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}
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2011-05-16 03:07:38 -06:00
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static __init void
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omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
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handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_ack = omap_mask_ack_irq;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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2012-04-24 21:05:24 -06:00
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ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
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2011-05-16 03:07:38 -06:00
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ct->regs.enable = INTC_MIR_CLEAR0;
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ct->regs.disable = INTC_MIR_SET0;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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}
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2011-11-30 11:21:07 -07:00
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static void __init omap_init_irq(u32 base, int nr_irqs,
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struct device_node *node)
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2005-11-10 07:26:51 -07:00
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{
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2014-09-08 18:54:35 -06:00
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int j, irq_base;
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2005-11-10 07:26:51 -07:00
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2011-05-17 04:51:26 -06:00
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omap_irq_base = ioremap(base, SZ_4K);
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if (WARN_ON(!omap_irq_base))
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return;
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2014-09-08 18:54:34 -06:00
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omap_nr_irqs = nr_irqs;
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2011-11-30 11:21:07 -07:00
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irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
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if (irq_base < 0) {
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pr_warn("Couldn't allocate IRQ numbers\n");
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irq_base = 0;
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}
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domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
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2014-09-08 18:54:35 -06:00
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&irq_domain_simple_ops, NULL);
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2005-11-10 07:26:51 -07:00
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2014-09-08 18:54:35 -06:00
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omap_irq_soft_reset();
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2011-05-16 03:07:38 -06:00
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2014-09-08 18:54:35 -06:00
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for (j = 0; j < omap_nr_irqs; j += 32)
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omap_alloc_gc(omap_irq_base + j, j + irq_base, 32);
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2005-11-10 07:26:51 -07:00
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}
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2011-05-17 04:51:26 -06:00
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void __init omap2_init_irq(void)
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{
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2011-11-30 11:21:07 -07:00
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omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
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2011-05-17 04:51:26 -06:00
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}
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void __init omap3_init_irq(void)
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{
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2011-11-30 11:21:07 -07:00
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omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
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2011-05-17 04:51:26 -06:00
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}
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2011-12-13 11:46:44 -07:00
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void __init ti81xx_init_irq(void)
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2011-05-17 04:51:26 -06:00
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{
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2011-11-30 11:21:07 -07:00
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omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
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2011-05-17 04:51:26 -06:00
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}
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2011-09-06 02:56:17 -06:00
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static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
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{
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u32 irqnr;
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2014-03-06 08:27:15 -07:00
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int handled_irq = 0;
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2011-09-06 02:56:17 -06:00
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do {
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irqnr = readl_relaxed(base_addr + 0x98);
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if (irqnr)
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goto out;
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irqnr = readl_relaxed(base_addr + 0xb8);
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if (irqnr)
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goto out;
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irqnr = readl_relaxed(base_addr + 0xd8);
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2013-10-17 01:18:38 -06:00
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#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
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2011-09-06 02:56:17 -06:00
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if (irqnr)
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goto out;
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irqnr = readl_relaxed(base_addr + 0xf8);
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#endif
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out:
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if (!irqnr)
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break;
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irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
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irqnr &= ACTIVEIRQ_MASK;
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2011-11-30 11:21:07 -07:00
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if (irqnr) {
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irqnr = irq_find_mapping(domain, irqnr);
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2011-09-06 02:56:17 -06:00
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handle_IRQ(irqnr, regs);
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2014-03-06 08:27:15 -07:00
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handled_irq = 1;
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2011-11-30 11:21:07 -07:00
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}
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2011-09-06 02:56:17 -06:00
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} while (irqnr);
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2014-03-06 08:27:15 -07:00
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/* If an irq is masked or deasserted while active, we will
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* keep ending up here with no irq handled. So remove it from
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* the INTC with an ack.*/
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if (!handled_irq)
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omap_ack_irq(NULL);
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2011-09-06 02:56:17 -06:00
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}
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asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
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{
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void __iomem *base_addr = OMAP2_IRQ_BASE;
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omap_intc_handle_irq(base_addr, regs);
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}
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2012-06-05 05:01:06 -06:00
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int __init intc_of_init(struct device_node *node,
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2011-11-30 11:21:07 -07:00
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struct device_node *parent)
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{
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struct resource res;
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2012-06-25 04:26:39 -06:00
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u32 nr_irq = 96;
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2011-11-30 11:21:07 -07:00
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if (WARN_ON(!node))
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return -ENODEV;
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if (of_address_to_resource(node, 0, &res)) {
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WARN(1, "unable to get intc registers\n");
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return -EINVAL;
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}
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2012-06-25 04:26:39 -06:00
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if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
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pr_warn("unable to get intc-size, default to %d\n", nr_irq);
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2011-11-30 11:21:07 -07:00
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2012-06-25 04:26:39 -06:00
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omap_init_irq(res.start, nr_irq, of_node_get(node));
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2011-11-30 11:21:07 -07:00
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return 0;
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}
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2014-09-10 02:26:17 -06:00
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static const struct of_device_id irq_match[] __initconst = {
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2012-06-05 05:01:06 -06:00
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{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
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{ }
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};
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void __init omap_intc_of_init(void)
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{
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of_irq_init(irq_match);
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}
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2012-05-10 13:08:49 -06:00
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
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2014-09-08 18:54:35 -06:00
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static struct omap3_intc_regs intc_context;
|
2011-01-27 17:39:43 -07:00
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2008-09-26 06:18:20 -06:00
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void omap_intc_save_context(void)
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{
|
2014-09-08 18:54:35 -06:00
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int i;
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intc_context.sysconfig =
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intc_readl(INTC_SYSCONFIG);
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intc_context.protection =
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|
|
|
intc_readl(INTC_PROTECTION);
|
|
|
|
intc_context.idle =
|
|
|
|
intc_readl(INTC_IDLE);
|
|
|
|
intc_context.threshold =
|
|
|
|
intc_readl(INTC_THRESHOLD);
|
|
|
|
|
|
|
|
for (i = 0; i < omap_nr_irqs; i++)
|
|
|
|
intc_context.ilr[i] =
|
|
|
|
intc_readl((INTC_ILR0 + 0x4 * i));
|
|
|
|
for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
|
|
|
|
intc_context.mir[i] =
|
|
|
|
intc_readl(INTC_MIR0 + (0x20 * i));
|
2008-09-26 06:18:20 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void omap_intc_restore_context(void)
|
|
|
|
{
|
2014-09-08 18:54:35 -06:00
|
|
|
int i;
|
|
|
|
|
|
|
|
intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
|
|
|
|
intc_writel(INTC_PROTECTION, intc_context.protection);
|
|
|
|
intc_writel(INTC_IDLE, intc_context.idle);
|
|
|
|
intc_writel(INTC_THRESHOLD, intc_context.threshold);
|
|
|
|
|
|
|
|
for (i = 0; i < omap_nr_irqs; i++)
|
|
|
|
intc_writel(INTC_ILR0 + 0x4 * i,
|
|
|
|
intc_context.ilr[i]);
|
|
|
|
|
|
|
|
for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
|
|
|
|
intc_writel(INTC_MIR0 + 0x20 * i,
|
|
|
|
intc_context.mir[i]);
|
2008-09-26 06:18:20 -06:00
|
|
|
/* MIRs are saved and restore with other PRCM registers */
|
|
|
|
}
|
2009-10-23 10:03:48 -06:00
|
|
|
|
|
|
|
void omap3_intc_suspend(void)
|
|
|
|
{
|
|
|
|
/* A pending interrupt would prevent OMAP from entering suspend */
|
2012-04-13 06:34:28 -06:00
|
|
|
omap_ack_irq(NULL);
|
2009-10-23 10:03:48 -06:00
|
|
|
}
|
2009-10-23 10:03:50 -06:00
|
|
|
|
|
|
|
void omap3_intc_prepare_idle(void)
|
|
|
|
{
|
2010-11-17 10:52:11 -07:00
|
|
|
/*
|
|
|
|
* Disable autoidle as it can stall interrupt controller,
|
|
|
|
* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
|
|
|
|
*/
|
2014-09-08 18:54:32 -06:00
|
|
|
intc_writel(INTC_SYSCONFIG, 0);
|
2009-10-23 10:03:50 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void omap3_intc_resume_idle(void)
|
|
|
|
{
|
|
|
|
/* Re-enable autoidle */
|
2014-09-08 18:54:32 -06:00
|
|
|
intc_writel(INTC_SYSCONFIG, 1);
|
2009-10-23 10:03:50 -06:00
|
|
|
}
|
2011-09-06 02:56:17 -06:00
|
|
|
|
|
|
|
asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
void __iomem *base_addr = OMAP3_IRQ_BASE;
|
|
|
|
omap_intc_handle_irq(base_addr, regs);
|
|
|
|
}
|
2008-09-26 06:18:20 -06:00
|
|
|
#endif /* CONFIG_ARCH_OMAP3 */
|