2005-11-10 07:26:52 -07:00
|
|
|
/*
|
|
|
|
* linux/arch/arm/mach-omap2/clock.c
|
|
|
|
*
|
2008-03-18 03:56:39 -06:00
|
|
|
* Copyright (C) 2005-2008 Texas Instruments, Inc.
|
|
|
|
* Copyright (C) 2004-2008 Nokia Corporation
|
2005-11-10 07:26:52 -07:00
|
|
|
*
|
2008-03-18 03:56:39 -06:00
|
|
|
* Contacts:
|
|
|
|
* Richard Woodruff <r-woodruff2@ti.com>
|
|
|
|
* Paul Walmsley
|
2005-11-10 07:26:52 -07:00
|
|
|
*
|
2008-03-18 03:56:39 -06:00
|
|
|
* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
|
|
|
|
* Gordon McNutt and RidgeRun, Inc.
|
2005-11-10 07:26:52 -07:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*/
|
2008-03-18 02:35:15 -06:00
|
|
|
#undef DEBUG
|
|
|
|
|
2005-11-10 07:26:52 -07:00
|
|
|
#include <linux/module.h>
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/device.h>
|
|
|
|
#include <linux/list.h>
|
|
|
|
#include <linux/errno.h>
|
|
|
|
#include <linux/delay.h>
|
2006-01-07 09:15:52 -07:00
|
|
|
#include <linux/clk.h>
|
2008-03-18 02:35:15 -06:00
|
|
|
#include <linux/io.h>
|
|
|
|
#include <linux/cpufreq.h>
|
2008-09-06 05:13:59 -06:00
|
|
|
#include <linux/bitops.h>
|
2005-11-10 07:26:52 -07:00
|
|
|
|
2009-10-20 10:40:47 -06:00
|
|
|
#include <plat/clock.h>
|
|
|
|
#include <plat/sram.h>
|
|
|
|
#include <plat/prcm.h>
|
2009-12-08 16:18:47 -07:00
|
|
|
#include <plat/clkdev_omap.h>
|
2006-12-13 00:02:43 -07:00
|
|
|
#include <asm/div64.h>
|
2009-01-19 08:27:29 -07:00
|
|
|
#include <asm/clkdev.h>
|
2005-11-10 07:26:52 -07:00
|
|
|
|
2009-10-20 10:40:47 -06:00
|
|
|
#include <plat/sdrc.h>
|
2008-03-18 02:35:15 -06:00
|
|
|
#include "clock.h"
|
2009-12-08 16:21:29 -07:00
|
|
|
#include "clock2xxx.h"
|
|
|
|
#include "opp2xxx.h"
|
2008-03-18 02:35:15 -06:00
|
|
|
#include "prm.h"
|
|
|
|
#include "prm-regbits-24xx.h"
|
|
|
|
#include "cm.h"
|
|
|
|
#include "cm-regbits-24xx.h"
|
2005-11-10 07:26:52 -07:00
|
|
|
|
2009-12-08 16:21:29 -07:00
|
|
|
struct clk *vclk, *sclk, *dclk;
|
2005-11-10 07:26:52 -07:00
|
|
|
|
|
|
|
/*-------------------------------------------------------------------------
|
2008-03-18 02:35:15 -06:00
|
|
|
* Omap24xx specific clock functions
|
2005-11-10 07:26:52 -07:00
|
|
|
*-------------------------------------------------------------------------*/
|
|
|
|
|
2010-01-26 20:13:09 -07:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2430
|
|
|
|
|
2009-07-24 19:44:04 -06:00
|
|
|
/**
|
|
|
|
* omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
|
|
|
|
* @clk: struct clk * being enabled
|
|
|
|
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
|
|
|
|
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
|
|
|
|
*
|
|
|
|
* OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
|
|
|
|
* CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
|
|
|
|
* passes back the correct CM_IDLEST register address for I2CHS
|
|
|
|
* modules. No return value.
|
|
|
|
*/
|
|
|
|
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
|
|
|
|
void __iomem **idlest_reg,
|
|
|
|
u8 *idlest_bit)
|
|
|
|
{
|
|
|
|
*idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
|
|
|
|
*idlest_bit = clk->enable_bit;
|
|
|
|
}
|
|
|
|
|
2010-01-26 20:13:09 -07:00
|
|
|
#else
|
|
|
|
#define omap2430_clk_i2chs_find_idlest NULL
|
|
|
|
#endif
|
|
|
|
|
2009-12-08 16:21:29 -07:00
|
|
|
/* 2430 I2CHS has non-standard IDLEST register */
|
|
|
|
const struct clkops clkops_omap2430_i2chs_wait = {
|
|
|
|
.enable = omap2_dflt_clk_enable,
|
|
|
|
.disable = omap2_dflt_clk_disable,
|
|
|
|
.find_idlest = omap2430_clk_i2chs_find_idlest,
|
|
|
|
.find_companion = omap2_clk_dflt_find_companion,
|
|
|
|
};
|
2009-07-24 19:44:04 -06:00
|
|
|
|
2006-09-25 03:41:20 -06:00
|
|
|
/*
|
|
|
|
* Set clocks for bypass mode for reboot to work.
|
|
|
|
*/
|
|
|
|
void omap2_clk_prepare_for_reboot(void)
|
|
|
|
{
|
|
|
|
u32 rate;
|
|
|
|
|
|
|
|
if (vclk == NULL || sclk == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
rate = clk_get_rate(sclk);
|
|
|
|
clk_set_rate(vclk, rate);
|
|
|
|
}
|
|
|
|
|
2005-11-10 07:26:52 -07:00
|
|
|
/*
|
|
|
|
* Switch the MPU rate if specified on cmdline.
|
|
|
|
* We cannot do this early until cmdline is parsed.
|
|
|
|
*/
|
|
|
|
static int __init omap2_clk_arch_init(void)
|
|
|
|
{
|
2009-12-08 16:21:29 -07:00
|
|
|
struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
|
|
|
|
unsigned long sys_ck_rate;
|
|
|
|
|
2005-11-10 07:26:52 -07:00
|
|
|
if (!mpurate)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2009-12-08 16:21:29 -07:00
|
|
|
virt_prcm_set = clk_get(NULL, "virt_prcm_set");
|
|
|
|
sys_ck = clk_get(NULL, "sys_ck");
|
|
|
|
dpll_ck = clk_get(NULL, "dpll_ck");
|
|
|
|
mpu_ck = clk_get(NULL, "mpu_ck");
|
|
|
|
|
|
|
|
if (clk_set_rate(virt_prcm_set, mpurate))
|
2005-11-10 07:26:52 -07:00
|
|
|
printk(KERN_ERR "Could not find matching MPU rate\n");
|
|
|
|
|
2008-03-18 02:35:15 -06:00
|
|
|
recalculate_root_clocks();
|
2005-11-10 07:26:52 -07:00
|
|
|
|
2009-12-08 16:21:29 -07:00
|
|
|
sys_ck_rate = clk_get_rate(sys_ck);
|
|
|
|
|
|
|
|
pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
|
|
|
|
"%ld.%01ld/%ld/%ld MHz\n",
|
|
|
|
(sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
|
|
|
|
(clk_get_rate(dpll_ck) / 1000000),
|
|
|
|
(clk_get_rate(mpu_ck) / 1000000));
|
2005-11-10 07:26:52 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
arch_initcall(omap2_clk_arch_init);
|
|
|
|
|
|
|
|
|