2005-09-23 13:08:58 -06:00
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#ifndef __ASM_POWERPC_CPUTABLE_H
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#define __ASM_POWERPC_CPUTABLE_H
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[PATCH] powerpc: Consolidate asm compatibility macros
This patch consolidates macros used to generate assembly for
compatibility across different CPUs or configs. A new header,
asm-powerpc/asm-compat.h contains the main compatibility macros. It
uses some preprocessor magic to make the macros suitable both for use
in .S files, and in inline asm in .c files. Headers (bitops.h,
uaccess.h, atomic.h, bug.h) which had their own such compatibility
macros are changed to use asm-compat.h.
ppc_asm.h is now for use in .S files *only*, and a #error enforces
that. As such, we're a lot more careless about namespace pollution
here than in asm-compat.h.
While we're at it, this patch adds a call to the PPC405_ERR77 macro in
futex.h which should have had it already, but didn't.
Built and booted on pSeries, Maple and iSeries (ARCH=powerpc). Built
for 32-bit powermac (ARCH=powerpc) and Walnut (ARCH=ppc).
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-09 18:56:55 -07:00
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#include <asm/asm-compat.h>
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2005-09-23 13:08:58 -06:00
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#define PPC_FEATURE_32 0x80000000
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#define PPC_FEATURE_64 0x40000000
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#define PPC_FEATURE_601_INSTR 0x20000000
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#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
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#define PPC_FEATURE_HAS_FPU 0x08000000
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#define PPC_FEATURE_HAS_MMU 0x04000000
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#define PPC_FEATURE_HAS_4xxMAC 0x02000000
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#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
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#define PPC_FEATURE_HAS_SPE 0x00800000
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#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
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#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
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2005-10-22 00:51:34 -06:00
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#define PPC_FEATURE_NO_TB 0x00100000
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2005-11-09 20:29:18 -07:00
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#define PPC_FEATURE_POWER4 0x00080000
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#define PPC_FEATURE_POWER5 0x00040000
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#define PPC_FEATURE_POWER5_PLUS 0x00020000
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#define PPC_FEATURE_CELL 0x00010000
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2006-01-13 16:11:39 -07:00
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#define PPC_FEATURE_BOOKE 0x00008000
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2006-02-28 21:07:07 -07:00
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#define PPC_FEATURE_SMT 0x00004000
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#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
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2006-04-28 17:51:06 -06:00
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#define PPC_FEATURE_ARCH_2_05 0x00001000
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2006-09-06 13:35:57 -06:00
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#define PPC_FEATURE_PA6T 0x00000800
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2006-11-10 02:38:53 -07:00
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#define PPC_FEATURE_HAS_DFP 0x00000400
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#define PPC_FEATURE_POWER6_EXT 0x00000200
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2005-09-23 13:08:58 -06:00
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2006-06-07 00:14:40 -06:00
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#define PPC_FEATURE_TRUE_LE 0x00000002
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#define PPC_FEATURE_PPC_LE 0x00000001
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2005-09-23 13:08:58 -06:00
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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/* This structure can grow, it's real size is used by head.S code
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* via the mkdefs mechanism.
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*/
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struct cpu_spec;
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typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
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2006-08-10 23:07:08 -06:00
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typedef void (*cpu_restore_t)(void);
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2005-09-23 13:08:58 -06:00
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2006-01-08 21:41:31 -07:00
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enum powerpc_oprofile_type {
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2006-01-13 05:35:49 -07:00
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PPC_OPROFILE_INVALID = 0,
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PPC_OPROFILE_RS64 = 1,
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PPC_OPROFILE_POWER4 = 2,
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PPC_OPROFILE_G4 = 3,
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PPC_OPROFILE_BOOKE = 4,
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[POWERPC] cell: Add oprofile support
Add PPU event-based and cycle-based profiling support to Oprofile for Cell.
Oprofile is expected to collect data on all CPUs simultaneously.
However, there is one set of performance counters per node. There are
two hardware threads or virtual CPUs on each node. Hence, OProfile must
multiplex in time the performance counter collection on the two virtual
CPUs.
The multiplexing of the performance counters is done by a virtual
counter routine. Initially, the counters are configured to collect data
on the even CPUs in the system, one CPU per node. In order to capture
the PC for the virtual CPU when the performance counter interrupt occurs
(the specified number of events between samples has occurred), the even
processors are configured to handle the performance counter interrupts
for their node. The virtual counter routine is called via a kernel
timer after the virtual sample time. The routine stops the counters,
saves the current counts, loads the last counts for the other virtual
CPU on the node, sets interrupts to be handled by the other virtual CPU
and restarts the counters, the virtual timer routine is scheduled to run
again. The virtual sample time is kept relatively small to make sure
sampling occurs on both CPUs on the node with a relatively small
granularity. Whenever the counters overflow, the performance counter
interrupt is called to collect the PC for the CPU where data is being
collected.
The oprofile driver relies on a firmware RTAS call to setup the debug bus
to route the desired signals to the performance counter hardware to be
counted. The RTAS call must set the routing registers appropriately in
each of the islands to pass the signals down the debug bus as well as
routing the signals from a particular island onto the bus. There is a
second firmware RTAS call to reset the debug bus to the non pass thru
state when the counters are not in use.
Signed-off-by: Carl Love <carll@us.ibm.com>
Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-20 10:45:16 -07:00
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PPC_OPROFILE_CELL = 5,
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2006-01-08 21:41:31 -07:00
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};
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2005-09-23 13:08:58 -06:00
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struct cpu_spec {
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/* CPU is matched via (PVR & pvr_mask) == pvr_value */
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unsigned int pvr_mask;
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unsigned int pvr_value;
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char *cpu_name;
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unsigned long cpu_features; /* Kernel features */
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unsigned int cpu_user_features; /* Userland features */
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/* cache line sizes */
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unsigned int icache_bsize;
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unsigned int dcache_bsize;
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/* number of performance monitor counters */
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unsigned int num_pmcs;
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/* this is called to initialize various CPU bits like L1 cache,
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* BHT, SPD, etc... from head.S before branching to identify_machine
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*/
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cpu_setup_t cpu_setup;
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2006-08-10 23:07:08 -06:00
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/* Used to restore cpu setup on secondary processors and at resume */
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cpu_restore_t cpu_restore;
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2005-09-23 13:08:58 -06:00
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/* Used by oprofile userspace to select the right counters */
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char *oprofile_cpu_type;
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/* Processor specific oprofile operations */
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2006-01-08 21:41:31 -07:00
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enum powerpc_oprofile_type oprofile_type;
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2006-01-13 16:11:39 -07:00
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2006-06-07 22:42:34 -06:00
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/* Bit locations inside the mmcra change */
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unsigned long oprofile_mmcra_sihv;
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unsigned long oprofile_mmcra_sipr;
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/* Bits to clear during an oprofile exception */
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unsigned long oprofile_mmcra_clear;
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2006-01-13 16:11:39 -07:00
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/* Name of processor class, for the ELF AT_PLATFORM entry */
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char *platform;
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2005-09-23 13:08:58 -06:00
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};
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extern struct cpu_spec *cur_cpu_spec;
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2006-10-24 00:42:40 -06:00
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extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
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2006-11-10 02:38:53 -07:00
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extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
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2006-10-19 19:47:18 -06:00
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extern void do_feature_fixups(unsigned long value, void *fixup_start,
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void *fixup_end);
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2005-10-05 20:06:20 -06:00
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2005-09-23 13:08:58 -06:00
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#endif /* __ASSEMBLY__ */
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/* CPU kernel features */
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/* Retain the 32b definitions all use bottom half of word */
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#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
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#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
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#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
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#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
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#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
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#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
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#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
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#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
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#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
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#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
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#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
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#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
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#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
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#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
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#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
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#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
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#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
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#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
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#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
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#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
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2006-03-21 02:45:58 -07:00
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#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
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2006-06-07 00:14:40 -06:00
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#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
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#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
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2005-09-23 13:08:58 -06:00
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2006-06-27 21:50:39 -06:00
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/*
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* Add the 64-bit processor unique features in the top half of the word;
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* on 32-bit, make the names available but defined to be 0.
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*/
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2005-09-23 13:08:58 -06:00
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#ifdef __powerpc64__
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2006-06-27 21:50:39 -06:00
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#define LONG_ASM_CONST(x) ASM_CONST(x)
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2005-09-23 13:08:58 -06:00
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#else
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2006-06-27 21:50:39 -06:00
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#define LONG_ASM_CONST(x) 0
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2005-09-23 13:08:58 -06:00
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#endif
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2006-06-27 21:50:39 -06:00
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#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
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#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
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#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
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#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
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#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
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#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
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#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
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#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
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#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
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#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
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#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
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#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
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#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
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2006-10-19 22:37:05 -06:00
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#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
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2006-11-10 02:38:53 -07:00
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#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
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2006-06-27 21:50:39 -06:00
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2005-09-23 13:08:58 -06:00
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#ifndef __ASSEMBLY__
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2006-11-29 17:46:22 -07:00
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#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
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CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
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CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
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2005-09-23 13:08:58 -06:00
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/* We only set the altivec features if the kernel was compiled with altivec
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* support
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*/
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#ifdef CONFIG_ALTIVEC
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#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
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#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
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#else
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#define CPU_FTR_ALTIVEC_COMP 0
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#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
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#endif
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/* We need to mark all pages as being coherent if we're SMP or we
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2006-02-22 08:46:02 -07:00
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* have a 74[45]x and an MPC107 host bridge. Also 83xx requires
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* it for PCI "streaming/prefetch" to work properly.
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2005-09-23 13:08:58 -06:00
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*/
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2006-02-22 08:46:02 -07:00
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#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
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|| defined(CONFIG_PPC_83xx)
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2005-09-23 13:08:58 -06:00
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#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
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#else
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#define CPU_FTR_COMMON 0
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#endif
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/* The powersave features NAP & DOZE seems to confuse BDI when
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debugging. So if a BDI is used, disable theses
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*/
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#ifndef CONFIG_BDI_SWITCH
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#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
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#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
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#else
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#define CPU_FTR_MAYBE_CAN_DOZE 0
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#define CPU_FTR_MAYBE_CAN_NAP 0
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#endif
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#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
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!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
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!defined(CONFIG_BOOKE))
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2006-03-22 23:36:59 -07:00
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#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
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#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
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2006-06-07 00:14:40 -06:00
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
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2006-03-22 23:36:59 -07:00
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#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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2006-06-07 00:14:40 -06:00
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CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
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CPU_FTR_PPC_LE)
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2006-03-22 23:36:59 -07:00
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#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
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2006-06-07 00:14:40 -06:00
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CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
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2006-03-22 23:36:59 -07:00
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#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
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2006-06-07 00:14:40 -06:00
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CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
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CPU_FTR_PPC_LE)
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2006-03-22 23:36:59 -07:00
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#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
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2006-06-07 00:14:40 -06:00
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CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
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CPU_FTR_PPC_LE)
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2006-03-22 23:36:59 -07:00
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#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
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CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
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2006-06-07 00:14:40 -06:00
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CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
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2006-03-22 23:36:59 -07:00
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#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
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CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
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2006-06-07 00:14:40 -06:00
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CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
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2006-03-22 23:36:59 -07:00
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#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
|
|
|
|
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
|
|
|
|
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
|
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
|
|
|
|
CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
|
|
|
|
CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
|
|
|
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
|
|
|
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
|
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
|
|
|
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
|
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
|
|
|
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
|
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
|
|
|
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
|
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
|
|
|
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
|
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
|
|
|
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
|
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
|
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
|
|
|
|
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
|
|
|
|
#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
|
|
|
|
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
|
|
|
|
#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
|
|
|
|
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
|
|
|
|
CPU_FTR_COMMON)
|
|
|
|
#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
|
|
|
|
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
|
|
|
|
#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
|
|
|
|
#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_NODSISRALIGN)
|
|
|
|
#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_NODSISRALIGN)
|
|
|
|
#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
|
|
|
|
#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_NODSISRALIGN)
|
|
|
|
#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
|
|
|
|
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
|
2006-11-22 16:46:46 -07:00
|
|
|
|
|
|
|
/* 64-bit CPUs */
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
2006-06-07 00:14:40 -06:00
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
|
|
|
|
CPU_FTR_MMCRA | CPU_FTR_CTRL)
|
|
|
|
#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
2006-09-06 13:35:19 -06:00
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
|
|
|
CPU_FTR_MMCRA)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
2006-09-06 13:35:19 -06:00
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
2006-03-22 23:36:59 -07:00
|
|
|
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
|
|
|
|
#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
2006-09-06 13:35:19 -06:00
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
2006-03-22 23:36:59 -07:00
|
|
|
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
|
|
|
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
2006-06-07 22:42:34 -06:00
|
|
|
CPU_FTR_PURR)
|
2006-04-28 17:51:06 -06:00
|
|
|
#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
2006-09-06 13:35:19 -06:00
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
2006-04-28 17:51:06 -06:00
|
|
|
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
|
|
|
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
2006-11-10 02:38:53 -07:00
|
|
|
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE)
|
|
|
|
#define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
|
|
|
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
|
|
|
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
|
|
|
CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
|
|
|
|
CPU_FTR_SPURR | CPU_FTR_REAL_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
2006-09-06 13:35:19 -06:00
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
2006-03-22 23:36:59 -07:00
|
|
|
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
2006-10-19 22:37:05 -06:00
|
|
|
CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
|
2006-09-06 13:35:57 -06:00
|
|
|
#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
|
|
|
|
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
|
|
|
|
CPU_FTR_PURR | CPU_FTR_REAL_LE)
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
|
|
|
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
|
2005-09-23 13:08:58 -06:00
|
|
|
|
2005-12-12 13:45:33 -07:00
|
|
|
#ifdef __powerpc64__
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_POSSIBLE \
|
|
|
|
(CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
|
2006-04-28 17:51:06 -06:00
|
|
|
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
|
2006-09-06 13:35:57 -06:00
|
|
|
CPU_FTRS_CELL | CPU_FTRS_PA6T)
|
2005-12-12 13:45:33 -07:00
|
|
|
#else
|
2006-03-22 23:36:59 -07:00
|
|
|
enum {
|
|
|
|
CPU_FTRS_POSSIBLE =
|
2005-09-23 13:08:58 -06:00
|
|
|
#if CLASSIC_PPC
|
|
|
|
CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
|
|
|
|
CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
|
|
|
|
CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
|
|
|
|
CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
|
|
|
|
CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
|
|
|
|
CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
|
|
|
|
CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
|
|
|
|
CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
|
|
|
|
#else
|
|
|
|
CPU_FTRS_GENERIC_32 |
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_8xx
|
|
|
|
CPU_FTRS_8XX |
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_40x
|
|
|
|
CPU_FTRS_40X |
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_44x
|
|
|
|
CPU_FTRS_44X |
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_E200
|
|
|
|
CPU_FTRS_E200 |
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_E500
|
|
|
|
CPU_FTRS_E500 | CPU_FTRS_E500_2 |
|
|
|
|
#endif
|
|
|
|
0,
|
2006-03-22 23:36:59 -07:00
|
|
|
};
|
|
|
|
#endif /* __powerpc64__ */
|
2005-09-23 13:08:58 -06:00
|
|
|
|
2005-12-12 13:45:33 -07:00
|
|
|
#ifdef __powerpc64__
|
2006-03-22 23:36:59 -07:00
|
|
|
#define CPU_FTRS_ALWAYS \
|
|
|
|
(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
|
2006-04-28 17:51:06 -06:00
|
|
|
CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
|
2006-09-06 13:35:57 -06:00
|
|
|
CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
|
2005-12-12 13:45:33 -07:00
|
|
|
#else
|
2006-03-22 23:36:59 -07:00
|
|
|
enum {
|
|
|
|
CPU_FTRS_ALWAYS =
|
2005-09-23 13:08:58 -06:00
|
|
|
#if CLASSIC_PPC
|
|
|
|
CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
|
|
|
|
CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
|
|
|
|
CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
|
|
|
|
CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
|
|
|
|
CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
|
|
|
|
CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
|
|
|
|
CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
|
|
|
|
CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
|
|
|
|
#else
|
|
|
|
CPU_FTRS_GENERIC_32 &
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_8xx
|
|
|
|
CPU_FTRS_8XX &
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_40x
|
|
|
|
CPU_FTRS_40X &
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_44x
|
|
|
|
CPU_FTRS_44X &
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_E200
|
|
|
|
CPU_FTRS_E200 &
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_E500
|
|
|
|
CPU_FTRS_E500 & CPU_FTRS_E500_2 &
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#endif
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CPU_FTRS_POSSIBLE,
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};
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2006-03-22 23:36:59 -07:00
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#endif /* __powerpc64__ */
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2005-09-23 13:08:58 -06:00
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static inline int cpu_has_feature(unsigned long feature)
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|
{
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return (CPU_FTRS_ALWAYS & feature) ||
|
|
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|
(CPU_FTRS_POSSIBLE
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& cur_cpu_spec->cpu_features
|
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|
|
& feature);
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}
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#endif /* !__ASSEMBLY__ */
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#ifdef __ASSEMBLY__
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2006-10-19 19:47:16 -06:00
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#define BEGIN_FTR_SECTION_NESTED(label) label:
|
2006-10-19 19:47:18 -06:00
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#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
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2006-10-19 19:47:16 -06:00
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|
#define END_FTR_SECTION_NESTED(msk, val, label) \
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2006-10-19 19:47:18 -06:00
|
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MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
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2006-10-19 19:47:16 -06:00
|
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|
#define END_FTR_SECTION(msk, val) \
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2006-10-19 19:47:18 -06:00
|
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|
END_FTR_SECTION_NESTED(msk, val, 97)
|
2006-10-19 19:47:16 -06:00
|
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|
2005-09-23 13:08:58 -06:00
|
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|
#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
|
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|
|
#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
|
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|
#endif /* __ASSEMBLY__ */
|
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|
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|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* __ASM_POWERPC_CPUTABLE_H */
|