2013-05-28 03:12:23 -06:00
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/dts-v1/;
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#include "vf610.dtsi"
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/ {
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model = "VF610 Tower Board";
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compatible = "fsl,vf610-twr", "fsl,vf610";
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chosen {
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bootargs = "console=ttyLP1,115200";
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};
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memory {
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reg = <0x80000000 0x8000000>;
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};
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2014-11-02 13:36:44 -07:00
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audio_ext: mclk_osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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2013-05-28 03:12:23 -06:00
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2014-11-02 13:36:44 -07:00
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enet_ext: eth_osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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2013-05-28 03:12:23 -06:00
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};
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2014-02-19 00:42:30 -07:00
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3p3v: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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2014-02-20 22:24:16 -07:00
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reg_vcc_3v3_mcu: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "vcc_3v3_mcu";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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2014-02-19 00:42:30 -07:00
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};
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2014-02-19 00:42:31 -07:00
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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simple-audio-card,widgets =
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"Microphone", "Microphone Jack",
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"Headphone", "Headphone Jack",
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"Speaker", "Speaker Ext",
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"Line", "Line In Jack";
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simple-audio-card,routing =
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"MIC_IN", "Microphone Jack",
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"Microphone Jack", "Mic Bias",
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"LINE_IN", "Line In Jack",
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"Headphone Jack", "HP_OUT",
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"Speaker Ext", "LINE_OUT";
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simple-audio-card,cpu {
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sound-dai = <&sai2>;
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frame-master;
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bitclock-master;
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};
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simple-audio-card,codec {
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sound-dai = <&codec>;
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frame-master;
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bitclock-master;
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};
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};
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2013-05-28 03:12:23 -06:00
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};
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2014-02-20 22:24:16 -07:00
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&adc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc0_ad5>;
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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2014-11-02 13:36:44 -07:00
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&clks {
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clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
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clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
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};
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2013-08-29 21:19:49 -06:00
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&dspi0 {
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bus-num = <0>;
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pinctrl-names = "default";
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2013-12-08 23:42:54 -07:00
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pinctrl-0 = <&pinctrl_dspi0>;
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2013-08-29 21:19:49 -06:00
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status = "okay";
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sflash: at26df081a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at26df081a";
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spi-max-frequency = <16000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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2014-11-02 13:36:46 -07:00
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&edma0 {
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status = "okay";
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};
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2014-03-06 09:40:34 -07:00
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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bus-width = <4>;
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2015-01-16 10:06:15 -07:00
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cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
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2014-03-06 09:40:34 -07:00
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status = "okay";
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};
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2013-05-28 03:12:23 -06:00
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&fec0 {
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phy-mode = "rmii";
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net: fec: fix MDIO bus assignement for dual fec SoC's
On i.MX28, the MDIO bus is shared between the two FEC instances.
The driver makes sure that the second FEC uses the MDIO bus of the
first FEC. This is done conditionally if FEC_QUIRK_ENET_MAC is set.
However, in newer designs, such as Vybrid or i.MX6SX, each FEC MAC
has its own MDIO bus. Simply removing the quirk FEC_QUIRK_ENET_MAC
is not an option since other logic, triggered by this quirk, is
still needed.
Furthermore, there are board designs which use the same MDIO bus
for both PHY's even though the second bus would be available on the
SoC side. Such layout are popular since it saves pins on SoC side.
Due to the above quirk, those boards currently do work fine. The
boards in the mainline tree with such a layout are:
- Freescale Vybrid Tower with TWR-SER2 (vf610-twr.dts)
- Freescale i.MX6 SoloX SDB Board (imx6sx-sdb.dts)
This patch adds a new quirk FEC_QUIRK_SINGLE_MDIO for i.MX28, which
makes sure that the MDIO bus of the first FEC is used in any case.
However, the boards above do have a SoC with a MDIO bus for each FEC
instance. But the PHY's are not connected in a 1:1 configuration. A
proper device tree description is needed to allow the driver to
figure out where to find its PHY. This patch fixes that shortcoming
by adding a MDIO bus child node to the first FEC instance, along
with the two PHY's on that bus, and making use of the phy-handle
property to add a reference to the PHY's.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-01-13 16:20:21 -07:00
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phy-handle = <ðphy0>;
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2013-05-28 03:12:23 -06:00
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pinctrl-names = "default";
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2013-12-08 23:42:54 -07:00
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pinctrl-0 = <&pinctrl_fec0>;
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2013-05-28 03:12:23 -06:00
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status = "okay";
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net: fec: fix MDIO bus assignement for dual fec SoC's
On i.MX28, the MDIO bus is shared between the two FEC instances.
The driver makes sure that the second FEC uses the MDIO bus of the
first FEC. This is done conditionally if FEC_QUIRK_ENET_MAC is set.
However, in newer designs, such as Vybrid or i.MX6SX, each FEC MAC
has its own MDIO bus. Simply removing the quirk FEC_QUIRK_ENET_MAC
is not an option since other logic, triggered by this quirk, is
still needed.
Furthermore, there are board designs which use the same MDIO bus
for both PHY's even though the second bus would be available on the
SoC side. Such layout are popular since it saves pins on SoC side.
Due to the above quirk, those boards currently do work fine. The
boards in the mainline tree with such a layout are:
- Freescale Vybrid Tower with TWR-SER2 (vf610-twr.dts)
- Freescale i.MX6 SoloX SDB Board (imx6sx-sdb.dts)
This patch adds a new quirk FEC_QUIRK_SINGLE_MDIO for i.MX28, which
makes sure that the MDIO bus of the first FEC is used in any case.
However, the boards above do have a SoC with a MDIO bus for each FEC
instance. But the PHY's are not connected in a 1:1 configuration. A
proper device tree description is needed to allow the driver to
figure out where to find its PHY. This patch fixes that shortcoming
by adding a MDIO bus child node to the first FEC instance, along
with the two PHY's on that bus, and making use of the phy-handle
property to add a reference to the PHY's.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-01-13 16:20:21 -07:00
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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2013-05-28 03:12:23 -06:00
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};
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&fec1 {
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phy-mode = "rmii";
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net: fec: fix MDIO bus assignement for dual fec SoC's
On i.MX28, the MDIO bus is shared between the two FEC instances.
The driver makes sure that the second FEC uses the MDIO bus of the
first FEC. This is done conditionally if FEC_QUIRK_ENET_MAC is set.
However, in newer designs, such as Vybrid or i.MX6SX, each FEC MAC
has its own MDIO bus. Simply removing the quirk FEC_QUIRK_ENET_MAC
is not an option since other logic, triggered by this quirk, is
still needed.
Furthermore, there are board designs which use the same MDIO bus
for both PHY's even though the second bus would be available on the
SoC side. Such layout are popular since it saves pins on SoC side.
Due to the above quirk, those boards currently do work fine. The
boards in the mainline tree with such a layout are:
- Freescale Vybrid Tower with TWR-SER2 (vf610-twr.dts)
- Freescale i.MX6 SoloX SDB Board (imx6sx-sdb.dts)
This patch adds a new quirk FEC_QUIRK_SINGLE_MDIO for i.MX28, which
makes sure that the MDIO bus of the first FEC is used in any case.
However, the boards above do have a SoC with a MDIO bus for each FEC
instance. But the PHY's are not connected in a 1:1 configuration. A
proper device tree description is needed to allow the driver to
figure out where to find its PHY. This patch fixes that shortcoming
by adding a MDIO bus child node to the first FEC instance, along
with the two PHY's on that bus, and making use of the phy-handle
property to add a reference to the PHY's.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-01-13 16:20:21 -07:00
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phy-handle = <ðphy1>;
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2013-05-28 03:12:23 -06:00
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pinctrl-names = "default";
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2013-12-08 23:42:54 -07:00
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pinctrl-0 = <&pinctrl_fec1>;
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2013-05-28 03:12:23 -06:00
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status = "okay";
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};
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2013-08-15 23:02:19 -06:00
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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2013-12-08 23:42:54 -07:00
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pinctrl-0 = <&pinctrl_i2c0>;
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2013-08-15 23:02:19 -06:00
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status = "okay";
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2014-02-19 00:42:30 -07:00
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codec: sgtl5000@0a {
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2014-02-19 00:42:31 -07:00
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#sound-dai-cells = <0>;
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2014-02-19 00:42:30 -07:00
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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clocks = <&clks VF610_CLK_SAI2>;
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};
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2013-08-15 23:02:19 -06:00
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};
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2013-12-08 23:42:54 -07:00
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&iomuxc {
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vf610-twr {
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2014-02-20 22:24:16 -07:00
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pinctrl_adc0_ad5: adc0ad5grp {
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fsl,pins = <
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VF610_PAD_PTC30__ADC0_SE5 0xa1
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>;
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};
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2013-12-08 23:42:54 -07:00
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pinctrl_dspi0: dspi0grp {
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fsl,pins = <
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VF610_PAD_PTB19__DSPI0_CS0 0x1182
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VF610_PAD_PTB20__DSPI0_SIN 0x1181
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VF610_PAD_PTB21__DSPI0_SOUT 0x1182
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VF610_PAD_PTB22__DSPI0_SCK 0x1182
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>;
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};
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2014-03-06 09:40:34 -07:00
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pinctrl_esdhc1: esdhc1grp {
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2014-08-05 11:34:00 -06:00
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fsl,pins = <
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2014-03-06 09:40:34 -07:00
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VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
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VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
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VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
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VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
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VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
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VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
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VF610_PAD_PTA7__GPIO_134 0x219d
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>;
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};
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2013-12-08 23:42:54 -07:00
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pinctrl_fec0: fec0grp {
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fsl,pins = <
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VF610_PAD_PTA6__RMII_CLKIN 0x30d1
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VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
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VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
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VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
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VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
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VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
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VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
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VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
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VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
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VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
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VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
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VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
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2015-05-13 21:11:38 -06:00
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VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
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2013-12-08 23:42:54 -07:00
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VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
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VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
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VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
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VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
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VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
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>;
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};
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pinctrl_i2c0: i2c0grp {
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fsl,pins = <
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VF610_PAD_PTB14__I2C0_SCL 0x30d3
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VF610_PAD_PTB15__I2C0_SDA 0x30d3
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>;
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|
|
|
|
};
|
|
|
|
|
|
2014-03-23 20:22:15 -06:00
|
|
|
pinctrl_pwm0: pwm0grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
VF610_PAD_PTB0__FTM0_CH0 0x1582
|
|
|
|
|
VF610_PAD_PTB1__FTM0_CH1 0x1582
|
|
|
|
|
VF610_PAD_PTB2__FTM0_CH2 0x1582
|
|
|
|
|
VF610_PAD_PTB3__FTM0_CH3 0x1582
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-19 00:42:29 -07:00
|
|
|
pinctrl_sai2: sai2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
|
|
|
|
|
VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
|
|
|
|
|
VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
|
|
|
|
|
VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
|
|
|
|
|
VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
|
|
|
|
|
VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
|
|
|
|
|
VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-08 23:42:54 -07:00
|
|
|
pinctrl_uart1: uart1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
VF610_PAD_PTB4__UART1_TX 0x21a2
|
|
|
|
|
VF610_PAD_PTB5__UART1_RX 0x21a1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-08-05 11:34:01 -06:00
|
|
|
|
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
VF610_PAD_PTB6__UART2_TX 0x21a2
|
|
|
|
|
VF610_PAD_PTB7__UART2_RX 0x21a1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2013-12-08 23:42:54 -07:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2014-03-23 20:22:16 -06:00
|
|
|
&pwm0 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_pwm0>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-19 00:42:29 -07:00
|
|
|
&sai2 {
|
2014-02-19 00:42:31 -07:00
|
|
|
#sound-dai-cells = <0>;
|
2014-02-19 00:42:29 -07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_sai2>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2013-05-28 03:12:23 -06:00
|
|
|
&uart1 {
|
|
|
|
|
pinctrl-names = "default";
|
2013-12-08 23:42:54 -07:00
|
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
2013-05-28 03:12:23 -06:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
2014-08-05 11:34:01 -06:00
|
|
|
|
|
|
|
|
&uart2 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2014-08-18 14:07:17 -06:00
|
|
|
|
|
|
|
|
&usbdev0 {
|
|
|
|
|
disable-over-current;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usbh1 {
|
|
|
|
|
disable-over-current;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2014-11-02 13:36:46 -07:00
|
|
|
|
2014-11-04 06:07:09 -07:00
|
|
|
&usbmisc0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usbmisc1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2014-11-02 13:36:46 -07:00
|
|
|
&usbphy0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usbphy1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|