2018-08-21 16:02:17 -06:00
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// SPDX-License-Identifier: GPL-2.0
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2009-10-01 20:22:09 -06:00
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/*
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2017-05-10 03:25:30 -06:00
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* Renesas SDHI
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2009-10-01 20:22:09 -06:00
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*
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2017-05-30 06:50:52 -06:00
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* Copyright (C) 2015-17 Renesas Electronics Corporation
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* Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
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* Copyright (C) 2016-17 Horms Solutions, Simon Horman
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2009-10-01 20:22:09 -06:00
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* Copyright (C) 2009 Magnus Damm
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*
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* Based on "Compaq ASIC3 support":
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*
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* Copyright 2001 Compaq Computer Corporation.
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* Copyright 2004-2005 Phil Blundell
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* Copyright 2007-2008 OpenedHand Ltd.
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*
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* Authors: Phil Blundell <pb@handhelds.org>,
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* Samuel Ortiz <sameo@openedhand.com>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2017-12-12 19:33:00 -07:00
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#include <linux/module.h>
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2013-02-15 08:13:56 -07:00
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#include <linux/of_device.h>
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2009-10-01 20:22:09 -06:00
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#include <linux/platform_device.h>
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2010-02-21 21:37:09 -07:00
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#include <linux/mmc/host.h>
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2018-06-01 05:00:37 -06:00
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#include <linux/mmc/slot-gpio.h>
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2009-10-01 20:22:09 -06:00
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#include <linux/mfd/tmio.h>
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2010-05-19 12:34:16 -06:00
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#include <linux/sh_dma.h>
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2011-06-20 17:00:10 -06:00
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#include <linux/delay.h>
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2016-04-01 09:44:37 -06:00
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/pinctrl-state.h>
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#include <linux/regulator/consumer.h>
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2009-10-01 20:22:09 -06:00
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2017-05-10 03:25:28 -06:00
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#include "renesas_sdhi.h"
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2011-03-14 02:52:33 -06:00
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#include "tmio_mmc.h"
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2018-03-20 15:42:58 -06:00
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#define HOST_MODE 0xe4
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2013-11-20 01:31:13 -07:00
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2016-05-11 06:46:00 -06:00
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#define SDHI_VER_GEN2_SDR50 0x490c
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2017-08-09 13:14:52 -06:00
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#define SDHI_VER_RZ_A1 0x820b
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2016-05-11 06:46:00 -06:00
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/* very old datasheets said 0x490c for SDR104, too. They are wrong! */
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#define SDHI_VER_GEN2_SDR104 0xcb0d
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#define SDHI_VER_GEN3_SD 0xcc10
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#define SDHI_VER_GEN3_SDMMC 0xcd10
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2017-05-10 03:25:29 -06:00
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static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
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2015-01-12 22:00:07 -07:00
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{
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u32 val;
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/*
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* see also
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2017-05-10 03:25:29 -06:00
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* renesas_sdhi_of_data :: dma_buswidth
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2015-01-12 22:00:07 -07:00
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*/
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switch (sd_ctrl_read16(host, CTL_VERSION)) {
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2016-05-11 06:46:00 -06:00
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case SDHI_VER_GEN2_SDR50:
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2015-01-12 22:00:07 -07:00
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val = (width == 32) ? 0x0001 : 0x0000;
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break;
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2016-05-11 06:46:00 -06:00
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case SDHI_VER_GEN2_SDR104:
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2015-01-12 22:00:07 -07:00
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val = (width == 32) ? 0x0000 : 0x0001;
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break;
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2016-05-11 06:46:00 -06:00
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case SDHI_VER_GEN3_SD:
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case SDHI_VER_GEN3_SDMMC:
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2016-02-15 08:01:48 -07:00
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if (width == 64)
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val = 0x0000;
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else if (width == 32)
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val = 0x0101;
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else
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val = 0x0001;
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break;
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2015-01-12 22:00:07 -07:00
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default:
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/* nothing to do */
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return;
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}
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2018-03-20 15:42:58 -06:00
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sd_ctrl_write16(host, HOST_MODE, val);
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2015-01-12 22:00:07 -07:00
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}
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2017-05-10 03:25:29 -06:00
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static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
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2012-06-20 11:10:32 -06:00
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{
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2016-04-01 09:44:31 -06:00
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struct mmc_host *mmc = host->mmc;
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2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv = host_to_priv(host);
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2013-10-28 16:49:25 -06:00
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int ret = clk_prepare_enable(priv->clk);
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2017-06-16 10:11:04 -06:00
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2012-06-20 11:10:32 -06:00
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if (ret < 0)
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return ret;
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2017-01-25 13:28:08 -07:00
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ret = clk_prepare_enable(priv->clk_cd);
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if (ret < 0) {
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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2016-04-01 09:44:32 -06:00
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/*
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* The clock driver may not know what maximum frequency
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* actually works, so it should be set with the max-frequency
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* property which will already have been read to f_max. If it
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* was missing, assume the current frequency is the maximum.
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*/
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if (!mmc->f_max)
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mmc->f_max = clk_get_rate(priv->clk);
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/*
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* Minimum frequency is the minimum input clock frequency
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* divided by our maximum divider.
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*/
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mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
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2015-01-12 22:00:07 -07:00
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/* enable 16bit data access on SDBUF as default */
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2017-05-10 03:25:29 -06:00
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renesas_sdhi_sdbuf_width(host, 16);
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2015-01-12 22:00:07 -07:00
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2012-06-20 11:10:32 -06:00
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return 0;
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}
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2017-05-10 03:25:29 -06:00
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static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
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2017-06-16 10:11:04 -06:00
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unsigned int new_clock)
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2016-04-01 09:44:32 -06:00
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{
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2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv = host_to_priv(host);
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2016-05-02 14:25:39 -06:00
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unsigned int freq, diff, best_freq = 0, diff_min = ~0;
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2016-05-02 14:25:42 -06:00
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int i, ret;
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2016-04-01 09:44:32 -06:00
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2017-05-28 03:30:47 -06:00
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/* tested only on R-Car Gen2+ currently; may work for others */
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2016-05-02 14:25:41 -06:00
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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return clk_get_rate(priv->clk);
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2016-04-01 09:44:32 -06:00
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/*
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* We want the bus clock to be as close as possible to, but no
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* greater than, new_clock. As we can divide by 1 << i for
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* any i in [0, 9] we want the input clock to be as close as
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* possible, but no greater than, new_clock << i.
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*/
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for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
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freq = clk_round_rate(priv->clk, new_clock << i);
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if (freq > (new_clock << i)) {
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/* Too fast; look for a slightly slower option */
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freq = clk_round_rate(priv->clk,
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(new_clock << i) / 4 * 3);
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if (freq > (new_clock << i))
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continue;
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}
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diff = new_clock - (freq >> i);
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if (diff <= diff_min) {
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best_freq = freq;
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diff_min = diff;
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}
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}
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2016-05-02 14:25:42 -06:00
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ret = clk_set_rate(priv->clk, best_freq);
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2016-04-01 09:44:32 -06:00
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2016-05-02 14:25:42 -06:00
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return ret == 0 ? best_freq : clk_get_rate(priv->clk);
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2016-04-01 09:44:32 -06:00
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}
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2018-08-22 22:44:19 -06:00
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static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
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unsigned int new_clock)
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2018-08-22 22:44:16 -06:00
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{
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2018-08-22 22:44:19 -06:00
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u32 clk = 0, clock;
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2018-08-22 22:44:16 -06:00
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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2018-08-22 22:44:19 -06:00
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if (new_clock == 0)
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goto out;
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2018-08-22 22:44:16 -06:00
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/*
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* Both HS400 and HS200/SD104 set 200MHz, but some devices need to
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* set 400MHz to distinguish the CPG settings in HS400.
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*/
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if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
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host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
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new_clock == 200000000)
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new_clock = 400000000;
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clock = renesas_sdhi_clk_update(host, new_clock) / 512;
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for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
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clock <<= 1;
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/* 1/1 clock is option */
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if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
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if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
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clk |= 0xff;
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else
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clk &= ~0xff;
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}
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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usleep_range(10000, 11000);
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2018-08-22 22:44:19 -06:00
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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out:
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/* HW engineers overrode docs: no sleep needed on R-Car2+ */
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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usleep_range(10000, 11000);
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2018-08-22 22:44:16 -06:00
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}
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2017-05-10 03:25:29 -06:00
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static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
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2012-06-20 11:10:32 -06:00
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{
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2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv = host_to_priv(host);
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2016-04-01 09:44:31 -06:00
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2013-10-28 16:49:25 -06:00
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clk_disable_unprepare(priv->clk);
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2017-01-25 13:28:08 -07:00
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clk_disable_unprepare(priv->clk_cd);
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2012-06-20 11:10:32 -06:00
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}
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2017-05-10 03:25:29 -06:00
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static int renesas_sdhi_card_busy(struct mmc_host *mmc)
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2016-08-24 03:34:37 -06:00
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{
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struct tmio_mmc_host *host = mmc_priv(mmc);
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2017-06-16 10:11:04 -06:00
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return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
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TMIO_STAT_DAT0);
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2016-08-24 03:34:37 -06:00
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}
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2017-05-10 03:25:29 -06:00
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static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
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2017-06-16 10:11:04 -06:00
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struct mmc_ios *ios)
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2016-04-01 09:44:37 -06:00
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{
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struct tmio_mmc_host *host = mmc_priv(mmc);
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2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv = host_to_priv(host);
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2016-04-01 09:44:37 -06:00
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struct pinctrl_state *pin_state;
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int ret;
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switch (ios->signal_voltage) {
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case MMC_SIGNAL_VOLTAGE_330:
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pin_state = priv->pins_default;
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break;
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case MMC_SIGNAL_VOLTAGE_180:
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pin_state = priv->pins_uhs;
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break;
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default:
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return -EINVAL;
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}
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/*
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* If anything is missing, assume signal voltage is fixed at
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* 3.3V and succeed/fail accordingly.
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*/
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if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
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return ios->signal_voltage ==
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MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
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ret = mmc_regulator_set_vqmmc(host->mmc, ios);
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if (ret)
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return ret;
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2016-04-26 09:55:27 -06:00
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return pinctrl_select_state(priv->pinctrl, pin_state);
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2016-04-01 09:44:37 -06:00
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}
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2016-11-03 08:16:04 -06:00
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/* SCC registers */
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#define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
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#define SH_MOBILE_SDHI_SCC_TAPSET 0x002
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#define SH_MOBILE_SDHI_SCC_DT2FF 0x004
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#define SH_MOBILE_SDHI_SCC_CKSEL 0x006
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#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
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#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
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2018-06-18 06:57:51 -06:00
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#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
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2016-11-03 08:16:04 -06:00
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/* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
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#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
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#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
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#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
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/* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
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#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
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/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
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#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
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/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
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#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
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2018-06-18 06:57:51 -06:00
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/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
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#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
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#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
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2016-11-03 08:16:04 -06:00
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static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
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2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv, int addr)
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2016-11-03 08:16:04 -06:00
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{
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return readl(priv->scc_ctl + (addr << host->bus_shift));
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}
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static inline void sd_scc_write32(struct tmio_mmc_host *host,
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2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv,
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2016-11-03 08:16:04 -06:00
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int addr, u32 val)
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{
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writel(val, priv->scc_ctl + (addr << host->bus_shift));
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}
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2017-05-10 03:25:29 -06:00
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static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
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2016-11-03 08:16:04 -06:00
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{
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2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv;
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2016-11-03 08:16:04 -06:00
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priv = host_to_priv(host);
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/* Initialize SCC */
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sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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2018-06-18 06:57:51 -06:00
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/* set sampling clock selection range */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
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0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
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2016-11-03 08:16:04 -06:00
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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2017-11-24 09:24:49 -07:00
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
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2016-11-03 08:16:04 -06:00
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2018-06-18 06:57:51 -06:00
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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2016-11-03 08:16:04 -06:00
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/* Read TAPNUM */
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return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
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}
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2017-05-10 03:25:29 -06:00
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static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
|
2017-06-16 10:11:04 -06:00
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unsigned long tap)
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2016-11-03 08:16:04 -06:00
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{
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2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv = host_to_priv(host);
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2016-11-03 08:16:04 -06:00
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/* Set sampling clock position */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
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}
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2018-06-18 06:57:51 -06:00
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static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* Set HS400 mode */
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sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
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sd_ctrl_read16(host, CTL_SDIF_MODE));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
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(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
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SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
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/* Set the sampling clock selection range of HS400 mode */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
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0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
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if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400)
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
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host->tap_set / 2);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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}
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static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
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struct renesas_sdhi *priv)
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{
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
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sd_scc_read32(host, priv,
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SH_MOBILE_SDHI_SCC_CKSEL));
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}
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static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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renesas_sdhi_reset_scc(host, priv);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
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sd_scc_read32(host, priv,
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SH_MOBILE_SDHI_SCC_DTCNTL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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}
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static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
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struct renesas_sdhi *priv)
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{
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* Reset HS400 mode */
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sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
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sd_ctrl_read16(host, CTL_SDIF_MODE));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
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~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
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SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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}
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static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host)
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{
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renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
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}
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|
2016-11-03 08:16:04 -06:00
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#define SH_MOBILE_SDHI_MAX_TAP 3
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|
2017-05-10 03:25:29 -06:00
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static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
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2016-11-03 08:16:04 -06:00
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{
|
2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv = host_to_priv(host);
|
2016-11-03 08:16:04 -06:00
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unsigned long tap_cnt; /* counter of tuning success */
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unsigned long tap_start;/* start position of tuning success */
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unsigned long tap_end; /* end position of tuning success */
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unsigned long ntap; /* temporary counter of tuning success */
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unsigned long i;
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/* Clear SCC_RVSREQ */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
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|
2018-07-24 08:51:38 -06:00
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/*
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* When tuning CMD19 is issued twice for each tap, merge the
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* result requiring the tap to be good in both runs before
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* considering it for tuning selection.
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*/
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for (i = 0; i < host->tap_num * 2; i++) {
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int offset = host->tap_num * (i < host->tap_num ? 1 : -1);
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if (!test_bit(i, host->taps))
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clear_bit(i + offset, host->taps);
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}
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2016-11-03 08:16:04 -06:00
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/*
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* Find the longest consecutive run of successful probes. If that
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* is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
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* center index as the tap.
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*/
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tap_cnt = 0;
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ntap = 0;
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tap_start = 0;
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tap_end = 0;
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for (i = 0; i < host->tap_num * 2; i++) {
|
2017-06-16 10:11:04 -06:00
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if (test_bit(i, host->taps)) {
|
2016-11-03 08:16:04 -06:00
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ntap++;
|
2017-06-16 10:11:04 -06:00
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} else {
|
2016-11-03 08:16:04 -06:00
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if (ntap > tap_cnt) {
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tap_start = i - ntap;
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tap_end = i - 1;
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tap_cnt = ntap;
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}
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ntap = 0;
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}
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}
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if (ntap > tap_cnt) {
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tap_start = i - ntap;
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tap_end = i - 1;
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tap_cnt = ntap;
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}
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if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
|
2018-06-18 06:57:51 -06:00
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host->tap_set = (tap_start + tap_end) / 2 % host->tap_num;
|
2016-11-03 08:16:04 -06:00
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else
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return -EIO;
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/* Set SCC */
|
2018-06-18 06:57:51 -06:00
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set);
|
2016-11-03 08:16:04 -06:00
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/* Enable auto re-tuning */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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return 0;
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}
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|
2017-05-10 03:25:29 -06:00
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static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
|
2016-11-03 08:16:04 -06:00
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{
|
2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv = host_to_priv(host);
|
2018-08-29 17:32:06 -06:00
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bool use_4tap = host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400;
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/*
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* Skip checking SCC errors when running on 4 taps in HS400 mode as
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* any retuning would still result in the same 4 taps being used.
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*/
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if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
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!(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
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!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
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return false;
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if (mmc_doing_retune(host->mmc))
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return false;
|
2016-11-03 08:16:04 -06:00
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/* Check SCC error */
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if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
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SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
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SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
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/* Clear SCC error */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
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return true;
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}
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return false;
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}
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|
2017-05-10 03:25:29 -06:00
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static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
|
2016-11-03 08:16:04 -06:00
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{
|
2017-05-10 03:25:29 -06:00
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struct renesas_sdhi *priv;
|
2016-11-03 08:16:04 -06:00
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priv = host_to_priv(host);
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|
2018-06-18 06:57:51 -06:00
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renesas_sdhi_reset_scc(host, priv);
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renesas_sdhi_reset_hs400_mode(host, priv);
|
2016-11-03 08:16:04 -06:00
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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|
|
|
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
|
|
|
|
~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
|
|
|
|
}
|
|
|
|
|
2017-06-28 09:21:56 -06:00
|
|
|
static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
|
2011-06-20 17:00:10 -06:00
|
|
|
{
|
|
|
|
int timeout = 1000;
|
2017-06-28 09:21:56 -06:00
|
|
|
/* CBSY is set when busy, SCLKDIVEN is cleared when busy */
|
|
|
|
u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
|
2011-06-20 17:00:10 -06:00
|
|
|
|
2017-06-28 09:21:56 -06:00
|
|
|
while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
|
|
|
|
& bit) == wait_state)
|
2011-06-20 17:00:10 -06:00
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
if (!timeout) {
|
2015-01-12 21:57:22 -07:00
|
|
|
dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
|
2011-06-20 17:00:10 -06:00
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-10 03:25:29 -06:00
|
|
|
static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
|
2011-06-20 17:00:10 -06:00
|
|
|
{
|
2017-06-28 09:21:56 -06:00
|
|
|
u32 bit = TMIO_STAT_SCLKDIVEN;
|
|
|
|
|
2017-06-16 10:11:04 -06:00
|
|
|
switch (addr) {
|
2011-06-20 17:00:10 -06:00
|
|
|
case CTL_SD_CMD:
|
|
|
|
case CTL_STOP_INTERNAL_ACTION:
|
|
|
|
case CTL_XFER_BLK_COUNT:
|
|
|
|
case CTL_SD_XFER_LEN:
|
|
|
|
case CTL_SD_MEM_CARD_OPT:
|
|
|
|
case CTL_TRANSACTION_CTL:
|
|
|
|
case CTL_DMA_ENABLE:
|
2018-03-20 15:42:58 -06:00
|
|
|
case HOST_MODE:
|
2017-08-09 13:00:41 -06:00
|
|
|
if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
|
2017-06-28 09:21:56 -06:00
|
|
|
bit = TMIO_STAT_CMD_BUSY;
|
|
|
|
/* fallthrough */
|
|
|
|
case CTL_SD_CARD_CLK_CTL:
|
|
|
|
return renesas_sdhi_wait_idle(host, bit);
|
2011-06-20 17:00:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-10 03:25:29 -06:00
|
|
|
static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
|
2017-06-16 10:11:04 -06:00
|
|
|
unsigned int direction, int blk_size)
|
2014-09-09 00:45:46 -06:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* In Renesas controllers, when performing a
|
|
|
|
* multiple block read of one or two blocks,
|
|
|
|
* depending on the timing with which the
|
|
|
|
* response register is read, the response
|
|
|
|
* value may not be read properly.
|
|
|
|
* Use single block read for this HW bug
|
|
|
|
*/
|
|
|
|
if ((direction == MMC_DATA_READ) &&
|
|
|
|
blk_size == 2)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return blk_size;
|
|
|
|
}
|
|
|
|
|
2017-05-10 03:25:29 -06:00
|
|
|
static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
|
2015-01-12 21:59:56 -07:00
|
|
|
{
|
2017-08-09 12:29:26 -06:00
|
|
|
/* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
|
|
|
|
int width = (host->bus_shift == 2) ? 64 : 32;
|
2015-01-12 22:00:07 -07:00
|
|
|
|
2017-08-09 12:29:26 -06:00
|
|
|
sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
|
|
|
|
renesas_sdhi_sdbuf_width(host, enable ? width : 16);
|
2015-01-12 21:59:56 -07:00
|
|
|
}
|
|
|
|
|
2017-05-10 03:25:30 -06:00
|
|
|
int renesas_sdhi_probe(struct platform_device *pdev,
|
|
|
|
const struct tmio_mmc_dma_ops *dma_ops)
|
2009-10-01 20:22:09 -06:00
|
|
|
{
|
2015-02-23 19:06:43 -07:00
|
|
|
struct tmio_mmc_data *mmd = pdev->dev.platform_data;
|
2017-06-16 10:11:04 -06:00
|
|
|
const struct renesas_sdhi_of_data *of_data;
|
|
|
|
struct tmio_mmc_data *mmc_data;
|
|
|
|
struct tmio_mmc_dma *dma_priv;
|
2011-03-14 02:52:33 -06:00
|
|
|
struct tmio_mmc_host *host;
|
2017-06-16 10:11:04 -06:00
|
|
|
struct renesas_sdhi *priv;
|
2013-11-20 01:30:55 -07:00
|
|
|
struct resource *res;
|
2016-11-03 08:16:04 -06:00
|
|
|
int irq, ret, i;
|
2017-06-16 10:11:04 -06:00
|
|
|
|
|
|
|
of_data = of_device_get_match_data(&pdev->dev);
|
2009-10-01 20:22:09 -06:00
|
|
|
|
2013-11-20 01:30:55 -07:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-06-16 10:11:04 -06:00
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
|
|
|
|
GFP_KERNEL);
|
2016-01-19 03:42:22 -07:00
|
|
|
if (!priv)
|
2009-10-01 20:22:09 -06:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-05-19 12:34:16 -06:00
|
|
|
mmc_data = &priv->mmc_data;
|
2013-04-26 09:47:19 -06:00
|
|
|
dma_priv = &priv->dma_priv;
|
2010-05-19 12:34:16 -06:00
|
|
|
|
2013-02-15 08:13:58 -07:00
|
|
|
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
2009-10-01 20:22:09 -06:00
|
|
|
if (IS_ERR(priv->clk)) {
|
|
|
|
ret = PTR_ERR(priv->clk);
|
2012-11-28 02:24:21 -07:00
|
|
|
dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
|
2017-11-24 09:24:38 -07:00
|
|
|
return ret;
|
2009-10-01 20:22:09 -06:00
|
|
|
}
|
|
|
|
|
2017-01-25 13:28:08 -07:00
|
|
|
/*
|
|
|
|
* Some controllers provide a 2nd clock just to run the internal card
|
|
|
|
* detection logic. Unfortunately, the existing driver architecture does
|
|
|
|
* not support a separation of clocks for runtime PM usage. When
|
|
|
|
* native hotplug is used, the tmio driver assumes that the core
|
|
|
|
* must continue to run for card detect to stay active, so we cannot
|
|
|
|
* disable it.
|
|
|
|
* Additionally, it is prohibited to supply a clock to the core but not
|
|
|
|
* to the card detect circuit. That leaves us with if separate clocks
|
|
|
|
* are presented, we must treat them both as virtually 1 clock.
|
|
|
|
*/
|
|
|
|
priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
|
|
|
|
if (IS_ERR(priv->clk_cd))
|
|
|
|
priv->clk_cd = NULL;
|
|
|
|
|
2016-04-01 09:44:37 -06:00
|
|
|
priv->pinctrl = devm_pinctrl_get(&pdev->dev);
|
|
|
|
if (!IS_ERR(priv->pinctrl)) {
|
|
|
|
priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
|
|
|
|
PINCTRL_STATE_DEFAULT);
|
|
|
|
priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
|
|
|
|
"state_uhs");
|
|
|
|
}
|
|
|
|
|
2018-01-17 09:28:02 -07:00
|
|
|
host = tmio_mmc_host_alloc(pdev, mmc_data);
|
2018-01-17 09:28:01 -07:00
|
|
|
if (IS_ERR(host))
|
|
|
|
return PTR_ERR(host);
|
2015-01-12 21:57:22 -07:00
|
|
|
|
2016-12-12 12:51:20 -07:00
|
|
|
if (of_data) {
|
2016-02-15 08:01:48 -07:00
|
|
|
mmc_data->flags |= of_data->tmio_flags;
|
2016-09-12 08:15:05 -06:00
|
|
|
mmc_data->ocr_mask = of_data->tmio_ocr_mask;
|
2016-02-15 08:01:48 -07:00
|
|
|
mmc_data->capabilities |= of_data->capabilities;
|
|
|
|
mmc_data->capabilities2 |= of_data->capabilities2;
|
|
|
|
mmc_data->dma_rx_offset = of_data->dma_rx_offset;
|
2017-06-21 08:00:27 -06:00
|
|
|
mmc_data->max_blk_count = of_data->max_blk_count;
|
|
|
|
mmc_data->max_segs = of_data->max_segs;
|
2016-02-15 08:01:48 -07:00
|
|
|
dma_priv->dma_buswidth = of_data->dma_buswidth;
|
|
|
|
host->bus_shift = of_data->bus_shift;
|
|
|
|
}
|
|
|
|
|
2017-05-10 03:25:29 -06:00
|
|
|
host->write16_hook = renesas_sdhi_write16_hook;
|
|
|
|
host->clk_enable = renesas_sdhi_clk_enable;
|
|
|
|
host->clk_disable = renesas_sdhi_clk_disable;
|
2018-08-22 22:44:16 -06:00
|
|
|
host->set_clock = renesas_sdhi_set_clock;
|
2017-05-10 03:25:29 -06:00
|
|
|
host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
|
2018-01-17 09:28:04 -07:00
|
|
|
host->dma_ops = dma_ops;
|
2016-08-24 03:34:38 -06:00
|
|
|
|
2018-06-01 05:00:37 -06:00
|
|
|
/* For some SoC, we disable internal WP. GPIO may override this */
|
|
|
|
if (mmc_can_gpio_ro(host->mmc))
|
|
|
|
mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
|
|
|
|
|
2016-08-24 03:34:38 -06:00
|
|
|
/* SDR speeds are only available on Gen2+ */
|
|
|
|
if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
|
|
|
|
/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
|
2017-11-24 09:24:42 -07:00
|
|
|
host->ops.card_busy = renesas_sdhi_card_busy;
|
|
|
|
host->ops.start_signal_voltage_switch =
|
2017-05-10 03:25:29 -06:00
|
|
|
renesas_sdhi_start_signal_voltage_switch;
|
2016-08-24 03:34:38 -06:00
|
|
|
}
|
2016-02-15 08:01:48 -07:00
|
|
|
|
|
|
|
/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
|
|
|
|
if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
|
2015-01-12 21:59:33 -07:00
|
|
|
host->bus_shift = 1;
|
2015-01-12 21:57:33 -07:00
|
|
|
|
2015-02-23 19:07:07 -07:00
|
|
|
if (mmd)
|
2015-02-23 19:06:43 -07:00
|
|
|
*mmc_data = *mmd;
|
2015-02-23 19:07:07 -07:00
|
|
|
|
2013-04-26 09:47:19 -06:00
|
|
|
dma_priv->filter = shdma_chan_filter;
|
2017-05-10 03:25:29 -06:00
|
|
|
dma_priv->enable = renesas_sdhi_enable_dma;
|
2013-04-26 09:47:19 -06:00
|
|
|
|
2015-01-12 21:58:46 -07:00
|
|
|
mmc_data->alignment_shift = 1; /* 2-byte alignment */
|
2015-02-23 19:06:43 -07:00
|
|
|
mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
|
2015-01-12 21:58:46 -07:00
|
|
|
|
2010-08-30 04:50:19 -06:00
|
|
|
/*
|
|
|
|
* All SDHI blocks support 2-byte and larger block sizes in 4-bit
|
|
|
|
* bus width mode.
|
|
|
|
*/
|
|
|
|
mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
|
|
|
|
|
2010-12-28 15:22:32 -07:00
|
|
|
/*
|
|
|
|
* All SDHI blocks support SDIO IRQ signalling.
|
|
|
|
*/
|
|
|
|
mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
|
|
|
|
|
2017-06-16 10:11:04 -06:00
|
|
|
/* All SDHI have CMD12 control bit */
|
2014-08-24 21:00:25 -06:00
|
|
|
mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
|
|
|
|
|
2017-01-19 13:07:17 -07:00
|
|
|
/* All SDHI have SDIO status bits which must be 1 */
|
|
|
|
mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
|
2014-08-24 21:00:52 -06:00
|
|
|
|
2018-01-17 09:28:02 -07:00
|
|
|
ret = renesas_sdhi_clk_enable(host);
|
|
|
|
if (ret)
|
2015-01-12 21:57:22 -07:00
|
|
|
goto efree;
|
2009-10-01 20:22:09 -06:00
|
|
|
|
2018-01-17 09:28:04 -07:00
|
|
|
ret = tmio_mmc_host_probe(host);
|
2018-01-17 09:28:02 -07:00
|
|
|
if (ret < 0)
|
|
|
|
goto edisclk;
|
|
|
|
|
2017-08-09 13:00:41 -06:00
|
|
|
/* One Gen2 SDHI incarnation does NOT have a CBSY bit */
|
|
|
|
if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50)
|
|
|
|
mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
|
|
|
|
|
2016-12-12 12:51:22 -07:00
|
|
|
/* Enable tuning iff we have an SCC and a supported mode */
|
2016-12-12 12:51:26 -07:00
|
|
|
if (of_data && of_data->scc_offset &&
|
|
|
|
(host->mmc->caps & MMC_CAP_UHS_SDR104 ||
|
2018-06-18 06:57:51 -06:00
|
|
|
host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
|
|
|
|
MMC_CAP2_HS400_1_8V))) {
|
2017-05-10 03:25:29 -06:00
|
|
|
const struct renesas_sdhi_scc *taps = of_data->taps;
|
2016-12-12 12:51:21 -07:00
|
|
|
bool hit = false;
|
|
|
|
|
2016-11-03 08:16:04 -06:00
|
|
|
host->mmc->caps |= MMC_CAP_HW_RESET;
|
|
|
|
|
2016-12-12 12:51:21 -07:00
|
|
|
for (i = 0; i < of_data->taps_num; i++) {
|
|
|
|
if (taps[i].clk_rate == 0 ||
|
|
|
|
taps[i].clk_rate == host->mmc->f_max) {
|
2017-11-24 09:24:49 -07:00
|
|
|
priv->scc_tappos = taps->tap;
|
2016-12-12 12:51:21 -07:00
|
|
|
hit = true;
|
|
|
|
break;
|
2016-11-03 08:16:04 -06:00
|
|
|
}
|
2016-12-12 12:51:21 -07:00
|
|
|
}
|
2016-11-03 08:16:04 -06:00
|
|
|
|
2016-12-12 12:51:21 -07:00
|
|
|
if (!hit)
|
|
|
|
dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
|
2016-11-03 08:16:04 -06:00
|
|
|
|
2016-12-12 12:51:21 -07:00
|
|
|
priv->scc_ctl = host->ctl + of_data->scc_offset;
|
2017-05-10 03:25:29 -06:00
|
|
|
host->init_tuning = renesas_sdhi_init_tuning;
|
|
|
|
host->prepare_tuning = renesas_sdhi_prepare_tuning;
|
|
|
|
host->select_tuning = renesas_sdhi_select_tuning;
|
|
|
|
host->check_scc_error = renesas_sdhi_check_scc_error;
|
|
|
|
host->hw_reset = renesas_sdhi_hw_reset;
|
2018-06-18 06:57:51 -06:00
|
|
|
host->prepare_hs400_tuning =
|
|
|
|
renesas_sdhi_prepare_hs400_tuning;
|
|
|
|
host->hs400_downgrade = renesas_sdhi_disable_scc;
|
|
|
|
host->hs400_complete = renesas_sdhi_hs400_complete;
|
2016-11-03 08:16:04 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
i = 0;
|
2016-04-26 09:55:23 -06:00
|
|
|
while (1) {
|
|
|
|
irq = platform_get_irq(pdev, i);
|
|
|
|
if (irq < 0)
|
|
|
|
break;
|
|
|
|
i++;
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
|
2017-06-16 10:11:04 -06:00
|
|
|
dev_name(&pdev->dev), host);
|
2011-08-26 02:42:39 -06:00
|
|
|
if (ret)
|
2013-02-15 08:13:58 -07:00
|
|
|
goto eirq;
|
2011-08-26 02:42:39 -06:00
|
|
|
}
|
|
|
|
|
2016-04-26 09:55:23 -06:00
|
|
|
/* There must be at least one IRQ source */
|
|
|
|
if (!i) {
|
2011-08-26 02:42:39 -06:00
|
|
|
ret = irq;
|
2013-02-15 08:13:58 -07:00
|
|
|
goto eirq;
|
2011-08-26 02:42:39 -06:00
|
|
|
}
|
|
|
|
|
2016-04-01 09:44:32 -06:00
|
|
|
dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
|
2011-05-06 05:02:41 -06:00
|
|
|
mmc_hostname(host->mmc), (unsigned long)
|
2012-02-09 14:57:10 -07:00
|
|
|
(platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
|
2012-11-28 02:24:13 -07:00
|
|
|
host->mmc->f_max / 1000000);
|
2009-10-01 20:22:09 -06:00
|
|
|
|
2011-03-14 02:52:33 -06:00
|
|
|
return ret;
|
2009-10-01 20:22:09 -06:00
|
|
|
|
2013-02-15 08:13:58 -07:00
|
|
|
eirq:
|
2011-05-06 05:02:33 -06:00
|
|
|
tmio_mmc_host_remove(host);
|
2018-01-17 09:28:02 -07:00
|
|
|
edisclk:
|
|
|
|
renesas_sdhi_clk_disable(host);
|
2015-01-12 21:57:22 -07:00
|
|
|
efree:
|
|
|
|
tmio_mmc_host_free(host);
|
2017-11-24 09:24:38 -07:00
|
|
|
|
2009-10-01 20:22:09 -06:00
|
|
|
return ret;
|
|
|
|
}
|
2017-05-10 03:25:30 -06:00
|
|
|
EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
|
2009-10-01 20:22:09 -06:00
|
|
|
|
2017-05-10 03:25:30 -06:00
|
|
|
int renesas_sdhi_remove(struct platform_device *pdev)
|
2009-10-01 20:22:09 -06:00
|
|
|
{
|
2017-11-24 09:24:39 -07:00
|
|
|
struct tmio_mmc_host *host = platform_get_drvdata(pdev);
|
2011-05-06 05:02:45 -06:00
|
|
|
|
2011-05-27 08:54:05 -06:00
|
|
|
tmio_mmc_host_remove(host);
|
2018-01-17 09:28:02 -07:00
|
|
|
renesas_sdhi_clk_disable(host);
|
2011-05-27 08:54:05 -06:00
|
|
|
|
2009-10-01 20:22:09 -06:00
|
|
|
return 0;
|
|
|
|
}
|
2017-05-10 03:25:30 -06:00
|
|
|
EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
|
2017-12-12 19:33:00 -07:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|