2015-05-20 04:48:26 -06:00
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/log2.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <linux/device.h>
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#include "kfd_pm4_headers.h"
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#include "kfd_pm4_headers_diq.h"
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#include "kfd_kernel_queue.h"
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#include "kfd_priv.h"
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#include "kfd_pm4_opcodes.h"
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#include "cik_regs.h"
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#include "kfd_dbgmgr.h"
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#include "kfd_dbgdev.h"
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#include "kfd_device_queue_manager.h"
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#include "../../radeon/cik_reg.h"
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static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev)
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{
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BUG_ON(!dev || !dev->kfd2kgd);
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dev->kfd2kgd->address_watch_disable(dev->kgd);
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}
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2015-05-20 04:58:12 -06:00
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static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
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unsigned int pasid, uint64_t vmid0_address,
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uint32_t *packet_buff, size_t size_in_bytes)
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{
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struct pm4__release_mem *rm_packet;
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struct pm4__indirect_buffer_pasid *ib_packet;
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struct kfd_mem_obj *mem_obj;
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size_t pq_packets_size_in_bytes;
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union ULARGE_INTEGER *largep;
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union ULARGE_INTEGER addr;
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struct kernel_queue *kq;
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uint64_t *rm_state;
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unsigned int *ib_packet_buff;
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int status;
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BUG_ON(!dbgdev || !dbgdev->kq || !packet_buff || !size_in_bytes);
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kq = dbgdev->kq;
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pq_packets_size_in_bytes = sizeof(struct pm4__release_mem) +
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sizeof(struct pm4__indirect_buffer_pasid);
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/*
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* We acquire a buffer from DIQ
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* The receive packet buff will be sitting on the Indirect Buffer
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* and in the PQ we put the IB packet + sync packet(s).
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*/
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status = kq->ops.acquire_packet_buffer(kq,
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pq_packets_size_in_bytes / sizeof(uint32_t),
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&ib_packet_buff);
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if (status != 0) {
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pr_err("amdkfd: acquire_packet_buffer failed\n");
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return status;
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}
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memset(ib_packet_buff, 0, pq_packets_size_in_bytes);
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ib_packet = (struct pm4__indirect_buffer_pasid *) (ib_packet_buff);
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ib_packet->header.count = 3;
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ib_packet->header.opcode = IT_INDIRECT_BUFFER_PASID;
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ib_packet->header.type = PM4_TYPE_3;
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largep = (union ULARGE_INTEGER *) &vmid0_address;
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ib_packet->bitfields2.ib_base_lo = largep->u.low_part >> 2;
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ib_packet->bitfields3.ib_base_hi = largep->u.high_part;
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ib_packet->control = (1 << 23) | (1 << 31) |
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((size_in_bytes / sizeof(uint32_t)) & 0xfffff);
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ib_packet->bitfields5.pasid = pasid;
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/*
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* for now we use release mem for GPU-CPU synchronization
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* Consider WaitRegMem + WriteData as a better alternative
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* we get a GART allocations ( gpu/cpu mapping),
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* for the sync variable, and wait until:
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* (a) Sync with HW
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* (b) Sync var is written by CP to mem.
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*/
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rm_packet = (struct pm4__release_mem *) (ib_packet_buff +
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(sizeof(struct pm4__indirect_buffer_pasid) /
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sizeof(unsigned int)));
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status = kfd_gtt_sa_allocate(dbgdev->dev, sizeof(uint64_t),
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&mem_obj);
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if (status != 0) {
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pr_err("amdkfd: Failed to allocate GART memory\n");
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kq->ops.rollback_packet(kq);
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return status;
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}
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rm_state = (uint64_t *) mem_obj->cpu_ptr;
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*rm_state = QUEUESTATE__ACTIVE_COMPLETION_PENDING;
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rm_packet->header.opcode = IT_RELEASE_MEM;
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rm_packet->header.type = PM4_TYPE_3;
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rm_packet->header.count = sizeof(struct pm4__release_mem) /
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sizeof(unsigned int) - 2;
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rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
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rm_packet->bitfields2.event_index =
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event_index___release_mem__end_of_pipe;
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rm_packet->bitfields2.cache_policy = cache_policy___release_mem__lru;
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rm_packet->bitfields2.atc = 0;
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rm_packet->bitfields2.tc_wb_action_ena = 1;
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addr.quad_part = mem_obj->gpu_addr;
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rm_packet->bitfields4.address_lo_32b = addr.u.low_part >> 2;
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rm_packet->address_hi = addr.u.high_part;
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rm_packet->bitfields3.data_sel =
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data_sel___release_mem__send_64_bit_data;
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rm_packet->bitfields3.int_sel =
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int_sel___release_mem__send_data_after_write_confirm;
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rm_packet->bitfields3.dst_sel =
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dst_sel___release_mem__memory_controller;
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rm_packet->data_lo = QUEUESTATE__ACTIVE;
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kq->ops.submit_packet(kq);
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/* Wait till CP writes sync code: */
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status = amdkfd_fence_wait_timeout(
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(unsigned int *) rm_state,
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QUEUESTATE__ACTIVE, 1500);
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kfd_gtt_sa_free(dbgdev->dev, mem_obj);
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return status;
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}
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2015-05-20 04:48:26 -06:00
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static int dbgdev_register_nodiq(struct kfd_dbgdev *dbgdev)
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{
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BUG_ON(!dbgdev);
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/*
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* no action is needed in this case,
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* just make sure diq will not be used
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*/
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dbgdev->kq = NULL;
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return 0;
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}
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static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev)
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{
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struct queue_properties properties;
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unsigned int qid;
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struct kernel_queue *kq = NULL;
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int status;
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BUG_ON(!dbgdev || !dbgdev->pqm || !dbgdev->dev);
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status = pqm_create_queue(dbgdev->pqm, dbgdev->dev, NULL,
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&properties, 0, KFD_QUEUE_TYPE_DIQ,
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&qid);
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if (status) {
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pr_err("amdkfd: Failed to create DIQ\n");
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return status;
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}
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pr_debug("DIQ Created with queue id: %d\n", qid);
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kq = pqm_get_kernel_queue(dbgdev->pqm, qid);
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if (kq == NULL) {
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pr_err("amdkfd: Error getting DIQ\n");
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pqm_destroy_queue(dbgdev->pqm, qid);
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return -EFAULT;
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}
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dbgdev->kq = kq;
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return status;
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}
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static int dbgdev_unregister_nodiq(struct kfd_dbgdev *dbgdev)
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{
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BUG_ON(!dbgdev || !dbgdev->dev);
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/* disable watch address */
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dbgdev_address_watch_disable_nodiq(dbgdev->dev);
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return 0;
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}
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static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev)
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{
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/* todo - disable address watch */
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int status;
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BUG_ON(!dbgdev || !dbgdev->pqm || !dbgdev->kq);
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status = pqm_destroy_queue(dbgdev->pqm,
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dbgdev->kq->queue->properties.queue_id);
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dbgdev->kq = NULL;
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return status;
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}
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2015-05-20 04:59:17 -06:00
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static void dbgdev_address_watch_set_registers(
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const struct dbg_address_watch_info *adw_info,
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union TCP_WATCH_ADDR_H_BITS *addrHi,
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union TCP_WATCH_ADDR_L_BITS *addrLo,
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union TCP_WATCH_CNTL_BITS *cntl,
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unsigned int index, unsigned int vmid)
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{
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union ULARGE_INTEGER addr;
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BUG_ON(!adw_info || !addrHi || !addrLo || !cntl);
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addr.quad_part = 0;
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addrHi->u32All = 0;
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addrLo->u32All = 0;
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cntl->u32All = 0;
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if (adw_info->watch_mask != NULL)
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cntl->bitfields.mask =
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(uint32_t) (adw_info->watch_mask[index] &
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ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK);
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else
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cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
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addr.quad_part = (unsigned long long) adw_info->watch_address[index];
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addrHi->bitfields.addr = addr.u.high_part &
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ADDRESS_WATCH_REG_ADDHIGH_MASK;
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addrLo->bitfields.addr =
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(addr.u.low_part >> ADDRESS_WATCH_REG_ADDLOW_SHIFT);
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cntl->bitfields.mode = adw_info->watch_mode[index];
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cntl->bitfields.vmid = (uint32_t) vmid;
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/* for now assume it is an ATC address */
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cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT;
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pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask);
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pr_debug("\t\t%20s %08x\n", "set reg add high :",
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addrHi->bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "set reg add low :",
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addrLo->bitfields.addr);
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}
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static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev,
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struct dbg_address_watch_info *adw_info)
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{
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union TCP_WATCH_ADDR_H_BITS addrHi;
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union TCP_WATCH_ADDR_L_BITS addrLo;
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union TCP_WATCH_CNTL_BITS cntl;
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struct kfd_process_device *pdd;
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unsigned int i;
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BUG_ON(!dbgdev || !dbgdev->dev || !adw_info);
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/* taking the vmid for that process on the safe way using pdd */
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pdd = kfd_get_process_device_data(dbgdev->dev,
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adw_info->process);
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if (!pdd) {
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pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n");
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return -EFAULT;
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}
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addrHi.u32All = 0;
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addrLo.u32All = 0;
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cntl.u32All = 0;
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if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) ||
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(adw_info->num_watch_points == 0)) {
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pr_err("amdkfd: num_watch_points is invalid\n");
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return -EINVAL;
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}
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if ((adw_info->watch_mode == NULL) ||
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(adw_info->watch_address == NULL)) {
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pr_err("amdkfd: adw_info fields are not valid\n");
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return -EINVAL;
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}
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for (i = 0 ; i < adw_info->num_watch_points ; i++) {
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dbgdev_address_watch_set_registers(adw_info, &addrHi, &addrLo,
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&cntl, i, pdd->qpd.vmid);
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pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
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pr_debug("\t\t%20s %08x\n", "register index :", i);
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pr_debug("\t\t%20s %08x\n", "vmid is :", pdd->qpd.vmid);
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pr_debug("\t\t%20s %08x\n", "Address Low is :",
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addrLo.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Address high is :",
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addrHi.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Address high is :",
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addrHi.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Control Mask is :",
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cntl.bitfields.mask);
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pr_debug("\t\t%20s %08x\n", "Control Mode is :",
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cntl.bitfields.mode);
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pr_debug("\t\t%20s %08x\n", "Control Vmid is :",
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cntl.bitfields.vmid);
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pr_debug("\t\t%20s %08x\n", "Control atc is :",
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cntl.bitfields.atc);
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pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
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pdd->dev->kfd2kgd->address_watch_execute(
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dbgdev->dev->kgd,
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i,
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cntl.u32All,
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addrHi.u32All,
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addrLo.u32All);
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}
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return 0;
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}
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static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
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struct dbg_address_watch_info *adw_info)
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|
{
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struct pm4__set_config_reg *packets_vec;
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union TCP_WATCH_ADDR_H_BITS addrHi;
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union TCP_WATCH_ADDR_L_BITS addrLo;
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union TCP_WATCH_CNTL_BITS cntl;
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struct kfd_mem_obj *mem_obj;
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unsigned int aw_reg_add_dword;
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|
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uint32_t *packet_buff_uint;
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unsigned int i;
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int status;
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size_t ib_size = sizeof(struct pm4__set_config_reg) * 4;
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/* we do not control the vmid in DIQ mode, just a place holder */
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unsigned int vmid = 0;
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BUG_ON(!dbgdev || !dbgdev->dev || !adw_info);
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addrHi.u32All = 0;
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addrLo.u32All = 0;
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cntl.u32All = 0;
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if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) ||
|
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|
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(adw_info->num_watch_points == 0)) {
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pr_err("amdkfd: num_watch_points is invalid\n");
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return -EINVAL;
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}
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if ((NULL == adw_info->watch_mode) ||
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(NULL == adw_info->watch_address)) {
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pr_err("amdkfd: adw_info fields are not valid\n");
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return -EINVAL;
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}
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status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj);
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if (status != 0) {
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pr_err("amdkfd: Failed to allocate GART memory\n");
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return status;
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}
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packet_buff_uint = mem_obj->cpu_ptr;
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memset(packet_buff_uint, 0, ib_size);
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packets_vec = (struct pm4__set_config_reg *) (packet_buff_uint);
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packets_vec[0].header.count = 1;
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packets_vec[0].header.opcode = IT_SET_CONFIG_REG;
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packets_vec[0].header.type = PM4_TYPE_3;
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packets_vec[0].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;
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packets_vec[0].bitfields2.insert_vmid = 1;
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packets_vec[1].ordinal1 = packets_vec[0].ordinal1;
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packets_vec[1].bitfields2.insert_vmid = 0;
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packets_vec[2].ordinal1 = packets_vec[0].ordinal1;
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packets_vec[2].bitfields2.insert_vmid = 0;
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packets_vec[3].ordinal1 = packets_vec[0].ordinal1;
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packets_vec[3].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;
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packets_vec[3].bitfields2.insert_vmid = 1;
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for (i = 0; i < adw_info->num_watch_points; i++) {
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dbgdev_address_watch_set_registers(adw_info,
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&addrHi,
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&addrLo,
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&cntl,
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i,
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vmid);
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pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
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pr_debug("\t\t%20s %08x\n", "register index :", i);
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pr_debug("\t\t%20s %08x\n", "vmid is :", vmid);
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pr_debug("\t\t%20s %p\n", "Add ptr is :",
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|
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adw_info->watch_address);
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pr_debug("\t\t%20s %08llx\n", "Add is :",
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adw_info->watch_address[i]);
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pr_debug("\t\t%20s %08x\n", "Address Low is :",
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addrLo.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Address high is :",
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|
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addrHi.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Control Mask is :",
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cntl.bitfields.mask);
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pr_debug("\t\t%20s %08x\n", "Control Mode is :",
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|
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cntl.bitfields.mode);
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pr_debug("\t\t%20s %08x\n", "Control Vmid is :",
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|
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cntl.bitfields.vmid);
|
|
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pr_debug("\t\t%20s %08x\n", "Control atc is :",
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|
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cntl.bitfields.atc);
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|
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pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
|
|
|
|
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|
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aw_reg_add_dword =
|
|
|
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dbgdev->dev->kfd2kgd->address_watch_get_offset(
|
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|
|
dbgdev->dev->kgd,
|
|
|
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i,
|
|
|
|
ADDRESS_WATCH_REG_CNTL);
|
|
|
|
|
|
|
|
packets_vec[0].bitfields2.reg_offset =
|
2015-06-05 02:27:43 -06:00
|
|
|
aw_reg_add_dword - AMD_CONFIG_REG_BASE;
|
2015-05-20 04:59:17 -06:00
|
|
|
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|
|
packets_vec[0].reg_data[0] = cntl.u32All;
|
|
|
|
|
|
|
|
aw_reg_add_dword =
|
|
|
|
dbgdev->dev->kfd2kgd->address_watch_get_offset(
|
|
|
|
dbgdev->dev->kgd,
|
|
|
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i,
|
|
|
|
ADDRESS_WATCH_REG_ADDR_HI);
|
|
|
|
|
|
|
|
packets_vec[1].bitfields2.reg_offset =
|
2015-06-05 02:27:43 -06:00
|
|
|
aw_reg_add_dword - AMD_CONFIG_REG_BASE;
|
2015-05-20 04:59:17 -06:00
|
|
|
packets_vec[1].reg_data[0] = addrHi.u32All;
|
|
|
|
|
|
|
|
aw_reg_add_dword =
|
|
|
|
dbgdev->dev->kfd2kgd->address_watch_get_offset(
|
|
|
|
dbgdev->dev->kgd,
|
|
|
|
i,
|
|
|
|
ADDRESS_WATCH_REG_ADDR_LO);
|
|
|
|
|
|
|
|
packets_vec[2].bitfields2.reg_offset =
|
2015-06-05 02:27:43 -06:00
|
|
|
aw_reg_add_dword - AMD_CONFIG_REG_BASE;
|
2015-05-20 04:59:17 -06:00
|
|
|
packets_vec[2].reg_data[0] = addrLo.u32All;
|
|
|
|
|
|
|
|
/* enable watch flag if address is not zero*/
|
|
|
|
if (adw_info->watch_address[i] > 0)
|
|
|
|
cntl.bitfields.valid = 1;
|
|
|
|
else
|
|
|
|
cntl.bitfields.valid = 0;
|
|
|
|
|
|
|
|
aw_reg_add_dword =
|
|
|
|
dbgdev->dev->kfd2kgd->address_watch_get_offset(
|
|
|
|
dbgdev->dev->kgd,
|
|
|
|
i,
|
|
|
|
ADDRESS_WATCH_REG_CNTL);
|
|
|
|
|
|
|
|
packets_vec[3].bitfields2.reg_offset =
|
2015-06-05 02:27:43 -06:00
|
|
|
aw_reg_add_dword - AMD_CONFIG_REG_BASE;
|
2015-05-20 04:59:17 -06:00
|
|
|
packets_vec[3].reg_data[0] = cntl.u32All;
|
|
|
|
|
|
|
|
status = dbgdev_diq_submit_ib(
|
|
|
|
dbgdev,
|
|
|
|
adw_info->process->pasid,
|
|
|
|
mem_obj->gpu_addr,
|
|
|
|
packet_buff_uint,
|
|
|
|
ib_size);
|
|
|
|
|
|
|
|
if (status != 0) {
|
|
|
|
pr_err("amdkfd: Failed to submit IB to DIQ\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
kfd_gtt_sa_free(dbgdev->dev, mem_obj);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2015-05-20 04:58:12 -06:00
|
|
|
static int dbgdev_wave_control_set_registers(
|
|
|
|
struct dbg_wave_control_info *wac_info,
|
|
|
|
union SQ_CMD_BITS *in_reg_sq_cmd,
|
|
|
|
union GRBM_GFX_INDEX_BITS *in_reg_gfx_index)
|
|
|
|
{
|
2016-03-11 00:51:51 -07:00
|
|
|
int status = 0;
|
2015-05-20 04:58:12 -06:00
|
|
|
union SQ_CMD_BITS reg_sq_cmd;
|
|
|
|
union GRBM_GFX_INDEX_BITS reg_gfx_index;
|
|
|
|
struct HsaDbgWaveMsgAMDGen2 *pMsg;
|
|
|
|
|
|
|
|
BUG_ON(!wac_info || !in_reg_sq_cmd || !in_reg_gfx_index);
|
|
|
|
|
|
|
|
reg_sq_cmd.u32All = 0;
|
|
|
|
reg_gfx_index.u32All = 0;
|
|
|
|
pMsg = &wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2;
|
|
|
|
|
|
|
|
switch (wac_info->mode) {
|
|
|
|
/* Send command to single wave */
|
|
|
|
case HSA_DBG_WAVEMODE_SINGLE:
|
|
|
|
/*
|
|
|
|
* Limit access to the process waves only,
|
|
|
|
* by setting vmid check
|
|
|
|
*/
|
|
|
|
reg_sq_cmd.bits.check_vmid = 1;
|
|
|
|
reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD;
|
|
|
|
reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId;
|
|
|
|
reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_SINGLE;
|
|
|
|
|
|
|
|
reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray;
|
|
|
|
reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine;
|
|
|
|
reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU;
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Send command to all waves with matching VMID */
|
|
|
|
case HSA_DBG_WAVEMODE_BROADCAST_PROCESS:
|
|
|
|
|
|
|
|
reg_gfx_index.bits.sh_broadcast_writes = 1;
|
|
|
|
reg_gfx_index.bits.se_broadcast_writes = 1;
|
|
|
|
reg_gfx_index.bits.instance_broadcast_writes = 1;
|
|
|
|
|
|
|
|
reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Send command to all CU waves with matching VMID */
|
|
|
|
case HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU:
|
|
|
|
|
|
|
|
reg_sq_cmd.bits.check_vmid = 1;
|
|
|
|
reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
|
|
|
|
|
|
|
|
reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray;
|
|
|
|
reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine;
|
|
|
|
reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU;
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (wac_info->operand) {
|
|
|
|
case HSA_DBG_WAVEOP_HALT:
|
|
|
|
reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_HALT;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HSA_DBG_WAVEOP_RESUME:
|
|
|
|
reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_RESUME;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HSA_DBG_WAVEOP_KILL:
|
|
|
|
reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HSA_DBG_WAVEOP_DEBUG:
|
|
|
|
reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_DEBUG;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HSA_DBG_WAVEOP_TRAP:
|
|
|
|
if (wac_info->trapId < MAX_TRAPID) {
|
|
|
|
reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_TRAP;
|
|
|
|
reg_sq_cmd.bits.trap_id = wac_info->trapId;
|
|
|
|
} else {
|
|
|
|
status = -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
status = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status == 0) {
|
|
|
|
*in_reg_sq_cmd = reg_sq_cmd;
|
|
|
|
*in_reg_gfx_index = reg_gfx_index;
|
|
|
|
}
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
|
|
|
|
struct dbg_wave_control_info *wac_info)
|
|
|
|
{
|
|
|
|
|
|
|
|
int status;
|
|
|
|
union SQ_CMD_BITS reg_sq_cmd;
|
|
|
|
union GRBM_GFX_INDEX_BITS reg_gfx_index;
|
|
|
|
struct kfd_mem_obj *mem_obj;
|
|
|
|
uint32_t *packet_buff_uint;
|
|
|
|
struct pm4__set_config_reg *packets_vec;
|
|
|
|
size_t ib_size = sizeof(struct pm4__set_config_reg) * 3;
|
|
|
|
|
|
|
|
BUG_ON(!dbgdev || !wac_info);
|
|
|
|
|
|
|
|
reg_sq_cmd.u32All = 0;
|
|
|
|
|
|
|
|
status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd,
|
|
|
|
®_gfx_index);
|
|
|
|
if (status) {
|
|
|
|
pr_err("amdkfd: Failed to set wave control registers\n");
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we do not control the VMID in DIQ,so reset it to a known value */
|
|
|
|
reg_sq_cmd.bits.vm_id = 0;
|
|
|
|
|
|
|
|
pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
|
|
|
|
|
|
|
|
pr_debug("\t\t mode is: %u\n", wac_info->mode);
|
|
|
|
pr_debug("\t\t operand is: %u\n", wac_info->operand);
|
|
|
|
pr_debug("\t\t trap id is: %u\n", wac_info->trapId);
|
|
|
|
pr_debug("\t\t msg value is: %u\n",
|
|
|
|
wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
|
|
|
|
pr_debug("\t\t vmid is: N/A\n");
|
|
|
|
|
|
|
|
pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid);
|
|
|
|
pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd);
|
|
|
|
pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id);
|
|
|
|
pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id);
|
|
|
|
pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode);
|
|
|
|
pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id);
|
|
|
|
pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id);
|
|
|
|
|
|
|
|
pr_debug("\t\t ibw is : %u\n",
|
|
|
|
reg_gfx_index.bitfields.instance_broadcast_writes);
|
|
|
|
pr_debug("\t\t ii is : %u\n",
|
|
|
|
reg_gfx_index.bitfields.instance_index);
|
|
|
|
pr_debug("\t\t sebw is : %u\n",
|
|
|
|
reg_gfx_index.bitfields.se_broadcast_writes);
|
|
|
|
pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index);
|
|
|
|
pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index);
|
|
|
|
pr_debug("\t\t sbw is : %u\n",
|
|
|
|
reg_gfx_index.bitfields.sh_broadcast_writes);
|
|
|
|
|
|
|
|
pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
|
|
|
|
|
|
|
|
status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj);
|
|
|
|
|
|
|
|
if (status != 0) {
|
|
|
|
pr_err("amdkfd: Failed to allocate GART memory\n");
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
packet_buff_uint = mem_obj->cpu_ptr;
|
|
|
|
|
|
|
|
memset(packet_buff_uint, 0, ib_size);
|
|
|
|
|
|
|
|
packets_vec = (struct pm4__set_config_reg *) packet_buff_uint;
|
|
|
|
packets_vec[0].header.count = 1;
|
|
|
|
packets_vec[0].header.opcode = IT_SET_UCONFIG_REG;
|
|
|
|
packets_vec[0].header.type = PM4_TYPE_3;
|
|
|
|
packets_vec[0].bitfields2.reg_offset =
|
|
|
|
GRBM_GFX_INDEX / (sizeof(uint32_t)) -
|
|
|
|
USERCONFIG_REG_BASE;
|
|
|
|
|
|
|
|
packets_vec[0].bitfields2.insert_vmid = 0;
|
|
|
|
packets_vec[0].reg_data[0] = reg_gfx_index.u32All;
|
|
|
|
|
|
|
|
packets_vec[1].header.count = 1;
|
|
|
|
packets_vec[1].header.opcode = IT_SET_CONFIG_REG;
|
|
|
|
packets_vec[1].header.type = PM4_TYPE_3;
|
|
|
|
packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -
|
2015-06-05 02:27:43 -06:00
|
|
|
AMD_CONFIG_REG_BASE;
|
2015-05-20 04:58:12 -06:00
|
|
|
|
|
|
|
packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;
|
|
|
|
packets_vec[1].bitfields2.insert_vmid = 1;
|
|
|
|
packets_vec[1].reg_data[0] = reg_sq_cmd.u32All;
|
|
|
|
|
|
|
|
/* Restore the GRBM_GFX_INDEX register */
|
|
|
|
|
|
|
|
reg_gfx_index.u32All = 0;
|
|
|
|
reg_gfx_index.bits.sh_broadcast_writes = 1;
|
|
|
|
reg_gfx_index.bits.instance_broadcast_writes = 1;
|
|
|
|
reg_gfx_index.bits.se_broadcast_writes = 1;
|
|
|
|
|
|
|
|
|
|
|
|
packets_vec[2].ordinal1 = packets_vec[0].ordinal1;
|
|
|
|
packets_vec[2].bitfields2.reg_offset =
|
|
|
|
GRBM_GFX_INDEX / (sizeof(uint32_t)) -
|
|
|
|
USERCONFIG_REG_BASE;
|
|
|
|
|
|
|
|
packets_vec[2].bitfields2.insert_vmid = 0;
|
|
|
|
packets_vec[2].reg_data[0] = reg_gfx_index.u32All;
|
|
|
|
|
|
|
|
status = dbgdev_diq_submit_ib(
|
|
|
|
dbgdev,
|
|
|
|
wac_info->process->pasid,
|
|
|
|
mem_obj->gpu_addr,
|
|
|
|
packet_buff_uint,
|
|
|
|
ib_size);
|
|
|
|
|
|
|
|
if (status != 0)
|
|
|
|
pr_err("amdkfd: Failed to submit IB to DIQ\n");
|
|
|
|
|
|
|
|
kfd_gtt_sa_free(dbgdev->dev, mem_obj);
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dbgdev_wave_control_nodiq(struct kfd_dbgdev *dbgdev,
|
|
|
|
struct dbg_wave_control_info *wac_info)
|
|
|
|
{
|
|
|
|
int status;
|
|
|
|
union SQ_CMD_BITS reg_sq_cmd;
|
|
|
|
union GRBM_GFX_INDEX_BITS reg_gfx_index;
|
|
|
|
struct kfd_process_device *pdd;
|
|
|
|
|
|
|
|
BUG_ON(!dbgdev || !dbgdev->dev || !wac_info);
|
|
|
|
|
|
|
|
reg_sq_cmd.u32All = 0;
|
|
|
|
|
|
|
|
/* taking the VMID for that process on the safe way using PDD */
|
|
|
|
pdd = kfd_get_process_device_data(dbgdev->dev, wac_info->process);
|
|
|
|
|
|
|
|
if (!pdd) {
|
|
|
|
pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n");
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd,
|
|
|
|
®_gfx_index);
|
|
|
|
if (status) {
|
|
|
|
pr_err("amdkfd: Failed to set wave control registers\n");
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* for non DIQ we need to patch the VMID: */
|
|
|
|
|
|
|
|
reg_sq_cmd.bits.vm_id = pdd->qpd.vmid;
|
|
|
|
|
|
|
|
pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
|
|
|
|
|
|
|
|
pr_debug("\t\t mode is: %u\n", wac_info->mode);
|
|
|
|
pr_debug("\t\t operand is: %u\n", wac_info->operand);
|
|
|
|
pr_debug("\t\t trap id is: %u\n", wac_info->trapId);
|
|
|
|
pr_debug("\t\t msg value is: %u\n",
|
|
|
|
wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
|
|
|
|
pr_debug("\t\t vmid is: %u\n", pdd->qpd.vmid);
|
|
|
|
|
|
|
|
pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid);
|
|
|
|
pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd);
|
|
|
|
pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id);
|
|
|
|
pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id);
|
|
|
|
pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode);
|
|
|
|
pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id);
|
|
|
|
pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id);
|
|
|
|
|
|
|
|
pr_debug("\t\t ibw is : %u\n",
|
|
|
|
reg_gfx_index.bitfields.instance_broadcast_writes);
|
|
|
|
pr_debug("\t\t ii is : %u\n",
|
|
|
|
reg_gfx_index.bitfields.instance_index);
|
|
|
|
pr_debug("\t\t sebw is : %u\n",
|
|
|
|
reg_gfx_index.bitfields.se_broadcast_writes);
|
|
|
|
pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index);
|
|
|
|
pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index);
|
|
|
|
pr_debug("\t\t sbw is : %u\n",
|
|
|
|
reg_gfx_index.bitfields.sh_broadcast_writes);
|
|
|
|
|
|
|
|
pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
|
|
|
|
|
|
|
|
return dbgdev->dev->kfd2kgd->wave_control_execute(dbgdev->dev->kgd,
|
|
|
|
reg_gfx_index.u32All,
|
|
|
|
reg_sq_cmd.u32All);
|
|
|
|
}
|
|
|
|
|
2015-05-20 09:05:44 -06:00
|
|
|
int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p)
|
|
|
|
{
|
|
|
|
int status = 0;
|
|
|
|
unsigned int vmid;
|
|
|
|
union SQ_CMD_BITS reg_sq_cmd;
|
|
|
|
union GRBM_GFX_INDEX_BITS reg_gfx_index;
|
|
|
|
struct kfd_process_device *pdd;
|
|
|
|
struct dbg_wave_control_info wac_info;
|
|
|
|
int temp;
|
|
|
|
int first_vmid_to_scan = 8;
|
|
|
|
int last_vmid_to_scan = 15;
|
|
|
|
|
|
|
|
first_vmid_to_scan = ffs(dev->shared_resources.compute_vmid_bitmap) - 1;
|
|
|
|
temp = dev->shared_resources.compute_vmid_bitmap >> first_vmid_to_scan;
|
|
|
|
last_vmid_to_scan = first_vmid_to_scan + ffz(temp);
|
|
|
|
|
|
|
|
reg_sq_cmd.u32All = 0;
|
|
|
|
status = 0;
|
|
|
|
|
|
|
|
wac_info.mode = HSA_DBG_WAVEMODE_BROADCAST_PROCESS;
|
|
|
|
wac_info.operand = HSA_DBG_WAVEOP_KILL;
|
|
|
|
|
|
|
|
pr_debug("Killing all process wavefronts\n");
|
|
|
|
|
|
|
|
/* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..
|
|
|
|
* ATC_VMID15_PASID_MAPPING
|
|
|
|
* to check which VMID the current process is mapped to. */
|
|
|
|
|
|
|
|
for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
|
|
|
|
if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid
|
|
|
|
(dev->kgd, vmid)) {
|
2017-08-15 20:59:59 -06:00
|
|
|
if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_pasid
|
2015-05-20 09:05:44 -06:00
|
|
|
(dev->kgd, vmid) == p->pasid) {
|
|
|
|
pr_debug("Killing wave fronts of vmid %d and pasid %d\n",
|
|
|
|
vmid, p->pasid);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (vmid > last_vmid_to_scan) {
|
|
|
|
pr_err("amdkfd: didn't found vmid for pasid (%d)\n", p->pasid);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* taking the VMID for that process on the safe way using PDD */
|
|
|
|
pdd = kfd_get_process_device_data(dev, p);
|
|
|
|
if (!pdd)
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
status = dbgdev_wave_control_set_registers(&wac_info, ®_sq_cmd,
|
|
|
|
®_gfx_index);
|
|
|
|
if (status != 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* for non DIQ we need to patch the VMID: */
|
|
|
|
reg_sq_cmd.bits.vm_id = vmid;
|
|
|
|
|
|
|
|
dev->kfd2kgd->wave_control_execute(dev->kgd,
|
|
|
|
reg_gfx_index.u32All,
|
|
|
|
reg_sq_cmd.u32All);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-05-20 04:48:26 -06:00
|
|
|
void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
|
|
|
|
enum DBGDEV_TYPE type)
|
|
|
|
{
|
|
|
|
BUG_ON(!pdbgdev || !pdev);
|
|
|
|
|
|
|
|
pdbgdev->dev = pdev;
|
|
|
|
pdbgdev->kq = NULL;
|
|
|
|
pdbgdev->type = type;
|
|
|
|
pdbgdev->pqm = NULL;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case DBGDEV_TYPE_NODIQ:
|
|
|
|
pdbgdev->dbgdev_register = dbgdev_register_nodiq;
|
|
|
|
pdbgdev->dbgdev_unregister = dbgdev_unregister_nodiq;
|
2015-05-20 04:58:12 -06:00
|
|
|
pdbgdev->dbgdev_wave_control = dbgdev_wave_control_nodiq;
|
2015-05-20 04:59:17 -06:00
|
|
|
pdbgdev->dbgdev_address_watch = dbgdev_address_watch_nodiq;
|
2015-05-20 04:48:26 -06:00
|
|
|
break;
|
|
|
|
case DBGDEV_TYPE_DIQ:
|
|
|
|
default:
|
|
|
|
pdbgdev->dbgdev_register = dbgdev_register_diq;
|
|
|
|
pdbgdev->dbgdev_unregister = dbgdev_unregister_diq;
|
2015-05-20 04:58:12 -06:00
|
|
|
pdbgdev->dbgdev_wave_control = dbgdev_wave_control_diq;
|
2015-05-20 04:59:17 -06:00
|
|
|
pdbgdev->dbgdev_address_watch = dbgdev_address_watch_diq;
|
2015-05-20 04:48:26 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|