License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 08:07:57 -06:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2015-11-30 20:36:28 -07:00
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#ifndef _ASM_POWERPC_BOOK3S_32_PGTABLE_H
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#define _ASM_POWERPC_BOOK3S_32_PGTABLE_H
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2017-03-09 07:24:05 -07:00
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#define __ARCH_USE_5LEVEL_HACK
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2015-11-30 20:36:28 -07:00
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#include <asm-generic/pgtable-nopmd.h>
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2015-11-30 20:36:31 -07:00
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#include <asm/book3s/32/hash.h>
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2015-11-30 20:36:28 -07:00
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2015-11-30 20:36:31 -07:00
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/* And here we include common definitions */
|
2018-10-09 07:52:04 -06:00
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#define _PAGE_KERNEL_RO 0
|
2018-11-28 10:21:10 -07:00
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#define _PAGE_KERNEL_ROX (_PAGE_EXEC)
|
2018-10-09 07:52:04 -06:00
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW)
|
2018-11-28 10:21:10 -07:00
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#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
|
2018-10-09 07:52:04 -06:00
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#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
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#ifndef __ASSEMBLY__
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static inline bool pte_user(pte_t pte)
|
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|
{
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|
return pte_val(pte) & _PAGE_USER;
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|
}
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#endif /* __ASSEMBLY__ */
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/*
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|
* Location of the PFN in the PTE. Most 32-bit platforms use the same
|
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* as _PAGE_SHIFT here (ie, naturally aligned).
|
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* Platform who don't just pre-define the value so we don't override it here.
|
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*/
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#define PTE_RPN_SHIFT (PAGE_SHIFT)
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/*
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* The mask covered by the RPN must be a ULL on 32-bit platforms with
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* 64-bit PTEs.
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*/
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#ifdef CONFIG_PTE_64BIT
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#define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1))
|
arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed
[ Upstream commit cef397038167ac15d085914493d6c86385773709 ]
Stefan Agner reported a bug when using zsram on 32-bit Arm machines
with RAM above the 4GB address boundary:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = a27bd01c
[00000000] *pgd=236a0003, *pmd=1ffa64003
Internal error: Oops: 207 [#1] SMP ARM
Modules linked in: mdio_bcm_unimac(+) brcmfmac cfg80211 brcmutil raspberrypi_hwmon hci_uart crc32_arm_ce bcm2711_thermal phy_generic genet
CPU: 0 PID: 123 Comm: mkfs.ext4 Not tainted 5.9.6 #1
Hardware name: BCM2711
PC is at zs_map_object+0x94/0x338
LR is at zram_bvec_rw.constprop.0+0x330/0xa64
pc : [<c0602b38>] lr : [<c0bda6a0>] psr: 60000013
sp : e376bbe0 ip : 00000000 fp : c1e2921c
r10: 00000002 r9 : c1dda730 r8 : 00000000
r7 : e8ff7a00 r6 : 00000000 r5 : 02f9ffa0 r4 : e3710000
r3 : 000fdffe r2 : c1e0ce80 r1 : ebf979a0 r0 : 00000000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 30c5383d Table: 235c2a80 DAC: fffffffd
Process mkfs.ext4 (pid: 123, stack limit = 0x495a22e6)
Stack: (0xe376bbe0 to 0xe376c000)
As it turns out, zsram needs to know the maximum memory size, which
is defined in MAX_PHYSMEM_BITS when CONFIG_SPARSEMEM is set, or in
MAX_POSSIBLE_PHYSMEM_BITS on the x86 architecture.
The same problem will be hit on all 32-bit architectures that have a
physical address space larger than 4GB and happen to not enable sparsemem
and include asm/sparsemem.h from asm/pgtable.h.
After the initial discussion, I suggested just always defining
MAX_POSSIBLE_PHYSMEM_BITS whenever CONFIG_PHYS_ADDR_T_64BIT is
set, or provoking a build error otherwise. This addresses all
configurations that can currently have this runtime bug, but
leaves all other configurations unchanged.
I looked up the possible number of bits in source code and
datasheets, here is what I found:
- on ARC, CONFIG_ARC_HAS_PAE40 controls whether 32 or 40 bits are used
- on ARM, CONFIG_LPAE enables 40 bit addressing, without it we never
support more than 32 bits, even though supersections in theory allow
up to 40 bits as well.
- on MIPS, some MIPS32r1 or later chips support 36 bits, and MIPS32r5
XPA supports up to 60 bits in theory, but 40 bits are more than
anyone will ever ship
- On PowerPC, there are three different implementations of 36 bit
addressing, but 32-bit is used without CONFIG_PTE_64BIT
- On RISC-V, the normal page table format can support 34 bit
addressing. There is no highmem support on RISC-V, so anything
above 2GB is unused, but it might be useful to eventually support
CONFIG_ZRAM for high pages.
Fixes: 61989a80fb3a ("staging: zsmalloc: zsmalloc memory allocation library")
Fixes: 02390b87a945 ("mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS")
Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Mike Rapoport <rppt@linux.ibm.com>
Link: https://lore.kernel.org/linux-mm/bdfa44bf1c570b05d6c70898e2bbb0acf234ecdf.1604762181.git.stefan@agner.ch/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-11-11 09:52:58 -07:00
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#define MAX_POSSIBLE_PHYSMEM_BITS 36
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2018-10-09 07:52:04 -06:00
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#else
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#define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
|
arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed
[ Upstream commit cef397038167ac15d085914493d6c86385773709 ]
Stefan Agner reported a bug when using zsram on 32-bit Arm machines
with RAM above the 4GB address boundary:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = a27bd01c
[00000000] *pgd=236a0003, *pmd=1ffa64003
Internal error: Oops: 207 [#1] SMP ARM
Modules linked in: mdio_bcm_unimac(+) brcmfmac cfg80211 brcmutil raspberrypi_hwmon hci_uart crc32_arm_ce bcm2711_thermal phy_generic genet
CPU: 0 PID: 123 Comm: mkfs.ext4 Not tainted 5.9.6 #1
Hardware name: BCM2711
PC is at zs_map_object+0x94/0x338
LR is at zram_bvec_rw.constprop.0+0x330/0xa64
pc : [<c0602b38>] lr : [<c0bda6a0>] psr: 60000013
sp : e376bbe0 ip : 00000000 fp : c1e2921c
r10: 00000002 r9 : c1dda730 r8 : 00000000
r7 : e8ff7a00 r6 : 00000000 r5 : 02f9ffa0 r4 : e3710000
r3 : 000fdffe r2 : c1e0ce80 r1 : ebf979a0 r0 : 00000000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 30c5383d Table: 235c2a80 DAC: fffffffd
Process mkfs.ext4 (pid: 123, stack limit = 0x495a22e6)
Stack: (0xe376bbe0 to 0xe376c000)
As it turns out, zsram needs to know the maximum memory size, which
is defined in MAX_PHYSMEM_BITS when CONFIG_SPARSEMEM is set, or in
MAX_POSSIBLE_PHYSMEM_BITS on the x86 architecture.
The same problem will be hit on all 32-bit architectures that have a
physical address space larger than 4GB and happen to not enable sparsemem
and include asm/sparsemem.h from asm/pgtable.h.
After the initial discussion, I suggested just always defining
MAX_POSSIBLE_PHYSMEM_BITS whenever CONFIG_PHYS_ADDR_T_64BIT is
set, or provoking a build error otherwise. This addresses all
configurations that can currently have this runtime bug, but
leaves all other configurations unchanged.
I looked up the possible number of bits in source code and
datasheets, here is what I found:
- on ARC, CONFIG_ARC_HAS_PAE40 controls whether 32 or 40 bits are used
- on ARM, CONFIG_LPAE enables 40 bit addressing, without it we never
support more than 32 bits, even though supersections in theory allow
up to 40 bits as well.
- on MIPS, some MIPS32r1 or later chips support 36 bits, and MIPS32r5
XPA supports up to 60 bits in theory, but 40 bits are more than
anyone will ever ship
- On PowerPC, there are three different implementations of 36 bit
addressing, but 32-bit is used without CONFIG_PTE_64BIT
- On RISC-V, the normal page table format can support 34 bit
addressing. There is no highmem support on RISC-V, so anything
above 2GB is unused, but it might be useful to eventually support
CONFIG_ZRAM for high pages.
Fixes: 61989a80fb3a ("staging: zsmalloc: zsmalloc memory allocation library")
Fixes: 02390b87a945 ("mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS")
Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Mike Rapoport <rppt@linux.ibm.com>
Link: https://lore.kernel.org/linux-mm/bdfa44bf1c570b05d6c70898e2bbb0acf234ecdf.1604762181.git.stefan@agner.ch/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-11-11 09:52:58 -07:00
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#define MAX_POSSIBLE_PHYSMEM_BITS 32
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2018-10-09 07:52:04 -06:00
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#endif
|
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/*
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* _PAGE_CHG_MASK masks of bits that are to be preserved across
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* pgprot changes.
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*/
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#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HASHPTE | _PAGE_DIRTY | \
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|
_PAGE_ACCESSED | _PAGE_SPECIAL)
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|
|
|
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/*
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|
* We define 2 sets of base prot bits, one for basic pages (ie,
|
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|
* cacheable kernel and user pages) and one for non cacheable
|
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* pages. We always set _PAGE_COHERENT when SMP is enabled or
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* the processor might need it for DMA coherency.
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*/
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
|
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/*
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|
* Permission masks used to generate the __P and __S table.
|
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*
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* Note:__pgprot is defined in arch/powerpc/include/asm/page.h
|
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|
*
|
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* Write permissions imply read permissions for now.
|
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*/
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#define PAGE_NONE __pgprot(_PAGE_BASE)
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#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
|
2018-11-28 10:21:10 -07:00
|
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#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
|
2018-10-09 07:52:04 -06:00
|
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#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
|
2018-11-28 10:21:10 -07:00
|
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#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
|
2018-10-09 07:52:04 -06:00
|
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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2018-11-28 10:21:10 -07:00
|
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#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
|
2018-10-09 07:52:04 -06:00
|
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/* Permission masks used for kernel mappings */
|
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#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
|
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#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE)
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#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
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_PAGE_NO_CACHE | _PAGE_GUARDED)
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#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
|
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#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
|
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#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
|
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|
|
|
|
|
|
/*
|
|
|
|
* Protection used for kernel text. We want the debuggers to be able to
|
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|
* set breakpoints anywhere, so don't write protect the kernel text
|
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|
* on platforms where such control is possible.
|
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*/
|
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#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
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defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
|
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#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
|
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#else
|
|
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#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
|
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|
#endif
|
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|
|
|
|
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/* Make modules code happy. We don't set RO yet */
|
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#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
|
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|
|
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/* Advertise special mapping type for AGP */
|
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#define PAGE_AGP (PAGE_KERNEL_NC)
|
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#define HAVE_PAGE_AGP
|
2015-11-30 20:36:28 -07:00
|
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|
2016-12-07 00:47:24 -07:00
|
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#define PTE_INDEX_SIZE PTE_SHIFT
|
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#define PMD_INDEX_SIZE 0
|
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#define PUD_INDEX_SIZE 0
|
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#define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
|
|
|
|
|
|
|
|
#define PMD_CACHE_INDEX PMD_INDEX_SIZE
|
2018-02-11 08:00:06 -07:00
|
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#define PUD_CACHE_INDEX PUD_INDEX_SIZE
|
2016-12-07 00:47:24 -07:00
|
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|
|
|
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#ifndef __ASSEMBLY__
|
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#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
|
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#define PMD_TABLE_SIZE 0
|
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|
#define PUD_TABLE_SIZE 0
|
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
|
|
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|
#endif /* __ASSEMBLY__ */
|
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|
|
|
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
|
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
|
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|
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|
2015-11-30 20:36:28 -07:00
|
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/*
|
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|
* The normal case is that PTEs are 32-bits and we have a 1-page
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|
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* 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
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*
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* For any >32-bit physical address platform, we can use the following
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* two level page table layout where the pgdir is 8KB and the MS 13 bits
|
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|
* are an index to the second level table. The combined pgdir/pmd first
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* level has 2048 entries and the second level has 512 64-bit PTE entries.
|
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* -Matt
|
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*/
|
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/* PGDIR_SHIFT determines what a top-level page table entry can map */
|
2016-12-07 00:47:24 -07:00
|
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|
#define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
|
2015-11-30 20:36:28 -07:00
|
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|
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
|
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|
|
#define PGDIR_MASK (~(PGDIR_SIZE-1))
|
|
|
|
|
|
|
|
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
|
2019-04-26 10:23:31 -06:00
|
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#ifndef __ASSEMBLY__
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int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot);
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|
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#endif /* !__ASSEMBLY__ */
|
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|
|
|
2015-11-30 20:36:28 -07:00
|
|
|
/*
|
|
|
|
* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
|
|
|
|
* value (for now) on others, from where we can start layout kernel
|
|
|
|
* virtual space that goes below PKMAP and FIXMAP
|
|
|
|
*/
|
2019-04-26 10:23:31 -06:00
|
|
|
#include <asm/fixmap.h>
|
|
|
|
|
2015-11-30 20:36:28 -07:00
|
|
|
/*
|
|
|
|
* ioremap_bot starts at that address. Early ioremaps move down from there,
|
|
|
|
* until mem_init() at which point this becomes the top of the vmalloc
|
|
|
|
* and ioremap space
|
|
|
|
*/
|
2019-08-14 07:22:30 -06:00
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
|
|
#define IOREMAP_TOP PKMAP_BASE
|
2015-11-30 20:36:28 -07:00
|
|
|
#else
|
2019-08-14 07:22:30 -06:00
|
|
|
#define IOREMAP_TOP FIXADDR_START
|
2015-11-30 20:36:28 -07:00
|
|
|
#endif
|
|
|
|
|
2019-08-20 08:07:19 -06:00
|
|
|
/* PPC32 shares vmalloc area with ioremap */
|
|
|
|
#define IOREMAP_START VMALLOC_START
|
|
|
|
#define IOREMAP_END VMALLOC_END
|
|
|
|
|
2015-11-30 20:36:28 -07:00
|
|
|
/*
|
|
|
|
* Just any arbitrary offset to the start of the vmalloc VM area: the
|
|
|
|
* current 16MB value just means that there will be a 64MB "hole" after the
|
|
|
|
* physical memory until the kernel virtual memory starts. That means that
|
|
|
|
* any out-of-bounds memory accesses will hopefully be caught.
|
|
|
|
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
|
|
|
|
* area for the same reason. ;)
|
|
|
|
*
|
|
|
|
* We no longer map larger than phys RAM with the BATs so we don't have
|
|
|
|
* to worry about the VMALLOC_OFFSET causing problems. We do have to worry
|
|
|
|
* about clashes between our early calls to ioremap() that start growing down
|
|
|
|
* from ioremap_base being run into the VM area allocations (growing upwards
|
|
|
|
* from VMALLOC_START). For this reason we have ioremap_bot to check when
|
|
|
|
* we actually run into our mappings setup in the early boot with the VM
|
|
|
|
* system. This really does become a problem for machines with good amounts
|
|
|
|
* of RAM. -- Cort
|
|
|
|
*/
|
|
|
|
#define VMALLOC_OFFSET (0x1000000) /* 16M */
|
2019-02-21 12:08:49 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* With CONFIG_STRICT_KERNEL_RWX, kernel segments are set NX. But when modules
|
|
|
|
* are used, NX cannot be set on VMALLOC space. So vmalloc VM space and linear
|
|
|
|
* memory shall not share segments.
|
|
|
|
*/
|
|
|
|
#if defined(CONFIG_STRICT_KERNEL_RWX) && defined(CONFIG_MODULES)
|
|
|
|
#define VMALLOC_START ((_ALIGN((long)high_memory, 256L << 20) + VMALLOC_OFFSET) & \
|
|
|
|
~(VMALLOC_OFFSET - 1))
|
|
|
|
#else
|
2015-11-30 20:36:28 -07:00
|
|
|
#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
|
2019-02-21 12:08:49 -07:00
|
|
|
#endif
|
2015-11-30 20:36:28 -07:00
|
|
|
#define VMALLOC_END ioremap_bot
|
|
|
|
|
2015-11-30 20:36:31 -07:00
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#include <linux/sched.h>
|
|
|
|
#include <linux/threads.h>
|
|
|
|
|
2016-12-07 00:47:24 -07:00
|
|
|
/* Bits to mask out from a PGD to get to the PUD page */
|
|
|
|
#define PGD_MASKED_BITS 0
|
2015-11-30 20:36:31 -07:00
|
|
|
|
|
|
|
#define pte_ERROR(e) \
|
|
|
|
pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
|
|
|
|
(unsigned long long)pte_val(e))
|
|
|
|
#define pgd_ERROR(e) \
|
|
|
|
pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
|
2015-11-30 20:36:28 -07:00
|
|
|
/*
|
|
|
|
* Bits in a linux-style PTE. These match the bits in the
|
|
|
|
* (hardware-defined) PowerPC PTE as closely as possible.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define pte_clear(mm, addr, ptep) \
|
|
|
|
do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
|
|
|
|
|
|
|
|
#define pmd_none(pmd) (!pmd_val(pmd))
|
|
|
|
#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
|
|
|
|
#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
|
2015-11-30 20:36:35 -07:00
|
|
|
static inline void pmd_clear(pmd_t *pmdp)
|
|
|
|
{
|
|
|
|
*pmdp = __pmd(0);
|
|
|
|
}
|
|
|
|
|
2015-11-30 20:36:28 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* When flushing the tlb entry for a page, we also need to flush the hash
|
|
|
|
* table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
|
|
|
|
*/
|
|
|
|
extern int flush_hash_pages(unsigned context, unsigned long va,
|
|
|
|
unsigned long pmdval, int count);
|
|
|
|
|
|
|
|
/* Add an HPTE to the hash table */
|
|
|
|
extern void add_hash_page(unsigned context, unsigned long va,
|
|
|
|
unsigned long pmdval);
|
|
|
|
|
|
|
|
/* Flush an entry from the TLB/hash table */
|
|
|
|
extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
|
|
|
|
unsigned long address);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PTE updates. This function is called whenever an existing
|
|
|
|
* valid PTE is updated. This does -not- include set_pte_at()
|
|
|
|
* which nowadays only sets a new PTE.
|
|
|
|
*
|
|
|
|
* Depending on the type of MMU, we may need to use atomic updates
|
|
|
|
* and the PTE may be either 32 or 64 bit wide. In the later case,
|
|
|
|
* when using atomic updates, only the low part of the PTE is
|
|
|
|
* accessed atomically.
|
|
|
|
*
|
|
|
|
* In addition, on 44x, we also maintain a global flag indicating
|
|
|
|
* that an executable user mapping was modified, which is needed
|
|
|
|
* to properly flush the virtually tagged instruction cache of
|
|
|
|
* those implementations.
|
|
|
|
*/
|
|
|
|
#ifndef CONFIG_PTE_64BIT
|
|
|
|
static inline unsigned long pte_update(pte_t *p,
|
|
|
|
unsigned long clr,
|
|
|
|
unsigned long set)
|
|
|
|
{
|
|
|
|
unsigned long old, tmp;
|
|
|
|
|
|
|
|
__asm__ __volatile__("\
|
|
|
|
1: lwarx %0,0,%3\n\
|
|
|
|
andc %1,%0,%4\n\
|
|
|
|
or %1,%1,%5\n"
|
|
|
|
" stwcx. %1,0,%3\n\
|
|
|
|
bne- 1b"
|
|
|
|
: "=&r" (old), "=&r" (tmp), "=m" (*p)
|
|
|
|
: "r" (p), "r" (clr), "r" (set), "m" (*p)
|
|
|
|
: "cc" );
|
2015-11-30 20:36:31 -07:00
|
|
|
|
2015-11-30 20:36:28 -07:00
|
|
|
return old;
|
|
|
|
}
|
|
|
|
#else /* CONFIG_PTE_64BIT */
|
|
|
|
static inline unsigned long long pte_update(pte_t *p,
|
|
|
|
unsigned long clr,
|
|
|
|
unsigned long set)
|
|
|
|
{
|
|
|
|
unsigned long long old;
|
|
|
|
unsigned long tmp;
|
|
|
|
|
|
|
|
__asm__ __volatile__("\
|
|
|
|
1: lwarx %L0,0,%4\n\
|
|
|
|
lwzx %0,0,%3\n\
|
|
|
|
andc %1,%L0,%5\n\
|
|
|
|
or %1,%1,%6\n"
|
|
|
|
" stwcx. %1,0,%4\n\
|
|
|
|
bne- 1b"
|
|
|
|
: "=&r" (old), "=&r" (tmp), "=m" (*p)
|
|
|
|
: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
|
|
|
|
: "cc" );
|
2015-11-30 20:36:31 -07:00
|
|
|
|
2015-11-30 20:36:28 -07:00
|
|
|
return old;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PTE_64BIT */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 2.6 calls this without flushing the TLB entry; this is wrong
|
|
|
|
* for our hash-based implementation, we fix that up here.
|
|
|
|
*/
|
|
|
|
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
|
|
|
static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
|
|
|
|
{
|
|
|
|
unsigned long old;
|
|
|
|
old = pte_update(ptep, _PAGE_ACCESSED, 0);
|
|
|
|
if (old & _PAGE_HASHPTE) {
|
|
|
|
unsigned long ptephys = __pa(ptep) & PAGE_MASK;
|
|
|
|
flush_hash_pages(context, addr, ptephys, 1);
|
|
|
|
}
|
|
|
|
return (old & _PAGE_ACCESSED) != 0;
|
|
|
|
}
|
|
|
|
#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
|
|
|
|
__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
|
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
|
|
|
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
|
|
|
|
pte_t *ptep)
|
|
|
|
{
|
|
|
|
return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
|
|
|
|
}
|
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
|
|
|
|
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
|
|
|
|
pte_t *ptep)
|
|
|
|
{
|
2018-10-09 07:52:04 -06:00
|
|
|
pte_update(ptep, _PAGE_RW, 0);
|
2015-11-30 20:36:28 -07:00
|
|
|
}
|
|
|
|
|
2018-05-29 08:28:40 -06:00
|
|
|
static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
|
2016-11-27 23:17:02 -07:00
|
|
|
pte_t *ptep, pte_t entry,
|
2018-05-29 08:28:40 -06:00
|
|
|
unsigned long address,
|
|
|
|
int psize)
|
2015-11-30 20:36:28 -07:00
|
|
|
{
|
|
|
|
unsigned long set = pte_val(entry) &
|
2018-11-28 10:21:10 -07:00
|
|
|
(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
|
2015-11-30 20:36:28 -07:00
|
|
|
|
2018-10-09 07:52:04 -06:00
|
|
|
pte_update(ptep, 0, set);
|
2018-05-29 08:28:41 -06:00
|
|
|
|
|
|
|
flush_tlb_page(vma, address);
|
2015-11-30 20:36:28 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTE_SAME
|
|
|
|
#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
|
|
|
|
|
|
|
|
#define pmd_page_vaddr(pmd) \
|
2018-11-29 07:07:01 -07:00
|
|
|
((unsigned long)__va(pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
|
2015-11-30 20:36:28 -07:00
|
|
|
#define pmd_page(pmd) \
|
|
|
|
pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
|
|
|
|
|
|
|
|
/* to find an entry in a kernel page-table-directory */
|
|
|
|
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
|
|
|
|
|
|
|
|
/* to find an entry in a page-table-directory */
|
|
|
|
#define pgd_index(address) ((address) >> PGDIR_SHIFT)
|
|
|
|
#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
|
|
|
|
|
|
|
|
/* Find an entry in the third-level page table.. */
|
|
|
|
#define pte_index(address) \
|
|
|
|
(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
|
|
|
|
#define pte_offset_kernel(dir, addr) \
|
|
|
|
((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
|
|
|
|
#define pte_offset_map(dir, addr) \
|
2018-11-29 07:07:01 -07:00
|
|
|
((pte_t *)(kmap_atomic(pmd_page(*(dir))) + \
|
|
|
|
(pmd_page_vaddr(*(dir)) & ~PAGE_MASK)) + pte_index(addr))
|
2015-11-30 20:36:28 -07:00
|
|
|
#define pte_unmap(pte) kunmap_atomic(pte)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Encode and decode a swap entry.
|
|
|
|
* Note that the bits we use in a PTE for representing a swap entry
|
|
|
|
* must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used).
|
|
|
|
* -- paulus
|
|
|
|
*/
|
|
|
|
#define __swp_type(entry) ((entry).val & 0x1f)
|
|
|
|
#define __swp_offset(entry) ((entry).val >> 5)
|
|
|
|
#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
|
|
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
|
|
|
|
#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
|
|
|
|
|
2015-11-30 20:36:37 -07:00
|
|
|
/* Generic accessors to PTE bits */
|
|
|
|
static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);}
|
powerpc/hugetlb: fix page rights verification in gup_hugepte()
gup_hugepte() checks if pages are present and readable, and
when 'write' is set, also checks if the pages are writable.
Initially this was done by checking if _PAGE_PRESENT and
_PAGE_READ were set. In addition, _PAGE_WRITE was verified for write
accesses.
The problem is that we have to handle the three following cases:
1/ The target defines __PAGE_READ and __PAGE_WRITE
2/ The target defines __PAGE_RW
3/ The target defines __PAGE_RO
In case 1/, this is obvious
In case 2/, __PAGE_READ is defined as 0 and __PAGE_WRITE as __PAGE_RW
so it works as well.
But in case 3, __PAGE_RW is defined as 0, which means __PAGE_WRITE is 0
and then the test returns true (page writable) in all cases.
A first correction was attempted in commit 6b8cb66a6a7cc ("powerpc: Fix
usage of _PAGE_RO in hugepage"), but that fix is wrong:
instead of checking that the page is writable when write is requested,
it checks that the page is NOT writable when write is NOT requested.
This patch adds a new pte_read() helper to check whether a page is
readable or not. This avoids handling all possible cases in
gup_hugepte().
Then gup_hugepte() is modified to use pte_present(), pte_read()
and pte_write() instead of the raw flags.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-07-12 09:03:42 -06:00
|
|
|
static inline int pte_read(pte_t pte) { return 1; }
|
2015-11-30 20:36:37 -07:00
|
|
|
static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
|
|
|
|
static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
|
|
|
|
static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
|
|
|
|
static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
|
2018-11-28 10:21:10 -07:00
|
|
|
static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
|
2015-11-30 20:36:37 -07:00
|
|
|
|
|
|
|
static inline int pte_present(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_val(pte) & _PAGE_PRESENT;
|
|
|
|
}
|
|
|
|
|
2018-10-09 07:51:52 -06:00
|
|
|
static inline bool pte_hw_valid(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_val(pte) & _PAGE_PRESENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pte_hashpte(pte_t pte)
|
|
|
|
{
|
|
|
|
return !!(pte_val(pte) & _PAGE_HASHPTE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pte_ci(pte_t pte)
|
|
|
|
{
|
|
|
|
return !!(pte_val(pte) & _PAGE_NO_CACHE);
|
|
|
|
}
|
|
|
|
|
2017-12-03 19:19:12 -07:00
|
|
|
/*
|
|
|
|
* We only find page table entry in the last level
|
|
|
|
* Hence no need for other accessors
|
|
|
|
*/
|
|
|
|
#define pte_access_permitted pte_access_permitted
|
|
|
|
static inline bool pte_access_permitted(pte_t pte, bool write)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* A read-only access is controlled by _PAGE_USER bit.
|
|
|
|
* We have _PAGE_READ set for WRITE and EXECUTE
|
|
|
|
*/
|
2018-10-09 07:51:56 -06:00
|
|
|
if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
|
|
|
|
return false;
|
2017-12-03 19:19:12 -07:00
|
|
|
|
2018-10-09 07:51:56 -06:00
|
|
|
if (write && !pte_write(pte))
|
2017-12-03 19:19:12 -07:00
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2015-11-30 20:36:37 -07:00
|
|
|
/* Conversion functions: convert a page and protection to a page entry,
|
|
|
|
* and a page entry and page directory to the page they refer to.
|
|
|
|
*
|
|
|
|
* Even if PTEs can be unsigned long long, a PFN is always an unsigned
|
|
|
|
* long for now.
|
|
|
|
*/
|
|
|
|
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
|
|
|
|
{
|
|
|
|
return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
|
|
|
|
pgprot_val(pgprot));
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long pte_pfn(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_val(pte) >> PTE_RPN_SHIFT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Generic modifiers for PTE bits */
|
|
|
|
static inline pte_t pte_wrprotect(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) & ~_PAGE_RW);
|
|
|
|
}
|
|
|
|
|
2018-10-09 07:51:52 -06:00
|
|
|
static inline pte_t pte_exprotect(pte_t pte)
|
|
|
|
{
|
2018-11-28 10:21:10 -07:00
|
|
|
return __pte(pte_val(pte) & ~_PAGE_EXEC);
|
2018-10-09 07:51:52 -06:00
|
|
|
}
|
|
|
|
|
2015-11-30 20:36:37 -07:00
|
|
|
static inline pte_t pte_mkclean(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) & ~_PAGE_DIRTY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkold(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
|
|
|
|
}
|
|
|
|
|
2018-10-09 07:51:52 -06:00
|
|
|
static inline pte_t pte_mkexec(pte_t pte)
|
|
|
|
{
|
2018-11-28 10:21:10 -07:00
|
|
|
return __pte(pte_val(pte) | _PAGE_EXEC);
|
2018-10-09 07:51:52 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkpte(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte;
|
|
|
|
}
|
|
|
|
|
2015-11-30 20:36:37 -07:00
|
|
|
static inline pte_t pte_mkwrite(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) | _PAGE_RW);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkdirty(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) | _PAGE_DIRTY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkyoung(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) | _PAGE_ACCESSED);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkspecial(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) | _PAGE_SPECIAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkhuge(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte;
|
|
|
|
}
|
|
|
|
|
2018-10-09 07:51:52 -06:00
|
|
|
static inline pte_t pte_mkprivileged(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) & ~_PAGE_USER);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkuser(pte_t pte)
|
|
|
|
{
|
|
|
|
return __pte(pte_val(pte) | _PAGE_USER);
|
|
|
|
}
|
|
|
|
|
2015-11-30 20:36:37 -07:00
|
|
|
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|
|
|
{
|
|
|
|
return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* This low level function performs the actual PTE insertion
|
|
|
|
* Setting the PTE depends on the MMU type and other factors. It's
|
|
|
|
* an horrible mess that I'm not going to try to clean up now but
|
|
|
|
* I'm keeping it in one place rather than spread around
|
|
|
|
*/
|
|
|
|
static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|
|
|
pte_t *ptep, pte_t pte, int percpu)
|
|
|
|
{
|
2018-11-17 03:25:00 -07:00
|
|
|
#if defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
|
2015-11-30 20:36:37 -07:00
|
|
|
/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
|
|
|
|
* helper pte_update() which does an atomic update. We need to do that
|
|
|
|
* because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
|
|
|
|
* per-CPU PTE such as a kmap_atomic, we do a simple update preserving
|
|
|
|
* the hash bits instead (ie, same as the non-SMP case)
|
|
|
|
*/
|
|
|
|
if (percpu)
|
|
|
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
|
|
|
else
|
|
|
|
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
|
|
|
|
|
2018-11-17 03:25:00 -07:00
|
|
|
#elif defined(CONFIG_PTE_64BIT)
|
2015-11-30 20:36:37 -07:00
|
|
|
/* Second case is 32-bit with 64-bit PTE. In this case, we
|
|
|
|
* can just store as long as we do the two halves in the right order
|
|
|
|
* with a barrier in between. This is possible because we take care,
|
|
|
|
* in the hash code, to pre-invalidate if the PTE was already hashed,
|
|
|
|
* which synchronizes us with any concurrent invalidation.
|
|
|
|
* In the percpu case, we also fallback to the simple update preserving
|
|
|
|
* the hash bits
|
|
|
|
*/
|
|
|
|
if (percpu) {
|
|
|
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (pte_val(*ptep) & _PAGE_HASHPTE)
|
|
|
|
flush_hash_entry(mm, ptep, addr);
|
|
|
|
__asm__ __volatile__("\
|
|
|
|
stw%U0%X0 %2,%0\n\
|
|
|
|
eieio\n\
|
|
|
|
stw%U0%X0 %L2,%1"
|
|
|
|
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
|
|
|
: "r" (pte) : "memory");
|
|
|
|
|
2018-11-17 03:25:00 -07:00
|
|
|
#else
|
2015-11-30 20:36:37 -07:00
|
|
|
/* Third case is 32-bit hash table in UP mode, we need to preserve
|
|
|
|
* the _PAGE_HASHPTE bit since we may not have invalidated the previous
|
|
|
|
* translation in the hash yet (done in a subsequent flush_tlb_xxx())
|
|
|
|
* and see we need to keep track that this PTE needs invalidating
|
|
|
|
*/
|
|
|
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Macro to mark a page protection value as "uncacheable".
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
|
|
|
|
_PAGE_WRITETHRU)
|
|
|
|
|
|
|
|
#define pgprot_noncached pgprot_noncached
|
|
|
|
static inline pgprot_t pgprot_noncached(pgprot_t prot)
|
|
|
|
{
|
|
|
|
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
|
|
|
_PAGE_NO_CACHE | _PAGE_GUARDED);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define pgprot_noncached_wc pgprot_noncached_wc
|
|
|
|
static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
|
|
|
|
{
|
|
|
|
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
|
|
|
_PAGE_NO_CACHE);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define pgprot_cached pgprot_cached
|
|
|
|
static inline pgprot_t pgprot_cached(pgprot_t prot)
|
|
|
|
{
|
|
|
|
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
|
|
|
_PAGE_COHERENT);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define pgprot_cached_wthru pgprot_cached_wthru
|
|
|
|
static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
|
|
|
|
{
|
|
|
|
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
|
|
|
_PAGE_COHERENT | _PAGE_WRITETHRU);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define pgprot_cached_noncoherent pgprot_cached_noncoherent
|
|
|
|
static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
|
|
|
|
{
|
|
|
|
return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define pgprot_writecombine pgprot_writecombine
|
|
|
|
static inline pgprot_t pgprot_writecombine(pgprot_t prot)
|
|
|
|
{
|
|
|
|
return pgprot_noncached_wc(prot);
|
|
|
|
}
|
|
|
|
|
2015-11-30 20:36:28 -07:00
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
|
|
|
|
#endif /* _ASM_POWERPC_BOOK3S_32_PGTABLE_H */
|