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alistair23-linux/arch/arm/boot/dts/r8a7744.dtsi

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ARM: dts: r8a7744: Initial SoC device tree Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30 08:26:16 -07:00
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a7744 SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r8a7744-cpg-mssr.h>
#include <dt-bindings/power/r8a7744-sysc.h>
/ {
compatible = "renesas,r8a7744";
#address-cells = <2>;
#size-cells = <2>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
<1312500 1000000>,
<1125000 1000000>,
< 937500 1000000>,
< 750000 1000000>,
< 375000 1000000>;
};
L2_CA15: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
power-domains = <&sysc R8A7744_PD_CA15_SCU>;
};
};
/* External root clock */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@e6050000 {
reg = <0 0xe6050000 0 0x50>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
/* placeholder */
};
gpio1: gpio@e6051000 {
reg = <0 0xe6051000 0 0x50>;
#gpio-cells = <2>;
/* placeholder */
};
gpio2: gpio@e6052000 {
reg = <0 0xe6052000 0 0x50>;
#gpio-cells = <2>;
/* placeholder */
};
gpio6: gpio@e6055400 {
reg = <0 0xe6055400 0 0x50>;
#gpio-cells = <2>;
/* placeholder */
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7744";
reg = <0 0xe6060000 0 0x250>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7744-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&usb_extal_clk>;
clock-names = "extal", "usb_extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7744-rst";
reg = <0 0xe6160000 0 0x100>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7744-sysc";
reg = <0 0xe6180000 0 0x200>;
#power-domain-cells = <1>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x100>;
};
};
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
};
i2c2: i2c@e6530000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xe6530000 0 0x40>;
/* placeholder */
};
i2c5: i2c@e6528000 {
/* doesn't need pinmux */
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xe6528000 0 0x40>;
/* placeholder */
};
hsusb: usb@e6590000 {
reg = <0 0xe6590000 0 0x100>;
/* placeholder */
};
usbphy: usb-phy@e6590100 {
reg = <0 0xe6590100 0 0x100>;
/* placeholder */
};
ARM: dts: r8a7744: Add SYS-DMAC support Describe SYS-DMAC0/1 in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30 08:26:18 -07:00
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <15>;
};
dmac1: dma-controller@e6720000 {
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <15>;
};
ARM: dts: r8a7744: Initial SoC device tree Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30 08:26:16 -07:00
avb: ethernet@e6800000 {
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
/* placeholder */
};
scifb1: serial@e6c30000 {
reg = <0 0xe6c30000 0 0x100>;
/* placeholder */
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7744",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 0x40>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 721>;
status = "disabled";
};
scif1: serial@e6e68000 {
reg = <0 0xe6e68000 0 0x40>;
/* placeholder */
};
hscif1: serial@e62c8000 {
reg = <0 0xe62c8000 0 0x60>;
/* placeholder */
};
can0: can@e6e80000 {
reg = <0 0xe6e80000 0 0x1000>;
/* placeholder */
};
can1: can@e6e88000 {
reg = <0 0xe6e88000 0 0x1000>;
/* placeholder */
};
rcar_sound: sound@ec500000 {
reg = <0 0xec500000 0 0x1000>;
rcar_sound,dvc {
dvc0: dvc-0 {};
dvc1: dvc-1 {};
};
rcar_sound,src {
src2: src-2 {};
src3: src-3 {};
};
rcar_sound,ssi {
ssi0: ssi-0 {};
ssi1: ssi-1 {};
};
/* placeholder */
};
pci0: pci@ee090000 {
reg = <0 0xee090000 0 0xc00>;
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
/* placeholder */
};
pci1: pci@ee0d0000 {
reg = <0 0xee0d0000 0 0xc00>;
bus-range = <1 1>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
/* placeholder */
};
sdhi1: sd@ee140000 {
reg = <0 0xee140000 0 0x100>;
/* placeholder */
};
sdhi2: sd@ee160000 {
reg = <0 0xee160000 0 0x100>;
/* placeholder */
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
du: display@feb00000 {
reg = <0 0xfeb00000 0 0x40000>,
<0 0xfeb90000 0 0x1c>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
};
};
};
/* placeholder */
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};