2005-11-10 07:26:51 -07:00
|
|
|
/*
|
2006-10-03 15:01:26 -06:00
|
|
|
* linux/arch/arm/mach-omap2/irq.c
|
2005-11-10 07:26:51 -07:00
|
|
|
*
|
|
|
|
* Interrupt handler for OMAP2 boards.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2005 Nokia Corporation
|
|
|
|
* Author: Paul Mundt <paul.mundt@nokia.com>
|
|
|
|
*
|
|
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
|
|
* for more details.
|
|
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/interrupt.h>
|
2008-10-09 08:51:28 -06:00
|
|
|
#include <linux/io.h>
|
2008-08-05 09:14:15 -06:00
|
|
|
#include <mach/hardware.h>
|
2005-11-10 07:26:51 -07:00
|
|
|
#include <asm/mach/irq.h>
|
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
|
|
|
|
/* selected INTC register offsets */
|
|
|
|
|
|
|
|
#define INTC_REVISION 0x0000
|
|
|
|
#define INTC_SYSCONFIG 0x0010
|
|
|
|
#define INTC_SYSSTATUS 0x0014
|
2008-12-10 18:36:52 -07:00
|
|
|
#define INTC_SIR 0x0040
|
2008-10-09 08:51:28 -06:00
|
|
|
#define INTC_CONTROL 0x0048
|
2008-09-26 06:18:20 -06:00
|
|
|
#define INTC_PROTECTION 0x004C
|
|
|
|
#define INTC_IDLE 0x0050
|
|
|
|
#define INTC_THRESHOLD 0x0068
|
|
|
|
#define INTC_MIR0 0x0084
|
2008-10-09 08:51:28 -06:00
|
|
|
#define INTC_MIR_CLEAR0 0x0088
|
|
|
|
#define INTC_MIR_SET0 0x008c
|
|
|
|
#define INTC_PENDING_IRQ0 0x0098
|
|
|
|
/* Number of IRQ state bits in each MIR register */
|
|
|
|
#define IRQ_BITS_PER_REG 32
|
2005-11-10 07:26:51 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* OMAP2 has a number of different interrupt controllers, each interrupt
|
|
|
|
* controller is identified as its own "bank". Register definitions are
|
|
|
|
* fairly consistent for each bank, but not all registers are implemented
|
|
|
|
* for each bank.. when in doubt, consult the TRM.
|
|
|
|
*/
|
|
|
|
static struct omap_irq_bank {
|
2008-09-01 15:07:37 -06:00
|
|
|
void __iomem *base_reg;
|
2005-11-10 07:26:51 -07:00
|
|
|
unsigned int nr_irqs;
|
|
|
|
} __attribute__ ((aligned(4))) irq_banks[] = {
|
|
|
|
{
|
|
|
|
/* MPU INTC */
|
|
|
|
.nr_irqs = 96,
|
2008-10-06 06:49:36 -06:00
|
|
|
},
|
2005-11-10 07:26:51 -07:00
|
|
|
};
|
|
|
|
|
2008-09-26 06:18:20 -06:00
|
|
|
/* Structure to save interrupt controller context */
|
|
|
|
struct omap3_intc_regs {
|
|
|
|
u32 sysconfig;
|
|
|
|
u32 protection;
|
|
|
|
u32 idle;
|
|
|
|
u32 threshold;
|
|
|
|
u32 ilr[INTCPS_NR_IRQS];
|
|
|
|
u32 mir[INTCPS_NR_MIR_REGS];
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
|
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
/* INTC bank register get/set */
|
|
|
|
|
|
|
|
static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
|
|
|
|
{
|
|
|
|
__raw_writel(val, bank->base_reg + reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
|
|
|
|
{
|
|
|
|
return __raw_readl(bank->base_reg + reg);
|
|
|
|
}
|
|
|
|
|
2008-12-10 18:36:52 -07:00
|
|
|
static int previous_irq;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On 34xx we can get occasional spurious interrupts if the ack from
|
|
|
|
* an interrupt handler does not get posted before we unmask. Warn about
|
|
|
|
* the interrupt handlers that need to flush posted writes.
|
|
|
|
*/
|
|
|
|
static int omap_check_spurious(unsigned int irq)
|
|
|
|
{
|
|
|
|
u32 sir, spurious;
|
|
|
|
|
|
|
|
sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
|
2009-04-23 12:10:50 -06:00
|
|
|
spurious = sir >> 7;
|
2008-12-10 18:36:52 -07:00
|
|
|
|
2009-04-23 12:10:50 -06:00
|
|
|
if (spurious) {
|
2008-12-10 18:36:52 -07:00
|
|
|
printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
|
|
|
|
"posted write for irq %i\n",
|
|
|
|
irq, sir, previous_irq);
|
|
|
|
return spurious;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-10 07:26:51 -07:00
|
|
|
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
|
2010-11-29 02:39:59 -07:00
|
|
|
static void omap_ack_irq(struct irq_data *d)
|
2005-11-10 07:26:51 -07:00
|
|
|
{
|
2008-10-09 08:51:28 -06:00
|
|
|
intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
|
2005-11-10 07:26:51 -07:00
|
|
|
}
|
|
|
|
|
2010-11-29 02:39:59 -07:00
|
|
|
static void omap_mask_irq(struct irq_data *d)
|
2005-11-10 07:26:51 -07:00
|
|
|
{
|
2010-11-29 02:39:59 -07:00
|
|
|
unsigned int irq = d->irq;
|
2008-10-09 08:51:28 -06:00
|
|
|
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
|
2005-11-10 07:26:51 -07:00
|
|
|
|
2008-12-10 18:36:52 -07:00
|
|
|
if (cpu_is_omap34xx()) {
|
|
|
|
int spurious = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
|
|
|
|
* it is the highest irq number?
|
|
|
|
*/
|
|
|
|
if (irq == INT_34XX_GPT12_IRQ)
|
|
|
|
spurious = omap_check_spurious(irq);
|
|
|
|
|
|
|
|
if (!spurious)
|
|
|
|
previous_irq = irq;
|
|
|
|
}
|
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
irq &= (IRQ_BITS_PER_REG - 1);
|
2005-11-10 07:26:51 -07:00
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
|
2005-11-10 07:26:51 -07:00
|
|
|
}
|
|
|
|
|
2010-11-29 02:39:59 -07:00
|
|
|
static void omap_unmask_irq(struct irq_data *d)
|
2005-11-10 07:26:51 -07:00
|
|
|
{
|
2010-11-29 02:39:59 -07:00
|
|
|
unsigned int irq = d->irq;
|
2008-10-09 08:51:28 -06:00
|
|
|
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
|
2005-11-10 07:26:51 -07:00
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
irq &= (IRQ_BITS_PER_REG - 1);
|
2005-11-10 07:26:51 -07:00
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
|
2005-11-10 07:26:51 -07:00
|
|
|
}
|
|
|
|
|
2010-11-29 02:39:59 -07:00
|
|
|
static void omap_mask_ack_irq(struct irq_data *d)
|
2005-11-10 07:26:51 -07:00
|
|
|
{
|
2010-11-29 02:39:59 -07:00
|
|
|
omap_mask_irq(d);
|
|
|
|
omap_ack_irq(d);
|
2005-11-10 07:26:51 -07:00
|
|
|
}
|
|
|
|
|
2006-08-01 15:26:25 -06:00
|
|
|
static struct irq_chip omap_irq_chip = {
|
2010-11-29 02:39:59 -07:00
|
|
|
.name = "INTC",
|
|
|
|
.irq_ack = omap_mask_ack_irq,
|
|
|
|
.irq_mask = omap_mask_irq,
|
|
|
|
.irq_unmask = omap_unmask_irq,
|
2005-11-10 07:26:51 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
|
|
|
|
{
|
|
|
|
unsigned long tmp;
|
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
|
2008-09-01 15:07:37 -06:00
|
|
|
printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
|
2005-11-10 07:26:51 -07:00
|
|
|
"(revision %ld.%ld) with %d interrupts\n",
|
|
|
|
bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
|
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
|
2005-11-10 07:26:51 -07:00
|
|
|
tmp |= 1 << 1; /* soft reset */
|
2008-10-09 08:51:28 -06:00
|
|
|
intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
|
2005-11-10 07:26:51 -07:00
|
|
|
|
2008-10-09 08:51:28 -06:00
|
|
|
while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
|
2005-11-10 07:26:51 -07:00
|
|
|
/* Wait for reset to complete */;
|
2006-12-06 18:13:50 -07:00
|
|
|
|
|
|
|
/* Enable autoidle */
|
2008-10-09 08:51:28 -06:00
|
|
|
intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
|
2005-11-10 07:26:51 -07:00
|
|
|
}
|
|
|
|
|
2009-02-03 16:49:04 -07:00
|
|
|
int omap_irq_pending(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
|
|
|
|
struct omap_irq_bank *bank = irq_banks + i;
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
for (irq = 0; irq < bank->nr_irqs; irq += 32)
|
|
|
|
if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
|
|
|
|
((irq >> 5) << 5)))
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-10 07:26:51 -07:00
|
|
|
void __init omap_init_irq(void)
|
|
|
|
{
|
2008-10-16 07:33:18 -06:00
|
|
|
unsigned long nr_of_irqs = 0;
|
2005-11-10 07:26:51 -07:00
|
|
|
unsigned int nr_banks = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
|
2010-01-29 15:20:06 -07:00
|
|
|
unsigned long base = 0;
|
2005-11-10 07:26:51 -07:00
|
|
|
struct omap_irq_bank *bank = irq_banks + i;
|
|
|
|
|
2008-10-06 06:49:36 -06:00
|
|
|
if (cpu_is_omap24xx())
|
2009-10-19 16:25:13 -06:00
|
|
|
base = OMAP24XX_IC_BASE;
|
2008-10-09 08:51:41 -06:00
|
|
|
else if (cpu_is_omap34xx())
|
2009-10-19 16:25:13 -06:00
|
|
|
base = OMAP34XX_IC_BASE;
|
|
|
|
|
2010-01-29 15:20:06 -07:00
|
|
|
BUG_ON(!base);
|
|
|
|
|
2009-10-19 16:25:13 -06:00
|
|
|
/* Static mapping, never released */
|
|
|
|
bank->base_reg = ioremap(base, SZ_4K);
|
|
|
|
if (!bank->base_reg) {
|
|
|
|
printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
|
|
|
|
continue;
|
|
|
|
}
|
2008-10-09 08:51:28 -06:00
|
|
|
|
2005-11-10 07:26:51 -07:00
|
|
|
omap_irq_bank_init_one(bank);
|
|
|
|
|
2008-10-16 07:33:18 -06:00
|
|
|
nr_of_irqs += bank->nr_irqs;
|
2005-11-10 07:26:51 -07:00
|
|
|
nr_banks++;
|
|
|
|
}
|
|
|
|
|
|
|
|
printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
|
2008-10-16 07:33:18 -06:00
|
|
|
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
|
2005-11-10 07:26:51 -07:00
|
|
|
|
2008-10-16 07:33:18 -06:00
|
|
|
for (i = 0; i < nr_of_irqs; i++) {
|
2005-11-10 07:26:51 -07:00
|
|
|
set_irq_chip(i, &omap_irq_chip);
|
2006-11-23 04:41:32 -07:00
|
|
|
set_irq_handler(i, handle_level_irq);
|
2005-11-10 07:26:51 -07:00
|
|
|
set_irq_flags(i, IRQF_VALID);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-09-26 06:18:20 -06:00
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
|
|
void omap_intc_save_context(void)
|
|
|
|
{
|
|
|
|
int ind = 0, i = 0;
|
|
|
|
for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
|
|
|
|
struct omap_irq_bank *bank = irq_banks + ind;
|
|
|
|
intc_context[ind].sysconfig =
|
|
|
|
intc_bank_read_reg(bank, INTC_SYSCONFIG);
|
|
|
|
intc_context[ind].protection =
|
|
|
|
intc_bank_read_reg(bank, INTC_PROTECTION);
|
|
|
|
intc_context[ind].idle =
|
|
|
|
intc_bank_read_reg(bank, INTC_IDLE);
|
|
|
|
intc_context[ind].threshold =
|
|
|
|
intc_bank_read_reg(bank, INTC_THRESHOLD);
|
|
|
|
for (i = 0; i < INTCPS_NR_IRQS; i++)
|
|
|
|
intc_context[ind].ilr[i] =
|
2009-03-12 10:12:29 -06:00
|
|
|
intc_bank_read_reg(bank, (0x100 + 0x4*i));
|
2008-09-26 06:18:20 -06:00
|
|
|
for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
|
|
|
|
intc_context[ind].mir[i] =
|
|
|
|
intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
|
|
|
|
(0x20 * i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void omap_intc_restore_context(void)
|
|
|
|
{
|
|
|
|
int ind = 0, i = 0;
|
|
|
|
|
|
|
|
for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
|
|
|
|
struct omap_irq_bank *bank = irq_banks + ind;
|
|
|
|
intc_bank_write_reg(intc_context[ind].sysconfig,
|
|
|
|
bank, INTC_SYSCONFIG);
|
|
|
|
intc_bank_write_reg(intc_context[ind].sysconfig,
|
|
|
|
bank, INTC_SYSCONFIG);
|
|
|
|
intc_bank_write_reg(intc_context[ind].protection,
|
|
|
|
bank, INTC_PROTECTION);
|
|
|
|
intc_bank_write_reg(intc_context[ind].idle,
|
|
|
|
bank, INTC_IDLE);
|
|
|
|
intc_bank_write_reg(intc_context[ind].threshold,
|
|
|
|
bank, INTC_THRESHOLD);
|
|
|
|
for (i = 0; i < INTCPS_NR_IRQS; i++)
|
|
|
|
intc_bank_write_reg(intc_context[ind].ilr[i],
|
2009-03-12 10:12:29 -06:00
|
|
|
bank, (0x100 + 0x4*i));
|
2008-09-26 06:18:20 -06:00
|
|
|
for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
|
|
|
|
intc_bank_write_reg(intc_context[ind].mir[i],
|
|
|
|
&irq_banks[0], INTC_MIR0 + (0x20 * i));
|
|
|
|
}
|
|
|
|
/* MIRs are saved and restore with other PRCM registers */
|
|
|
|
}
|
2009-10-23 10:03:48 -06:00
|
|
|
|
|
|
|
void omap3_intc_suspend(void)
|
|
|
|
{
|
|
|
|
/* A pending interrupt would prevent OMAP from entering suspend */
|
|
|
|
omap_ack_irq(0);
|
|
|
|
}
|
2009-10-23 10:03:50 -06:00
|
|
|
|
|
|
|
void omap3_intc_prepare_idle(void)
|
|
|
|
{
|
2010-11-17 10:52:11 -07:00
|
|
|
/*
|
|
|
|
* Disable autoidle as it can stall interrupt controller,
|
|
|
|
* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
|
|
|
|
*/
|
2009-10-23 10:03:50 -06:00
|
|
|
intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
|
|
|
|
}
|
|
|
|
|
|
|
|
void omap3_intc_resume_idle(void)
|
|
|
|
{
|
|
|
|
/* Re-enable autoidle */
|
|
|
|
intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
|
|
|
|
}
|
2008-09-26 06:18:20 -06:00
|
|
|
#endif /* CONFIG_ARCH_OMAP3 */
|