2009-07-29 02:20:10 -06:00
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/*
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* flexcan.c - FLEXCAN CAN controller driver
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*
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* Copyright (c) 2005-2006 Varma Electronics Oy
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* Copyright (c) 2009 Sascha Hauer, Pengutronix
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* Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
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*
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* Based on code originally by Andrey Volkov <avolkov@varma-el.com>
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*
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* LICENCE:
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/netdevice.h>
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#include <linux/can.h>
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#include <linux/can/dev.h>
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#include <linux/can/error.h>
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2012-12-18 10:50:58 -07:00
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#include <linux/can/led.h>
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2015-05-10 07:26:58 -06:00
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#include <linux/can/rx-offload.h>
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2009-07-29 02:20:10 -06:00
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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2011-08-16 11:32:23 -06:00
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#include <linux/of.h>
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2012-06-28 02:21:35 -06:00
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#include <linux/of_device.h>
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2009-07-29 02:20:10 -06:00
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#include <linux/platform_device.h>
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2013-06-10 20:12:57 -06:00
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#include <linux/regulator/consumer.h>
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2009-07-29 02:20:10 -06:00
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#define DRV_NAME "flexcan"
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/* 8 for RX fifo and 2 error handling */
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#define FLEXCAN_NAPI_WEIGHT (8 + 2)
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/* FLEXCAN module configuration register (CANMCR) bits */
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#define FLEXCAN_MCR_MDIS BIT(31)
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#define FLEXCAN_MCR_FRZ BIT(30)
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#define FLEXCAN_MCR_FEN BIT(29)
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#define FLEXCAN_MCR_HALT BIT(28)
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#define FLEXCAN_MCR_NOT_RDY BIT(27)
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#define FLEXCAN_MCR_WAK_MSK BIT(26)
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#define FLEXCAN_MCR_SOFTRST BIT(25)
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#define FLEXCAN_MCR_FRZ_ACK BIT(24)
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#define FLEXCAN_MCR_SUPV BIT(23)
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#define FLEXCAN_MCR_SLF_WAK BIT(22)
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#define FLEXCAN_MCR_WRN_EN BIT(21)
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#define FLEXCAN_MCR_LPM_ACK BIT(20)
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#define FLEXCAN_MCR_WAK_SRC BIT(19)
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#define FLEXCAN_MCR_DOZE BIT(18)
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#define FLEXCAN_MCR_SRX_DIS BIT(17)
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2015-08-27 08:01:27 -06:00
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#define FLEXCAN_MCR_IRMQ BIT(16)
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2009-07-29 02:20:10 -06:00
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#define FLEXCAN_MCR_LPRIO_EN BIT(13)
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#define FLEXCAN_MCR_AEN BIT(12)
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2014-09-02 08:54:17 -06:00
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#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
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2015-08-06 06:53:57 -06:00
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#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
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#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
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#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
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#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
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2009-07-29 02:20:10 -06:00
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/* FLEXCAN control register (CANCTRL) bits */
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#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
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#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
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#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
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#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
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#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
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#define FLEXCAN_CTRL_ERR_MSK BIT(14)
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#define FLEXCAN_CTRL_CLK_SRC BIT(13)
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#define FLEXCAN_CTRL_LPB BIT(12)
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#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
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#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
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#define FLEXCAN_CTRL_SMP BIT(7)
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#define FLEXCAN_CTRL_BOFF_REC BIT(6)
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#define FLEXCAN_CTRL_TSYN BIT(5)
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#define FLEXCAN_CTRL_LBUF BIT(4)
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#define FLEXCAN_CTRL_LOM BIT(3)
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#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
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#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
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#define FLEXCAN_CTRL_ERR_STATE \
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(FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
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FLEXCAN_CTRL_BOFF_MSK)
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#define FLEXCAN_CTRL_ERR_ALL \
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(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
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2014-07-15 06:56:21 -06:00
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/* FLEXCAN control register 2 (CTRL2) bits */
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2014-09-23 03:03:01 -06:00
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#define FLEXCAN_CTRL2_ECRWRE BIT(29)
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#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
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#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
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#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
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#define FLEXCAN_CTRL2_MRP BIT(18)
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#define FLEXCAN_CTRL2_RRS BIT(17)
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#define FLEXCAN_CTRL2_EACEN BIT(16)
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2014-07-15 06:56:21 -06:00
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/* FLEXCAN memory error control register (MECR) bits */
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#define FLEXCAN_MECR_ECRWRDIS BIT(31)
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#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
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#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
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#define FLEXCAN_MECR_CEI_MSK BIT(16)
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#define FLEXCAN_MECR_HAERRIE BIT(15)
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#define FLEXCAN_MECR_FAERRIE BIT(14)
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#define FLEXCAN_MECR_EXTERRIE BIT(13)
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#define FLEXCAN_MECR_RERRDIS BIT(9)
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#define FLEXCAN_MECR_ECCDIS BIT(8)
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#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
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2009-07-29 02:20:10 -06:00
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/* FLEXCAN error and status register (ESR) bits */
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#define FLEXCAN_ESR_TWRN_INT BIT(17)
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#define FLEXCAN_ESR_RWRN_INT BIT(16)
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#define FLEXCAN_ESR_BIT1_ERR BIT(15)
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#define FLEXCAN_ESR_BIT0_ERR BIT(14)
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#define FLEXCAN_ESR_ACK_ERR BIT(13)
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#define FLEXCAN_ESR_CRC_ERR BIT(12)
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#define FLEXCAN_ESR_FRM_ERR BIT(11)
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#define FLEXCAN_ESR_STF_ERR BIT(10)
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#define FLEXCAN_ESR_TX_WRN BIT(9)
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#define FLEXCAN_ESR_RX_WRN BIT(8)
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#define FLEXCAN_ESR_IDLE BIT(7)
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#define FLEXCAN_ESR_TXRX BIT(6)
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#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
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#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
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#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
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#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
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#define FLEXCAN_ESR_BOFF_INT BIT(2)
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#define FLEXCAN_ESR_ERR_INT BIT(1)
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#define FLEXCAN_ESR_WAK_INT BIT(0)
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#define FLEXCAN_ESR_ERR_BUS \
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(FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
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FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
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FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
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#define FLEXCAN_ESR_ERR_STATE \
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(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
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#define FLEXCAN_ESR_ERR_ALL \
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(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
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2011-12-12 08:09:28 -07:00
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#define FLEXCAN_ESR_ALL_INT \
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(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
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FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
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2009-07-29 02:20:10 -06:00
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/* FLEXCAN interrupt flag register (IFLAG) bits */
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2014-09-03 08:47:22 -06:00
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/* Errata ERR005829 step7: Reserve first valid MB */
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2015-07-11 16:47:47 -06:00
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#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
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#define FLEXCAN_TX_MB_OFF_FIFO 9
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#define FLEXCAN_IFLAG_MB(x) BIT(x)
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2009-07-29 02:20:10 -06:00
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#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
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#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
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#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
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/* FLEXCAN message buffers */
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2014-09-16 04:39:28 -06:00
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#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
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#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
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#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
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2015-08-06 06:53:57 -06:00
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#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
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2014-09-16 04:39:28 -06:00
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#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
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#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
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#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
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#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
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#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
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2009-07-29 02:20:10 -06:00
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#define FLEXCAN_MB_CNT_SRR BIT(22)
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#define FLEXCAN_MB_CNT_IDE BIT(21)
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#define FLEXCAN_MB_CNT_RTR BIT(20)
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#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
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#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
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2015-08-06 06:53:57 -06:00
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#define FLEXCAN_TIMEOUT_US (50)
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2009-07-29 02:20:10 -06:00
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2015-08-06 06:53:57 -06:00
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/* FLEXCAN hardware feature flags
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2012-10-10 13:10:42 -06:00
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*
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* Below is some version info we got:
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2014-10-10 07:04:03 -06:00
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* SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
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* Filter? connected? detection ception in MB
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* MX25 FlexCAN2 03.00.00.00 no no no no
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* MX28 FlexCAN2 03.00.04.00 yes yes no no
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* MX35 FlexCAN2 03.00.00.00 no no no no
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* MX53 FlexCAN2 03.00.00.00 yes no no no
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* MX6s FlexCAN3 10.00.12.00 yes yes no yes
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* VF610 FlexCAN3 ? no yes yes yes?
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2012-10-10 13:10:42 -06:00
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*
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* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
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*/
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2015-05-08 07:22:36 -06:00
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#define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
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#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
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#define FLEXCAN_QUIRK_DISABLE_MECR BIT(3) /* Disble Memory error detection */
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2012-09-27 21:17:15 -06:00
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2009-07-29 02:20:10 -06:00
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/* Structure of the message buffer */
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struct flexcan_mb {
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u32 can_ctrl;
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u32 can_id;
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u32 data[2];
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};
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/* Structure of the hardware registers */
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struct flexcan_regs {
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u32 mcr; /* 0x00 */
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u32 ctrl; /* 0x04 */
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u32 timer; /* 0x08 */
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u32 _reserved1; /* 0x0c */
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u32 rxgmask; /* 0x10 */
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u32 rx14mask; /* 0x14 */
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u32 rx15mask; /* 0x18 */
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u32 ecr; /* 0x1c */
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u32 esr; /* 0x20 */
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u32 imask2; /* 0x24 */
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u32 imask1; /* 0x28 */
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u32 iflag2; /* 0x2c */
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u32 iflag1; /* 0x30 */
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2015-08-27 08:01:27 -06:00
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union { /* 0x34 */
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u32 gfwr_mx28; /* MX28, MX53 */
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u32 ctrl2; /* MX6, VF610 */
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};
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2012-06-28 02:21:35 -06:00
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u32 esr2; /* 0x38 */
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u32 imeur; /* 0x3c */
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u32 lrfr; /* 0x40 */
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u32 crcr; /* 0x44 */
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u32 rxfgmask; /* 0x48 */
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u32 rxfir; /* 0x4c */
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2014-07-15 06:56:21 -06:00
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u32 _reserved3[12]; /* 0x50 */
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2015-08-25 02:39:19 -06:00
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struct flexcan_mb mb[64]; /* 0x80 */
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2014-09-17 04:50:48 -06:00
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/* FIFO-mode:
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* MB
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* 0x080...0x08f 0 RX message buffer
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* 0x090...0x0df 1-5 reserverd
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* 0x0e0...0x0ff 6-7 8 entry ID table
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* (mx25, mx28, mx35, mx53)
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* 0x0e0...0x2df 6-7..37 8..128 entry ID table
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2015-08-06 06:53:57 -06:00
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* size conf'ed via ctrl2::RFFN
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2014-09-17 04:50:48 -06:00
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* (mx6, vf610)
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*/
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2015-08-27 08:01:27 -06:00
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u32 _reserved4[256]; /* 0x480 */
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u32 rximr[64]; /* 0x880 */
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u32 _reserved5[24]; /* 0x980 */
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u32 gfwr_mx6; /* 0x9e0 - MX6 */
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u32 _reserved6[63]; /* 0x9e4 */
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2014-07-15 06:56:21 -06:00
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u32 mecr; /* 0xae0 */
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u32 erriar; /* 0xae4 */
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u32 erridpr; /* 0xae8 */
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u32 errippr; /* 0xaec */
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u32 rerrar; /* 0xaf0 */
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u32 rerrdr; /* 0xaf4 */
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u32 rerrsynr; /* 0xaf8 */
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u32 errsr; /* 0xafc */
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2009-07-29 02:20:10 -06:00
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};
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2012-06-28 02:21:35 -06:00
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struct flexcan_devtype_data {
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2015-05-08 07:22:36 -06:00
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u32 quirks; /* quirks needed for different IP cores */
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2012-06-28 02:21:35 -06:00
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};
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2009-07-29 02:20:10 -06:00
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struct flexcan_priv {
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struct can_priv can;
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2015-05-10 07:26:58 -06:00
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struct can_rx_offload offload;
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2009-07-29 02:20:10 -06:00
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2015-05-08 01:32:58 -06:00
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struct flexcan_regs __iomem *regs;
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2015-07-11 16:47:47 -06:00
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struct flexcan_mb __iomem *tx_mb;
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struct flexcan_mb __iomem *tx_mb_reserved;
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u8 tx_mb_idx;
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2009-07-29 02:20:10 -06:00
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u32 reg_ctrl_default;
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2015-08-04 05:46:10 -06:00
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u32 reg_imask1_default;
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2009-07-29 02:20:10 -06:00
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2012-07-17 08:14:34 -06:00
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struct clk *clk_ipg;
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|
|
struct clk *clk_per;
|
2012-07-13 06:52:48 -06:00
|
|
|
const struct flexcan_devtype_data *devtype_data;
|
2013-06-10 20:12:57 -06:00
|
|
|
struct regulator *reg_xceiver;
|
2012-06-28 02:21:35 -06:00
|
|
|
};
|
|
|
|
|
2016-07-04 06:45:44 -06:00
|
|
|
static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
|
2015-05-08 07:22:36 -06:00
|
|
|
.quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
|
2012-06-28 02:21:35 -06:00
|
|
|
};
|
2015-08-06 06:53:57 -06:00
|
|
|
|
2016-07-04 06:45:44 -06:00
|
|
|
static const struct flexcan_devtype_data fsl_imx28_devtype_data;
|
2015-08-06 06:53:57 -06:00
|
|
|
|
2016-07-04 06:45:44 -06:00
|
|
|
static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
|
2015-05-08 07:22:36 -06:00
|
|
|
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG,
|
2009-07-29 02:20:10 -06:00
|
|
|
};
|
2015-08-06 06:53:57 -06:00
|
|
|
|
2016-07-04 06:45:44 -06:00
|
|
|
static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
|
2015-05-08 07:22:36 -06:00
|
|
|
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
|
2014-07-15 06:56:21 -06:00
|
|
|
};
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2012-07-16 04:58:31 -06:00
|
|
|
static const struct can_bittiming_const flexcan_bittiming_const = {
|
2009-07-29 02:20:10 -06:00
|
|
|
.name = DRV_NAME,
|
|
|
|
.tseg1_min = 4,
|
|
|
|
.tseg1_max = 16,
|
|
|
|
.tseg2_min = 2,
|
|
|
|
.tseg2_max = 8,
|
|
|
|
.sjw_max = 4,
|
|
|
|
.brp_min = 1,
|
|
|
|
.brp_max = 256,
|
|
|
|
.brp_inc = 1,
|
|
|
|
};
|
|
|
|
|
2015-08-06 06:53:57 -06:00
|
|
|
/* Abstract off the read/write for arm versus ppc. This
|
2014-01-14 03:44:09 -07:00
|
|
|
* assumes that PPC uses big-endian registers and everything
|
|
|
|
* else uses little-endian registers, independent of CPU
|
2015-08-06 06:53:57 -06:00
|
|
|
* endianness.
|
2011-08-16 11:32:20 -06:00
|
|
|
*/
|
2014-01-14 03:44:09 -07:00
|
|
|
#if defined(CONFIG_PPC)
|
2011-08-16 11:32:20 -06:00
|
|
|
static inline u32 flexcan_read(void __iomem *addr)
|
|
|
|
{
|
|
|
|
return in_be32(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void flexcan_write(u32 val, void __iomem *addr)
|
|
|
|
{
|
|
|
|
out_be32(addr, val);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline u32 flexcan_read(void __iomem *addr)
|
|
|
|
{
|
|
|
|
return readl(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void flexcan_write(u32 val, void __iomem *addr)
|
|
|
|
{
|
|
|
|
writel(val, addr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-02-28 09:18:27 -07:00
|
|
|
static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
|
|
|
|
{
|
|
|
|
if (!priv->reg_xceiver)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return regulator_enable(priv->reg_xceiver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
|
|
|
|
{
|
|
|
|
if (!priv->reg_xceiver)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return regulator_disable(priv->reg_xceiver);
|
|
|
|
}
|
|
|
|
|
2014-02-28 07:30:18 -07:00
|
|
|
static int flexcan_chip_enable(struct flexcan_priv *priv)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2014-02-28 07:30:18 -07:00
|
|
|
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
|
2009-07-29 02:20:10 -06:00
|
|
|
u32 reg;
|
|
|
|
|
2011-08-16 11:32:20 -06:00
|
|
|
reg = flexcan_read(®s->mcr);
|
2009-07-29 02:20:10 -06:00
|
|
|
reg &= ~FLEXCAN_MCR_MDIS;
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(reg, ®s->mcr);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2014-02-28 07:30:18 -07:00
|
|
|
while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
2014-08-27 04:02:16 -06:00
|
|
|
udelay(10);
|
2014-02-28 07:30:18 -07:00
|
|
|
|
|
|
|
if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
return 0;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
2014-02-28 07:30:18 -07:00
|
|
|
static int flexcan_chip_disable(struct flexcan_priv *priv)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2014-02-28 07:30:18 -07:00
|
|
|
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
|
2009-07-29 02:20:10 -06:00
|
|
|
u32 reg;
|
|
|
|
|
2011-08-16 11:32:20 -06:00
|
|
|
reg = flexcan_read(®s->mcr);
|
2009-07-29 02:20:10 -06:00
|
|
|
reg |= FLEXCAN_MCR_MDIS;
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(reg, ®s->mcr);
|
2014-02-28 07:30:18 -07:00
|
|
|
|
|
|
|
while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
2014-08-27 04:02:16 -06:00
|
|
|
udelay(10);
|
2014-02-28 07:30:18 -07:00
|
|
|
|
|
|
|
if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
return 0;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
2014-02-28 09:08:21 -07:00
|
|
|
static int flexcan_chip_freeze(struct flexcan_priv *priv)
|
|
|
|
{
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2014-02-28 09:08:21 -07:00
|
|
|
unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = flexcan_read(®s->mcr);
|
|
|
|
reg |= FLEXCAN_MCR_HALT;
|
|
|
|
flexcan_write(reg, ®s->mcr);
|
|
|
|
|
|
|
|
while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
2014-08-27 04:02:16 -06:00
|
|
|
udelay(100);
|
2014-02-28 09:08:21 -07:00
|
|
|
|
|
|
|
if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
|
|
|
|
{
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2014-02-28 09:08:21 -07:00
|
|
|
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = flexcan_read(®s->mcr);
|
|
|
|
reg &= ~FLEXCAN_MCR_HALT;
|
|
|
|
flexcan_write(reg, ®s->mcr);
|
|
|
|
|
|
|
|
while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
2014-08-27 04:02:16 -06:00
|
|
|
udelay(10);
|
2014-02-28 09:08:21 -07:00
|
|
|
|
|
|
|
if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-28 07:16:59 -07:00
|
|
|
static int flexcan_chip_softreset(struct flexcan_priv *priv)
|
|
|
|
{
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2014-02-28 07:16:59 -07:00
|
|
|
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
|
|
|
|
|
|
|
|
flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
|
|
|
|
while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
|
2014-08-27 04:02:16 -06:00
|
|
|
udelay(10);
|
2014-02-28 07:16:59 -07:00
|
|
|
|
|
|
|
if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-15 06:56:20 -06:00
|
|
|
static int __flexcan_get_berr_counter(const struct net_device *dev,
|
|
|
|
struct can_berr_counter *bec)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
|
|
|
const struct flexcan_priv *priv = netdev_priv(dev);
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2011-08-16 11:32:20 -06:00
|
|
|
u32 reg = flexcan_read(®s->ecr);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
bec->txerr = (reg >> 0) & 0xff;
|
|
|
|
bec->rxerr = (reg >> 8) & 0xff;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-15 06:56:20 -06:00
|
|
|
static int flexcan_get_berr_counter(const struct net_device *dev,
|
|
|
|
struct can_berr_counter *bec)
|
|
|
|
{
|
|
|
|
const struct flexcan_priv *priv = netdev_priv(dev);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = clk_prepare_enable(priv->clk_ipg);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = clk_prepare_enable(priv->clk_per);
|
|
|
|
if (err)
|
|
|
|
goto out_disable_ipg;
|
|
|
|
|
|
|
|
err = __flexcan_get_berr_counter(dev, bec);
|
|
|
|
|
|
|
|
clk_disable_unprepare(priv->clk_per);
|
|
|
|
out_disable_ipg:
|
|
|
|
clk_disable_unprepare(priv->clk_ipg);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
|
|
{
|
|
|
|
const struct flexcan_priv *priv = netdev_priv(dev);
|
|
|
|
struct can_frame *cf = (struct can_frame *)skb->data;
|
|
|
|
u32 can_id;
|
2015-08-06 06:53:57 -06:00
|
|
|
u32 data;
|
2014-09-23 03:18:11 -06:00
|
|
|
u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
if (can_dropped_invalid_skb(dev, skb))
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
|
|
|
netif_stop_queue(dev);
|
|
|
|
|
|
|
|
if (cf->can_id & CAN_EFF_FLAG) {
|
|
|
|
can_id = cf->can_id & CAN_EFF_MASK;
|
|
|
|
ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
|
|
|
|
} else {
|
|
|
|
can_id = (cf->can_id & CAN_SFF_MASK) << 18;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cf->can_id & CAN_RTR_FLAG)
|
|
|
|
ctrl |= FLEXCAN_MB_CNT_RTR;
|
|
|
|
|
|
|
|
if (cf->can_dlc > 0) {
|
2015-08-06 06:53:57 -06:00
|
|
|
data = be32_to_cpup((__be32 *)&cf->data[0]);
|
2015-07-11 16:47:47 -06:00
|
|
|
flexcan_write(data, &priv->tx_mb->data[0]);
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
if (cf->can_dlc > 3) {
|
2015-08-06 06:53:57 -06:00
|
|
|
data = be32_to_cpup((__be32 *)&cf->data[4]);
|
2015-07-11 16:47:47 -06:00
|
|
|
flexcan_write(data, &priv->tx_mb->data[1]);
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
2011-10-31 16:18:03 -06:00
|
|
|
can_put_echo_skb(skb, dev, 0);
|
|
|
|
|
2015-07-11 16:47:47 -06:00
|
|
|
flexcan_write(can_id, &priv->tx_mb->can_id);
|
|
|
|
flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2014-09-03 08:47:22 -06:00
|
|
|
/* Errata ERR005829 step8:
|
|
|
|
* Write twice INACTIVE(0x8) code to first MB.
|
|
|
|
*/
|
|
|
|
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
2015-07-11 16:47:47 -06:00
|
|
|
&priv->tx_mb_reserved->can_ctrl);
|
2014-09-03 08:47:22 -06:00
|
|
|
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
2015-07-11 16:47:47 -06:00
|
|
|
&priv->tx_mb_reserved->can_ctrl);
|
2014-09-03 08:47:22 -06:00
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
return NETDEV_TX_OK;
|
|
|
|
}
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
2017-01-18 03:38:26 -07:00
|
|
|
struct sk_buff *skb;
|
|
|
|
struct can_frame *cf;
|
2017-01-17 09:33:46 -07:00
|
|
|
bool rx_errors = false, tx_errors = false;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2017-01-18 03:38:26 -07:00
|
|
|
skb = alloc_can_err_skb(dev, &cf);
|
|
|
|
if (unlikely(!skb))
|
2015-05-10 07:26:58 -06:00
|
|
|
return;
|
2017-01-18 03:38:26 -07:00
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
|
|
|
|
|
|
|
|
if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "BIT1_ERR irq\n");
|
2009-07-29 02:20:10 -06:00
|
|
|
cf->data[2] |= CAN_ERR_PROT_BIT1;
|
2017-01-17 09:33:46 -07:00
|
|
|
tx_errors = true;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "BIT0_ERR irq\n");
|
2009-07-29 02:20:10 -06:00
|
|
|
cf->data[2] |= CAN_ERR_PROT_BIT0;
|
2017-01-17 09:33:46 -07:00
|
|
|
tx_errors = true;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "ACK_ERR irq\n");
|
2009-07-29 02:20:10 -06:00
|
|
|
cf->can_id |= CAN_ERR_ACK;
|
2015-11-21 10:41:20 -07:00
|
|
|
cf->data[3] = CAN_ERR_PROT_LOC_ACK;
|
2017-01-17 09:33:46 -07:00
|
|
|
tx_errors = true;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "CRC_ERR irq\n");
|
2009-07-29 02:20:10 -06:00
|
|
|
cf->data[2] |= CAN_ERR_PROT_BIT;
|
2015-11-21 10:41:20 -07:00
|
|
|
cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
|
2017-01-17 09:33:46 -07:00
|
|
|
rx_errors = true;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "FRM_ERR irq\n");
|
2009-07-29 02:20:10 -06:00
|
|
|
cf->data[2] |= CAN_ERR_PROT_FORM;
|
2017-01-17 09:33:46 -07:00
|
|
|
rx_errors = true;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
if (reg_esr & FLEXCAN_ESR_STF_ERR) {
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "STF_ERR irq\n");
|
2009-07-29 02:20:10 -06:00
|
|
|
cf->data[2] |= CAN_ERR_PROT_STUFF;
|
2017-01-17 09:33:46 -07:00
|
|
|
rx_errors = true;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
priv->can.can_stats.bus_error++;
|
|
|
|
if (rx_errors)
|
|
|
|
dev->stats.rx_errors++;
|
|
|
|
if (tx_errors)
|
|
|
|
dev->stats.tx_errors++;
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
|
|
|
struct sk_buff *skb;
|
|
|
|
struct can_frame *cf;
|
2017-01-18 03:25:41 -07:00
|
|
|
enum can_state new_state, rx_state, tx_state;
|
2009-07-29 02:20:10 -06:00
|
|
|
int flt;
|
2014-12-03 10:54:15 -07:00
|
|
|
struct can_berr_counter bec;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
|
|
|
|
if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
|
2014-12-03 10:54:15 -07:00
|
|
|
tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
|
2015-08-06 06:53:57 -06:00
|
|
|
CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
|
2014-12-03 10:54:15 -07:00
|
|
|
rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
|
2015-08-06 06:53:57 -06:00
|
|
|
CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
|
2014-12-03 10:54:15 -07:00
|
|
|
new_state = max(tx_state, rx_state);
|
2015-03-17 07:03:09 -06:00
|
|
|
} else {
|
2014-12-03 10:54:15 -07:00
|
|
|
__flexcan_get_berr_counter(dev, &bec);
|
2015-03-17 07:03:09 -06:00
|
|
|
new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
|
2015-08-06 06:53:57 -06:00
|
|
|
CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
|
2014-12-03 10:54:15 -07:00
|
|
|
rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
|
|
|
|
tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
|
|
|
|
}
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* state hasn't changed */
|
|
|
|
if (likely(new_state == priv->can.state))
|
2015-05-10 07:26:58 -06:00
|
|
|
return;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
skb = alloc_can_err_skb(dev, &cf);
|
|
|
|
if (unlikely(!skb))
|
2015-05-10 07:26:58 -06:00
|
|
|
return;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2014-12-03 10:54:15 -07:00
|
|
|
can_change_state(dev, cf, tx_state, rx_state);
|
|
|
|
|
|
|
|
if (unlikely(new_state == CAN_STATE_BUS_OFF))
|
|
|
|
can_bus_off(dev);
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
|
|
|
|
}
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
|
|
|
|
{
|
|
|
|
return container_of(offload, struct flexcan_priv, offload);
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
|
|
|
|
struct can_frame *cf,
|
|
|
|
u32 *timestamp, unsigned int n)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
2015-05-10 07:26:58 -06:00
|
|
|
struct flexcan_priv *priv = rx_offload_to_priv(offload);
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2015-05-10 07:26:58 -06:00
|
|
|
struct flexcan_mb __iomem *mb = ®s->mb[n];
|
|
|
|
u32 reg_ctrl, reg_id, reg_iflag1;
|
|
|
|
|
|
|
|
reg_iflag1 = flexcan_read(®s->iflag1);
|
|
|
|
if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
|
|
|
|
return 0;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2011-08-16 11:32:20 -06:00
|
|
|
reg_ctrl = flexcan_read(&mb->can_ctrl);
|
2015-05-10 07:26:58 -06:00
|
|
|
/* increase timstamp to full 32 bit */
|
|
|
|
*timestamp = reg_ctrl << 16;
|
|
|
|
|
2011-08-16 11:32:20 -06:00
|
|
|
reg_id = flexcan_read(&mb->can_id);
|
2009-07-29 02:20:10 -06:00
|
|
|
if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
|
|
|
|
cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
|
|
|
|
else
|
|
|
|
cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
|
|
|
|
|
|
|
|
if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
|
|
|
|
cf->can_id |= CAN_RTR_FLAG;
|
|
|
|
cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
|
|
|
|
|
2011-08-16 11:32:20 -06:00
|
|
|
*(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
|
|
|
|
*(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* mark as read */
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
|
|
|
|
flexcan_read(®s->timer);
|
2012-12-18 10:50:58 -07:00
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t flexcan_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct net_device *dev = dev_id;
|
|
|
|
struct net_device_stats *stats = &dev->stats;
|
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2017-01-18 03:45:14 -07:00
|
|
|
irqreturn_t handled = IRQ_NONE;
|
2009-07-29 02:20:10 -06:00
|
|
|
u32 reg_iflag1, reg_esr;
|
|
|
|
|
2011-08-16 11:32:20 -06:00
|
|
|
reg_iflag1 = flexcan_read(®s->iflag1);
|
2015-08-06 06:53:57 -06:00
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
/* reception interrupt */
|
|
|
|
if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
|
2017-01-18 03:45:14 -07:00
|
|
|
handled = IRQ_HANDLED;
|
2015-05-10 07:26:58 -06:00
|
|
|
can_rx_offload_irq_offload_fifo(&priv->offload);
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
/* FIFO overflow interrupt */
|
2009-07-29 02:20:10 -06:00
|
|
|
if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
|
2017-01-18 03:45:14 -07:00
|
|
|
handled = IRQ_HANDLED;
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
|
2009-07-29 02:20:10 -06:00
|
|
|
dev->stats.rx_over_errors++;
|
|
|
|
dev->stats.rx_errors++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* transmission complete interrupt */
|
2015-07-11 16:47:47 -06:00
|
|
|
if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
|
2017-01-18 03:45:14 -07:00
|
|
|
handled = IRQ_HANDLED;
|
2011-10-31 16:18:03 -06:00
|
|
|
stats->tx_bytes += can_get_echo_skb(dev, 0);
|
2009-07-29 02:20:10 -06:00
|
|
|
stats->tx_packets++;
|
2012-12-18 10:50:58 -07:00
|
|
|
can_led_event(dev, CAN_LED_EVENT_TX);
|
2015-08-06 06:53:57 -06:00
|
|
|
|
|
|
|
/* after sending a RTR frame MB is in RX mode */
|
2014-09-16 07:31:27 -06:00
|
|
|
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
2015-07-11 16:47:47 -06:00
|
|
|
&priv->tx_mb->can_ctrl);
|
|
|
|
flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
|
2009-07-29 02:20:10 -06:00
|
|
|
netif_wake_queue(dev);
|
|
|
|
}
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
reg_esr = flexcan_read(®s->esr);
|
|
|
|
|
2017-01-18 03:45:14 -07:00
|
|
|
/* ACK all bus error and state change IRQ sources */
|
|
|
|
if (reg_esr & FLEXCAN_ESR_ALL_INT) {
|
|
|
|
handled = IRQ_HANDLED;
|
|
|
|
flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
|
|
|
|
}
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
/* state change interrupt */
|
|
|
|
if (reg_esr & FLEXCAN_ESR_ERR_STATE)
|
|
|
|
flexcan_irq_state(dev, reg_esr);
|
|
|
|
|
|
|
|
/* bus error IRQ - handle if bus error reporting is activated */
|
|
|
|
if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
|
|
|
|
(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
|
|
|
|
flexcan_irq_bus_err(dev, reg_esr);
|
|
|
|
|
2017-01-18 03:45:14 -07:00
|
|
|
return handled;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void flexcan_set_bittiming(struct net_device *dev)
|
|
|
|
{
|
|
|
|
const struct flexcan_priv *priv = netdev_priv(dev);
|
|
|
|
const struct can_bittiming *bt = &priv->can.bittiming;
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2009-07-29 02:20:10 -06:00
|
|
|
u32 reg;
|
|
|
|
|
2011-08-16 11:32:20 -06:00
|
|
|
reg = flexcan_read(®s->ctrl);
|
2009-07-29 02:20:10 -06:00
|
|
|
reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
|
|
|
|
FLEXCAN_CTRL_RJW(0x3) |
|
|
|
|
FLEXCAN_CTRL_PSEG1(0x7) |
|
|
|
|
FLEXCAN_CTRL_PSEG2(0x7) |
|
|
|
|
FLEXCAN_CTRL_PROPSEG(0x7) |
|
|
|
|
FLEXCAN_CTRL_LPB |
|
|
|
|
FLEXCAN_CTRL_SMP |
|
|
|
|
FLEXCAN_CTRL_LOM);
|
|
|
|
|
|
|
|
reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
|
|
|
|
FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
|
|
|
|
FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
|
|
|
|
FLEXCAN_CTRL_RJW(bt->sjw - 1) |
|
|
|
|
FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
|
|
|
|
|
|
|
|
if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
|
|
|
|
reg |= FLEXCAN_CTRL_LPB;
|
|
|
|
if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
|
|
|
|
reg |= FLEXCAN_CTRL_LOM;
|
|
|
|
if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
|
|
|
|
reg |= FLEXCAN_CTRL_SMP;
|
|
|
|
|
2015-08-07 09:16:03 -06:00
|
|
|
netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(reg, ®s->ctrl);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* print chip status */
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
|
|
|
|
flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
2015-08-06 06:53:57 -06:00
|
|
|
/* flexcan_chip_start
|
2009-07-29 02:20:10 -06:00
|
|
|
*
|
|
|
|
* this functions is entered with clocks enabled
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static int flexcan_chip_start(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2014-09-23 03:03:01 -06:00
|
|
|
u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
|
2014-09-23 10:09:27 -06:00
|
|
|
int err, i;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* enable module */
|
2014-02-28 07:30:18 -07:00
|
|
|
err = flexcan_chip_enable(priv);
|
|
|
|
if (err)
|
|
|
|
return err;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* soft reset */
|
2014-02-28 07:16:59 -07:00
|
|
|
err = flexcan_chip_softreset(priv);
|
|
|
|
if (err)
|
2014-02-28 09:08:21 -07:00
|
|
|
goto out_chip_disable;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
flexcan_set_bittiming(dev);
|
|
|
|
|
2015-08-06 06:53:57 -06:00
|
|
|
/* MCR
|
2009-07-29 02:20:10 -06:00
|
|
|
*
|
|
|
|
* enable freeze
|
|
|
|
* enable fifo
|
|
|
|
* halt now
|
|
|
|
* only supervisor access
|
|
|
|
* enable warning int
|
2011-10-31 16:18:03 -06:00
|
|
|
* disable local echo
|
2015-08-31 13:03:29 -06:00
|
|
|
* enable individual RX masking
|
2015-08-31 13:32:34 -06:00
|
|
|
* choose format C
|
|
|
|
* set max mailbox number
|
2009-07-29 02:20:10 -06:00
|
|
|
*/
|
2011-08-16 11:32:20 -06:00
|
|
|
reg_mcr = flexcan_read(®s->mcr);
|
2013-10-04 02:52:36 -06:00
|
|
|
reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
|
2009-07-29 02:20:10 -06:00
|
|
|
reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
|
2015-08-31 13:32:34 -06:00
|
|
|
FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
|
2015-08-31 13:03:29 -06:00
|
|
|
FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
|
|
|
|
FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(reg_mcr, ®s->mcr);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2015-08-06 06:53:57 -06:00
|
|
|
/* CTRL
|
2009-07-29 02:20:10 -06:00
|
|
|
*
|
|
|
|
* disable timer sync feature
|
|
|
|
*
|
|
|
|
* disable auto busoff recovery
|
|
|
|
* transmit lowest buffer first
|
|
|
|
*
|
|
|
|
* enable tx and rx warning interrupt
|
|
|
|
* enable bus off interrupt
|
|
|
|
* (== FLEXCAN_CTRL_ERR_STATE)
|
|
|
|
*/
|
2011-08-16 11:32:20 -06:00
|
|
|
reg_ctrl = flexcan_read(®s->ctrl);
|
2009-07-29 02:20:10 -06:00
|
|
|
reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
|
|
|
|
reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
|
2012-09-27 21:17:15 -06:00
|
|
|
FLEXCAN_CTRL_ERR_STATE;
|
2015-08-06 06:53:57 -06:00
|
|
|
|
|
|
|
/* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
|
2012-09-27 21:17:15 -06:00
|
|
|
* on most Flexcan cores, too. Otherwise we don't get
|
|
|
|
* any error warning or passive interrupts.
|
|
|
|
*/
|
2015-05-08 07:22:36 -06:00
|
|
|
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
|
2012-09-27 21:17:15 -06:00
|
|
|
priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
|
|
|
|
reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
|
2014-08-12 02:47:21 -06:00
|
|
|
else
|
|
|
|
reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* save for later use */
|
|
|
|
priv->reg_ctrl_default = reg_ctrl;
|
2015-08-27 06:24:48 -06:00
|
|
|
/* leave interrupts disabled for now */
|
|
|
|
reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(reg_ctrl, ®s->ctrl);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2014-08-27 03:58:05 -06:00
|
|
|
/* clear and invalidate all mailboxes first */
|
2015-07-11 16:47:47 -06:00
|
|
|
for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
|
2014-08-27 03:58:05 -06:00
|
|
|
flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
|
2015-08-25 02:39:19 -06:00
|
|
|
®s->mb[i].can_ctrl);
|
2014-08-27 03:58:05 -06:00
|
|
|
}
|
|
|
|
|
2014-09-03 08:47:22 -06:00
|
|
|
/* Errata ERR005829: mark first TX mailbox as INACTIVE */
|
|
|
|
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
2015-07-11 16:47:47 -06:00
|
|
|
&priv->tx_mb_reserved->can_ctrl);
|
2014-09-03 08:47:22 -06:00
|
|
|
|
2014-09-16 04:39:28 -06:00
|
|
|
/* mark TX mailbox as INACTIVE */
|
|
|
|
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
2015-07-11 16:47:47 -06:00
|
|
|
&priv->tx_mb->can_ctrl);
|
2013-10-04 02:52:36 -06:00
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
/* acceptance mask/acceptance code (accept everything) */
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(0x0, ®s->rxgmask);
|
|
|
|
flexcan_write(0x0, ®s->rx14mask);
|
|
|
|
flexcan_write(0x0, ®s->rx15mask);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2015-05-08 07:22:36 -06:00
|
|
|
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
|
2012-06-28 02:21:35 -06:00
|
|
|
flexcan_write(0x0, ®s->rxfgmask);
|
|
|
|
|
2015-08-31 13:03:29 -06:00
|
|
|
/* clear acceptance filters */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
|
|
|
|
flexcan_write(0, ®s->rximr[i]);
|
|
|
|
|
2015-08-06 06:53:57 -06:00
|
|
|
/* On Vybrid, disable memory error detection interrupts
|
2014-07-15 06:56:21 -06:00
|
|
|
* and freeze mode.
|
|
|
|
* This also works around errata e5295 which generates
|
|
|
|
* false positive memory errors and put the device in
|
|
|
|
* freeze mode.
|
|
|
|
*/
|
2015-05-08 07:22:36 -06:00
|
|
|
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
|
2015-08-06 06:53:57 -06:00
|
|
|
/* Follow the protocol as described in "Detection
|
2014-07-15 06:56:21 -06:00
|
|
|
* and Correction of Memory Errors" to write to
|
|
|
|
* MECR register
|
|
|
|
*/
|
2014-09-23 03:03:01 -06:00
|
|
|
reg_ctrl2 = flexcan_read(®s->ctrl2);
|
|
|
|
reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
|
|
|
|
flexcan_write(reg_ctrl2, ®s->ctrl2);
|
2014-07-15 06:56:21 -06:00
|
|
|
|
|
|
|
reg_mecr = flexcan_read(®s->mecr);
|
|
|
|
reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
|
|
|
|
flexcan_write(reg_mecr, ®s->mecr);
|
|
|
|
reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
|
2015-08-06 06:53:57 -06:00
|
|
|
FLEXCAN_MECR_FANCEI_MSK);
|
2014-07-15 06:56:21 -06:00
|
|
|
flexcan_write(reg_mecr, ®s->mecr);
|
|
|
|
}
|
|
|
|
|
2014-02-28 09:18:27 -07:00
|
|
|
err = flexcan_transceiver_enable(priv);
|
|
|
|
if (err)
|
2014-02-28 09:08:21 -07:00
|
|
|
goto out_chip_disable;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* synchronize with the can bus */
|
2014-02-28 09:08:21 -07:00
|
|
|
err = flexcan_chip_unfreeze(priv);
|
|
|
|
if (err)
|
|
|
|
goto out_transceiver_disable;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
priv->can.state = CAN_STATE_ERROR_ACTIVE;
|
|
|
|
|
2015-08-27 06:24:48 -06:00
|
|
|
/* enable interrupts atomically */
|
|
|
|
disable_irq(dev->irq);
|
|
|
|
flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
|
2015-08-04 05:46:10 -06:00
|
|
|
flexcan_write(priv->reg_imask1_default, ®s->imask1);
|
2015-08-27 06:24:48 -06:00
|
|
|
enable_irq(dev->irq);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* print chip status */
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
|
|
|
|
flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2014-02-28 09:08:21 -07:00
|
|
|
out_transceiver_disable:
|
|
|
|
flexcan_transceiver_disable(priv);
|
|
|
|
out_chip_disable:
|
2009-07-29 02:20:10 -06:00
|
|
|
flexcan_chip_disable(priv);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2015-08-06 06:53:57 -06:00
|
|
|
/* flexcan_chip_stop
|
2009-07-29 02:20:10 -06:00
|
|
|
*
|
|
|
|
* this functions is entered with clocks enabled
|
|
|
|
*/
|
|
|
|
static void flexcan_chip_stop(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2014-02-28 09:08:21 -07:00
|
|
|
/* freeze + disable module */
|
|
|
|
flexcan_chip_freeze(priv);
|
|
|
|
flexcan_chip_disable(priv);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2014-02-19 04:00:51 -07:00
|
|
|
/* Disable all interrupts */
|
|
|
|
flexcan_write(0, ®s->imask1);
|
|
|
|
flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
|
|
|
|
®s->ctrl);
|
|
|
|
|
2014-02-28 09:18:27 -07:00
|
|
|
flexcan_transceiver_disable(priv);
|
2009-07-29 02:20:10 -06:00
|
|
|
priv->can.state = CAN_STATE_STOPPED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int flexcan_open(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
|
|
|
int err;
|
|
|
|
|
2013-07-22 09:41:40 -06:00
|
|
|
err = clk_prepare_enable(priv->clk_ipg);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = clk_prepare_enable(priv->clk_per);
|
|
|
|
if (err)
|
|
|
|
goto out_disable_ipg;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
err = open_candev(dev);
|
|
|
|
if (err)
|
2013-07-22 09:41:40 -06:00
|
|
|
goto out_disable_per;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
|
|
|
|
if (err)
|
|
|
|
goto out_close;
|
|
|
|
|
|
|
|
/* start chip and queuing */
|
|
|
|
err = flexcan_chip_start(dev);
|
|
|
|
if (err)
|
2014-02-28 06:52:01 -07:00
|
|
|
goto out_free_irq;
|
2012-12-18 10:50:58 -07:00
|
|
|
|
|
|
|
can_led_event(dev, CAN_LED_EVENT_OPEN);
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
can_rx_offload_enable(&priv->offload);
|
2009-07-29 02:20:10 -06:00
|
|
|
netif_start_queue(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2014-02-28 06:52:01 -07:00
|
|
|
out_free_irq:
|
|
|
|
free_irq(dev->irq, dev);
|
2009-07-29 02:20:10 -06:00
|
|
|
out_close:
|
|
|
|
close_candev(dev);
|
2013-07-22 09:41:40 -06:00
|
|
|
out_disable_per:
|
2012-07-17 08:14:34 -06:00
|
|
|
clk_disable_unprepare(priv->clk_per);
|
2013-07-22 09:41:40 -06:00
|
|
|
out_disable_ipg:
|
2012-07-17 08:14:34 -06:00
|
|
|
clk_disable_unprepare(priv->clk_ipg);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int flexcan_close(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
|
|
|
|
|
|
|
netif_stop_queue(dev);
|
2015-05-10 07:26:58 -06:00
|
|
|
can_rx_offload_disable(&priv->offload);
|
2009-07-29 02:20:10 -06:00
|
|
|
flexcan_chip_stop(dev);
|
|
|
|
|
|
|
|
free_irq(dev->irq, dev);
|
2012-07-17 08:14:34 -06:00
|
|
|
clk_disable_unprepare(priv->clk_per);
|
|
|
|
clk_disable_unprepare(priv->clk_ipg);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
close_candev(dev);
|
|
|
|
|
2012-12-18 10:50:58 -07:00
|
|
|
can_led_event(dev, CAN_LED_EVENT_STOP);
|
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case CAN_MODE_START:
|
|
|
|
err = flexcan_chip_start(dev);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
netif_wake_queue(dev);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct net_device_ops flexcan_netdev_ops = {
|
|
|
|
.ndo_open = flexcan_open,
|
|
|
|
.ndo_stop = flexcan_close,
|
|
|
|
.ndo_start_xmit = flexcan_start_xmit,
|
2014-03-07 01:23:41 -07:00
|
|
|
.ndo_change_mtu = can_change_mtu,
|
2009-07-29 02:20:10 -06:00
|
|
|
};
|
|
|
|
|
2012-12-03 07:22:44 -07:00
|
|
|
static int register_flexcandev(struct net_device *dev)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
2009-07-29 02:20:10 -06:00
|
|
|
u32 reg, err;
|
|
|
|
|
2013-07-22 09:41:40 -06:00
|
|
|
err = clk_prepare_enable(priv->clk_ipg);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = clk_prepare_enable(priv->clk_per);
|
|
|
|
if (err)
|
|
|
|
goto out_disable_ipg;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* select "bus clock", chip must be disabled */
|
2014-02-28 07:30:18 -07:00
|
|
|
err = flexcan_chip_disable(priv);
|
|
|
|
if (err)
|
|
|
|
goto out_disable_per;
|
2011-08-16 11:32:20 -06:00
|
|
|
reg = flexcan_read(®s->ctrl);
|
2009-07-29 02:20:10 -06:00
|
|
|
reg |= FLEXCAN_CTRL_CLK_SRC;
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(reg, ®s->ctrl);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2014-02-28 07:30:18 -07:00
|
|
|
err = flexcan_chip_enable(priv);
|
|
|
|
if (err)
|
|
|
|
goto out_chip_disable;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
/* set freeze, halt and activate FIFO, restrict register access */
|
2011-08-16 11:32:20 -06:00
|
|
|
reg = flexcan_read(®s->mcr);
|
2009-07-29 02:20:10 -06:00
|
|
|
reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
|
|
|
|
FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
|
2011-08-16 11:32:20 -06:00
|
|
|
flexcan_write(reg, ®s->mcr);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2015-08-06 06:53:57 -06:00
|
|
|
/* Currently we only support newer versions of this core
|
2009-07-29 02:20:10 -06:00
|
|
|
* featuring a RX FIFO. Older cores found on some Coldfire
|
|
|
|
* derivates are not yet supported.
|
|
|
|
*/
|
2011-08-16 11:32:20 -06:00
|
|
|
reg = flexcan_read(®s->mcr);
|
2009-07-29 02:20:10 -06:00
|
|
|
if (!(reg & FLEXCAN_MCR_FEN)) {
|
2012-02-01 03:02:05 -07:00
|
|
|
netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
|
2009-07-29 02:20:10 -06:00
|
|
|
err = -ENODEV;
|
2014-02-28 07:30:18 -07:00
|
|
|
goto out_chip_disable;
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
err = register_candev(dev);
|
|
|
|
|
|
|
|
/* disable core and turn off clocks */
|
2014-02-28 07:30:18 -07:00
|
|
|
out_chip_disable:
|
2009-07-29 02:20:10 -06:00
|
|
|
flexcan_chip_disable(priv);
|
2014-02-28 07:30:18 -07:00
|
|
|
out_disable_per:
|
2012-07-17 08:14:34 -06:00
|
|
|
clk_disable_unprepare(priv->clk_per);
|
2013-07-22 09:41:40 -06:00
|
|
|
out_disable_ipg:
|
2012-07-17 08:14:34 -06:00
|
|
|
clk_disable_unprepare(priv->clk_ipg);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2012-12-03 07:22:44 -07:00
|
|
|
static void unregister_flexcandev(struct net_device *dev)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
|
|
|
unregister_candev(dev);
|
|
|
|
}
|
|
|
|
|
2012-06-28 02:21:35 -06:00
|
|
|
static const struct of_device_id flexcan_of_match[] = {
|
|
|
|
{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
|
2013-10-03 15:51:55 -06:00
|
|
|
{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
|
|
|
|
{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
|
2014-07-15 06:56:21 -06:00
|
|
|
{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
|
2012-06-28 02:21:35 -06:00
|
|
|
{ /* sentinel */ },
|
|
|
|
};
|
2012-10-04 02:55:35 -06:00
|
|
|
MODULE_DEVICE_TABLE(of, flexcan_of_match);
|
2012-06-28 02:21:35 -06:00
|
|
|
|
|
|
|
static const struct platform_device_id flexcan_id_table[] = {
|
|
|
|
{ .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
|
|
|
|
{ /* sentinel */ },
|
|
|
|
};
|
2012-10-04 02:55:35 -06:00
|
|
|
MODULE_DEVICE_TABLE(platform, flexcan_id_table);
|
2012-06-28 02:21:35 -06:00
|
|
|
|
2012-12-03 07:22:44 -07:00
|
|
|
static int flexcan_probe(struct platform_device *pdev)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
2012-06-28 02:21:35 -06:00
|
|
|
const struct of_device_id *of_id;
|
2012-07-13 06:52:48 -06:00
|
|
|
const struct flexcan_devtype_data *devtype_data;
|
2009-07-29 02:20:10 -06:00
|
|
|
struct net_device *dev;
|
|
|
|
struct flexcan_priv *priv;
|
2015-03-22 10:35:52 -06:00
|
|
|
struct regulator *reg_xceiver;
|
2009-07-29 02:20:10 -06:00
|
|
|
struct resource *mem;
|
2012-07-17 08:14:34 -06:00
|
|
|
struct clk *clk_ipg = NULL, *clk_per = NULL;
|
2015-05-08 01:32:58 -06:00
|
|
|
struct flexcan_regs __iomem *regs;
|
2009-07-29 02:20:10 -06:00
|
|
|
int err, irq;
|
2011-08-16 11:32:23 -06:00
|
|
|
u32 clock_freq = 0;
|
|
|
|
|
2015-03-22 10:35:52 -06:00
|
|
|
reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
|
|
|
|
if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
else if (IS_ERR(reg_xceiver))
|
|
|
|
reg_xceiver = NULL;
|
|
|
|
|
2012-06-28 02:21:34 -06:00
|
|
|
if (pdev->dev.of_node)
|
|
|
|
of_property_read_u32(pdev->dev.of_node,
|
2015-08-06 06:53:57 -06:00
|
|
|
"clock-frequency", &clock_freq);
|
2011-08-16 11:32:23 -06:00
|
|
|
|
|
|
|
if (!clock_freq) {
|
2012-07-17 08:14:34 -06:00
|
|
|
clk_ipg = devm_clk_get(&pdev->dev, "ipg");
|
|
|
|
if (IS_ERR(clk_ipg)) {
|
|
|
|
dev_err(&pdev->dev, "no ipg clock defined\n");
|
2013-07-22 09:41:39 -06:00
|
|
|
return PTR_ERR(clk_ipg);
|
2012-07-17 08:14:34 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
clk_per = devm_clk_get(&pdev->dev, "per");
|
|
|
|
if (IS_ERR(clk_per)) {
|
|
|
|
dev_err(&pdev->dev, "no per clock defined\n");
|
2013-07-22 09:41:39 -06:00
|
|
|
return PTR_ERR(clk_per);
|
2011-08-16 11:32:23 -06:00
|
|
|
}
|
2013-11-25 14:15:20 -07:00
|
|
|
clock_freq = clk_get_rate(clk_per);
|
2009-07-29 02:20:10 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
2013-07-22 09:41:39 -06:00
|
|
|
if (irq <= 0)
|
|
|
|
return -ENODEV;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2015-05-08 01:32:58 -06:00
|
|
|
regs = devm_ioremap_resource(&pdev->dev, mem);
|
|
|
|
if (IS_ERR(regs))
|
|
|
|
return PTR_ERR(regs);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2012-06-28 02:21:35 -06:00
|
|
|
of_id = of_match_device(flexcan_of_match, &pdev->dev);
|
|
|
|
if (of_id) {
|
|
|
|
devtype_data = of_id->data;
|
2014-03-04 14:04:22 -07:00
|
|
|
} else if (platform_get_device_id(pdev)->driver_data) {
|
2012-06-28 02:21:35 -06:00
|
|
|
devtype_data = (struct flexcan_devtype_data *)
|
2014-03-04 14:04:22 -07:00
|
|
|
platform_get_device_id(pdev)->driver_data;
|
2012-06-28 02:21:35 -06:00
|
|
|
} else {
|
2013-07-22 09:41:39 -06:00
|
|
|
return -ENODEV;
|
2012-06-28 02:21:35 -06:00
|
|
|
}
|
|
|
|
|
2013-07-22 09:41:39 -06:00
|
|
|
dev = alloc_candev(sizeof(struct flexcan_priv), 1);
|
|
|
|
if (!dev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
dev->netdev_ops = &flexcan_netdev_ops;
|
|
|
|
dev->irq = irq;
|
2011-10-31 16:18:03 -06:00
|
|
|
dev->flags |= IFF_ECHO;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
priv = netdev_priv(dev);
|
2011-08-16 11:32:23 -06:00
|
|
|
priv->can.clock.freq = clock_freq;
|
2009-07-29 02:20:10 -06:00
|
|
|
priv->can.bittiming_const = &flexcan_bittiming_const;
|
|
|
|
priv->can.do_set_mode = flexcan_set_mode;
|
|
|
|
priv->can.do_get_berr_counter = flexcan_get_berr_counter;
|
|
|
|
priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
|
|
|
|
CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
|
|
|
|
CAN_CTRLMODE_BERR_REPORTING;
|
2015-05-08 01:32:58 -06:00
|
|
|
priv->regs = regs;
|
2012-07-17 08:14:34 -06:00
|
|
|
priv->clk_ipg = clk_ipg;
|
|
|
|
priv->clk_per = clk_per;
|
2012-06-28 02:21:35 -06:00
|
|
|
priv->devtype_data = devtype_data;
|
2015-03-22 10:35:52 -06:00
|
|
|
priv->reg_xceiver = reg_xceiver;
|
2013-06-10 20:12:57 -06:00
|
|
|
|
2015-07-11 16:47:47 -06:00
|
|
|
priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
|
|
|
|
priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
|
|
|
|
priv->tx_mb = ®s->mb[priv->tx_mb_idx];
|
|
|
|
|
2015-08-04 05:46:10 -06:00
|
|
|
priv->reg_imask1_default = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
|
|
|
|
FLEXCAN_IFLAG_RX_FIFO_AVAILABLE |
|
2015-07-11 16:47:47 -06:00
|
|
|
FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
|
2015-08-04 05:46:10 -06:00
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
priv->offload.mailbox_read = flexcan_mailbox_read;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
|
|
|
|
if (err)
|
|
|
|
goto failed_offload;
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
err = register_flexcandev(dev);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "registering netdev failed\n");
|
|
|
|
goto failed_register;
|
|
|
|
}
|
|
|
|
|
2012-12-18 10:50:58 -07:00
|
|
|
devm_can_led_init(dev);
|
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
|
2015-05-08 01:32:58 -06:00
|
|
|
priv->regs, dev->irq);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2015-05-10 07:26:58 -06:00
|
|
|
failed_offload:
|
2009-07-29 02:20:10 -06:00
|
|
|
failed_register:
|
|
|
|
free_candev(dev);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2012-12-03 07:22:44 -07:00
|
|
|
static int flexcan_remove(struct platform_device *pdev)
|
2009-07-29 02:20:10 -06:00
|
|
|
{
|
|
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
2014-02-28 12:48:36 -07:00
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
unregister_flexcandev(dev);
|
2015-05-10 07:26:58 -06:00
|
|
|
can_rx_offload_del(&priv->offload);
|
2010-10-20 23:07:58 -06:00
|
|
|
free_candev(dev);
|
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-05 11:10:44 -07:00
|
|
|
static int __maybe_unused flexcan_suspend(struct device *device)
|
2012-05-08 09:12:17 -06:00
|
|
|
{
|
2013-05-20 12:43:43 -06:00
|
|
|
struct net_device *dev = dev_get_drvdata(device);
|
2012-05-08 09:12:17 -06:00
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
2014-02-28 07:30:18 -07:00
|
|
|
int err;
|
2012-05-08 09:12:17 -06:00
|
|
|
|
|
|
|
if (netif_running(dev)) {
|
2016-08-17 09:41:08 -06:00
|
|
|
err = flexcan_chip_disable(priv);
|
|
|
|
if (err)
|
|
|
|
return err;
|
2012-05-08 09:12:17 -06:00
|
|
|
netif_stop_queue(dev);
|
|
|
|
netif_device_detach(dev);
|
|
|
|
}
|
|
|
|
priv->can.state = CAN_STATE_SLEEPING;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-05 11:10:44 -07:00
|
|
|
static int __maybe_unused flexcan_resume(struct device *device)
|
2012-05-08 09:12:17 -06:00
|
|
|
{
|
2013-05-20 12:43:43 -06:00
|
|
|
struct net_device *dev = dev_get_drvdata(device);
|
2012-05-08 09:12:17 -06:00
|
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
2016-08-17 09:41:08 -06:00
|
|
|
int err;
|
2012-05-08 09:12:17 -06:00
|
|
|
|
|
|
|
priv->can.state = CAN_STATE_ERROR_ACTIVE;
|
|
|
|
if (netif_running(dev)) {
|
|
|
|
netif_device_attach(dev);
|
|
|
|
netif_start_queue(dev);
|
2016-08-17 09:41:08 -06:00
|
|
|
err = flexcan_chip_enable(priv);
|
|
|
|
if (err)
|
|
|
|
return err;
|
2012-05-08 09:12:17 -06:00
|
|
|
}
|
2016-08-17 09:41:08 -06:00
|
|
|
return 0;
|
2012-05-08 09:12:17 -06:00
|
|
|
}
|
2013-05-20 12:43:43 -06:00
|
|
|
|
|
|
|
static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
|
2012-05-08 09:12:17 -06:00
|
|
|
|
2009-07-29 02:20:10 -06:00
|
|
|
static struct platform_driver flexcan_driver = {
|
2011-08-16 11:32:22 -06:00
|
|
|
.driver = {
|
|
|
|
.name = DRV_NAME,
|
2013-05-20 12:43:43 -06:00
|
|
|
.pm = &flexcan_pm_ops,
|
2011-08-16 11:32:22 -06:00
|
|
|
.of_match_table = flexcan_of_match,
|
|
|
|
},
|
2009-07-29 02:20:10 -06:00
|
|
|
.probe = flexcan_probe,
|
2012-12-03 07:22:44 -07:00
|
|
|
.remove = flexcan_remove,
|
2012-06-28 02:21:35 -06:00
|
|
|
.id_table = flexcan_id_table,
|
2009-07-29 02:20:10 -06:00
|
|
|
};
|
|
|
|
|
2011-11-27 08:42:31 -07:00
|
|
|
module_platform_driver(flexcan_driver);
|
2009-07-29 02:20:10 -06:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
|
|
|
|
"Marc Kleine-Budde <kernel@pengutronix.de>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
|