2009-01-02 14:33:00 -07:00
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/*
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* Copyright 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Jesse Barnes <jesse.barnes@intel.com>
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*/
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#include <linux/i2c.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2009-01-02 14:33:00 -07:00
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#include <linux/delay.h>
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#include "drmP.h"
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#include "drm.h"
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#include "drm_crtc.h"
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2009-05-05 10:52:46 -06:00
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#include "drm_edid.h"
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2009-01-02 14:33:00 -07:00
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#include "intel_drv.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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2010-08-04 06:50:23 -06:00
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struct intel_hdmi {
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struct intel_encoder base;
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2009-01-02 14:33:00 -07:00
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u32 sdvox_reg;
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2010-07-20 16:44:45 -06:00
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int ddc_bus;
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2011-02-21 15:23:52 -07:00
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uint32_t color_range;
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2009-04-01 23:13:26 -06:00
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bool has_hdmi_sink;
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2010-09-09 20:39:40 -06:00
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bool has_audio;
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2010-09-19 02:29:33 -06:00
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int force_audio;
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2011-08-03 10:22:55 -06:00
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void (*write_infoframe)(struct drm_encoder *encoder,
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struct dip_infoframe *frame);
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2009-01-02 14:33:00 -07:00
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};
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2010-08-04 06:50:23 -06:00
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static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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{
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2010-09-09 08:14:28 -06:00
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return container_of(encoder, struct intel_hdmi, base.base);
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2010-08-04 06:50:23 -06:00
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}
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2010-09-09 09:20:55 -06:00
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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
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{
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return container_of(intel_attached_encoder(connector),
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struct intel_hdmi, base);
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}
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2011-08-03 10:22:55 -06:00
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void intel_dip_infoframe_csum(struct dip_infoframe *frame)
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2010-09-24 13:44:32 -06:00
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{
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2011-08-03 10:22:55 -06:00
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uint8_t *data = (uint8_t *)frame;
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2010-09-24 13:44:32 -06:00
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uint8_t sum = 0;
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unsigned i;
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2011-08-03 10:22:55 -06:00
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frame->checksum = 0;
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frame->ecc = 0;
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2010-09-24 13:44:32 -06:00
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2011-09-21 23:46:00 -06:00
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for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
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2010-09-24 13:44:32 -06:00
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sum += data[i];
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2011-08-03 10:22:55 -06:00
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frame->checksum = 0x100 - sum;
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2010-09-24 13:44:32 -06:00
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}
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2011-08-03 10:22:55 -06:00
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static u32 intel_infoframe_index(struct dip_infoframe *frame)
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2010-09-24 13:44:32 -06:00
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{
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2011-08-03 10:22:55 -06:00
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u32 flags = 0;
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switch (frame->type) {
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case DIP_TYPE_AVI:
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flags |= VIDEO_DIP_SELECT_AVI;
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break;
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case DIP_TYPE_SPD:
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flags |= VIDEO_DIP_SELECT_SPD;
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break;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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break;
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}
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return flags;
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}
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static u32 intel_infoframe_flags(struct dip_infoframe *frame)
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{
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u32 flags = 0;
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switch (frame->type) {
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case DIP_TYPE_AVI:
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flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
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break;
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case DIP_TYPE_SPD:
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2011-09-21 23:46:00 -06:00
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flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC;
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2011-08-03 10:22:55 -06:00
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break;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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break;
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}
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return flags;
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}
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static void i9xx_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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2010-09-24 13:44:32 -06:00
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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2011-08-03 10:22:55 -06:00
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u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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2010-09-24 13:44:32 -06:00
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/* XXX first guess at handling video port, is this corrent? */
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if (intel_hdmi->sdvox_reg == SDVOB)
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port = VIDEO_DIP_PORT_B;
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else if (intel_hdmi->sdvox_reg == SDVOC)
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port = VIDEO_DIP_PORT_C;
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else
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return;
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2011-08-03 10:22:55 -06:00
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flags = intel_infoframe_index(frame);
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val &= ~VIDEO_DIP_SELECT_MASK;
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I915_WRITE(VIDEO_DIP_CTL, val | port | flags);
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2010-09-24 13:44:32 -06:00
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2011-08-03 10:22:55 -06:00
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for (i = 0; i < len; i += 4) {
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2010-09-24 13:44:32 -06:00
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I915_WRITE(VIDEO_DIP_DATA, *data);
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data++;
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}
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2011-08-03 10:22:55 -06:00
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flags |= intel_infoframe_flags(frame);
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I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
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2010-09-24 13:44:32 -06:00
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}
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2011-08-03 10:22:55 -06:00
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static void ironlake_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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2011-07-08 12:31:57 -06:00
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{
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2011-08-03 10:22:55 -06:00
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uint32_t *data = (uint32_t *)frame;
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2011-07-08 12:31:57 -06:00
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = encoder->crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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2011-08-03 10:22:55 -06:00
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 flags, val = I915_READ(reg);
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2011-07-08 12:31:57 -06:00
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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2011-08-03 10:22:55 -06:00
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flags = intel_infoframe_index(frame);
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2011-07-08 12:31:57 -06:00
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2011-09-21 23:46:00 -06:00
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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2011-08-03 10:22:55 -06:00
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2011-09-21 23:46:00 -06:00
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I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
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2011-08-03 10:22:55 -06:00
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for (i = 0; i < len; i += 4) {
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2011-07-08 12:31:57 -06:00
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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2011-08-03 10:22:55 -06:00
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flags |= intel_infoframe_flags(frame);
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I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
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}
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static void intel_set_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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if (!intel_hdmi->has_hdmi_sink)
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return;
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intel_dip_infoframe_csum(frame);
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intel_hdmi->write_infoframe(encoder, frame);
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}
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static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
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{
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struct dip_infoframe avi_if = {
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.type = DIP_TYPE_AVI,
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.ver = DIP_VERSION_AVI,
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.len = DIP_LEN_AVI,
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};
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intel_set_infoframe(encoder, &avi_if);
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2011-07-08 12:31:57 -06:00
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}
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2011-08-03 10:22:56 -06:00
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static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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{
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struct dip_infoframe spd_if;
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memset(&spd_if, 0, sizeof(spd_if));
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spd_if.type = DIP_TYPE_SPD;
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spd_if.ver = DIP_VERSION_SPD;
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spd_if.len = DIP_LEN_SPD;
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strcpy(spd_if.body.spd.vn, "Intel");
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strcpy(spd_if.body.spd.pd, "Integrated gfx");
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spd_if.body.spd.sdi = DIP_SPD_PC;
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intel_set_infoframe(encoder, &spd_if);
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}
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2009-01-02 14:33:00 -07:00
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static void intel_hdmi_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = encoder->crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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2010-08-04 06:50:23 -06:00
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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2009-01-02 14:33:00 -07:00
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u32 sdvox;
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2010-07-16 12:46:31 -06:00
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sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
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2011-06-24 13:19:19 -06:00
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if (!HAS_PCH_SPLIT(dev))
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sdvox |= intel_hdmi->color_range;
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2010-07-16 12:46:31 -06:00
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
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if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
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sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
|
2009-01-02 14:33:00 -07:00
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2011-06-24 13:19:25 -06:00
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if (intel_crtc->bpp > 24)
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sdvox |= COLOR_FORMAT_12bpc;
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else
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sdvox |= COLOR_FORMAT_8bpc;
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2010-09-09 20:39:40 -06:00
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/* Required on CPT */
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if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
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sdvox |= HDMI_MODE_SELECT;
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|
2010-09-24 13:44:32 -06:00
|
|
|
if (intel_hdmi->has_audio) {
|
drm/i915: pass ELD to HDMI/DP audio driver
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake,
SandyBridge/CougarPoint and IvyBridge/PantherPoint chips.
ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio
capabilities of the plugged monitor. It's built and passed to audio
driver in 2 steps:
(1) at get_modes time, parse EDID and save ELD to drm_connector.eld[]
(2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw
ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver
This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP.
Test scheme: plug in the HDMI/DP monitor, and run
cat /proc/asound/card0/eld*
to check if the monitor name, HDMI/DP type, etc. show up correctly.
Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always
reads 0 (reserved). Without knowing the port number, I worked it around
by setting the ELD_valid bit for ALL the three ports. It's tested to not
be a problem, because the audio driver will find invalid ELD data and
hence rightfully abort, even when it sees the ELD_valid indicator.
Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing.
CC: Zhao Yakui <yakui.zhao@intel.com>
CC: Wang Zhenyu <zhenyu.z.wang@intel.com>
CC: Jeremy Bush <contractfrombelow@gmail.com>
CC: Christopher White <c.white@pulseforce.com>
CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com>
CC: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-05 00:25:34 -06:00
|
|
|
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
|
|
|
|
pipe_name(intel_crtc->pipe));
|
2009-01-02 14:33:00 -07:00
|
|
|
sdvox |= SDVO_AUDIO_ENABLE;
|
2010-09-24 13:44:32 -06:00
|
|
|
sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
|
drm/i915: pass ELD to HDMI/DP audio driver
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake,
SandyBridge/CougarPoint and IvyBridge/PantherPoint chips.
ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio
capabilities of the plugged monitor. It's built and passed to audio
driver in 2 steps:
(1) at get_modes time, parse EDID and save ELD to drm_connector.eld[]
(2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw
ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver
This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP.
Test scheme: plug in the HDMI/DP monitor, and run
cat /proc/asound/card0/eld*
to check if the monitor name, HDMI/DP type, etc. show up correctly.
Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always
reads 0 (reserved). Without knowing the port number, I worked it around
by setting the ELD_valid bit for ALL the three ports. It's tested to not
be a problem, because the audio driver will find invalid ELD data and
hence rightfully abort, even when it sees the ELD_valid indicator.
Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing.
CC: Zhao Yakui <yakui.zhao@intel.com>
CC: Wang Zhenyu <zhenyu.z.wang@intel.com>
CC: Jeremy Bush <contractfrombelow@gmail.com>
CC: Christopher White <c.white@pulseforce.com>
CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com>
CC: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-05 00:25:34 -06:00
|
|
|
intel_write_eld(encoder, adjusted_mode);
|
2010-09-24 13:44:32 -06:00
|
|
|
}
|
2009-01-02 14:33:00 -07:00
|
|
|
|
2011-10-12 10:01:58 -06:00
|
|
|
if (HAS_PCH_CPT(dev))
|
|
|
|
sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
|
|
|
|
else if (intel_crtc->pipe == 1)
|
|
|
|
sdvox |= SDVO_PIPE_B_SELECT;
|
2009-01-02 14:33:00 -07:00
|
|
|
|
2010-08-04 06:50:23 -06:00
|
|
|
I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
|
|
|
|
POSTING_READ(intel_hdmi->sdvox_reg);
|
2010-09-24 13:44:32 -06:00
|
|
|
|
2011-08-03 10:22:55 -06:00
|
|
|
intel_hdmi_set_avi_infoframe(encoder);
|
2011-08-03 10:22:56 -06:00
|
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
2009-01-02 14:33:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-08-04 06:50:23 -06:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
2009-01-02 14:33:00 -07:00
|
|
|
u32 temp;
|
2011-12-09 05:42:20 -07:00
|
|
|
u32 enable_bits = SDVO_ENABLE;
|
|
|
|
|
|
|
|
if (intel_hdmi->has_audio)
|
|
|
|
enable_bits |= SDVO_AUDIO_ENABLE;
|
2009-01-02 14:33:00 -07:00
|
|
|
|
2010-08-04 06:50:23 -06:00
|
|
|
temp = I915_READ(intel_hdmi->sdvox_reg);
|
2009-11-02 00:52:30 -07:00
|
|
|
|
|
|
|
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
|
|
|
|
* we do this anyway which shows more stable in testing.
|
|
|
|
*/
|
2010-01-28 17:45:52 -07:00
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
2010-08-04 06:50:23 -06:00
|
|
|
I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
|
|
|
|
POSTING_READ(intel_hdmi->sdvox_reg);
|
2009-11-02 00:52:30 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (mode != DRM_MODE_DPMS_ON) {
|
2011-12-09 05:42:20 -07:00
|
|
|
temp &= ~enable_bits;
|
2009-01-02 14:33:00 -07:00
|
|
|
} else {
|
2011-12-09 05:42:20 -07:00
|
|
|
temp |= enable_bits;
|
2009-01-02 14:33:00 -07:00
|
|
|
}
|
2009-11-02 00:52:30 -07:00
|
|
|
|
2010-08-04 06:50:23 -06:00
|
|
|
I915_WRITE(intel_hdmi->sdvox_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->sdvox_reg);
|
2009-11-02 00:52:30 -07:00
|
|
|
|
|
|
|
/* HW workaround, need to write this twice for issue that may result
|
|
|
|
* in first write getting masked.
|
|
|
|
*/
|
2010-01-28 17:45:52 -07:00
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
2010-08-04 06:50:23 -06:00
|
|
|
I915_WRITE(intel_hdmi->sdvox_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->sdvox_reg);
|
2009-11-02 00:52:30 -07:00
|
|
|
}
|
2009-01-02 14:33:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_mode_valid(struct drm_connector *connector,
|
|
|
|
struct drm_display_mode *mode)
|
|
|
|
{
|
|
|
|
if (mode->clock > 165000)
|
|
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
if (mode->clock < 20000)
|
2011-05-30 04:48:26 -06:00
|
|
|
return MODE_CLOCK_LOW;
|
2009-01-02 14:33:00 -07:00
|
|
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
|
|
return MODE_NO_DBLESCAN;
|
|
|
|
|
|
|
|
return MODE_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
|
|
|
|
struct drm_display_mode *mode,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-05-05 10:52:46 -06:00
|
|
|
static enum drm_connector_status
|
2010-09-14 04:07:23 -06:00
|
|
|
intel_hdmi_detect(struct drm_connector *connector, bool force)
|
2009-04-01 23:13:26 -06:00
|
|
|
{
|
2010-09-09 09:20:55 -06:00
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
2010-07-20 16:44:45 -06:00
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
|
|
struct edid *edid;
|
2009-05-05 10:52:46 -06:00
|
|
|
enum drm_connector_status status = connector_status_disconnected;
|
2009-04-01 23:13:26 -06:00
|
|
|
|
2010-08-04 06:50:23 -06:00
|
|
|
intel_hdmi->has_hdmi_sink = false;
|
2010-09-09 20:39:40 -06:00
|
|
|
intel_hdmi->has_audio = false;
|
2010-07-20 16:44:45 -06:00
|
|
|
edid = drm_get_edid(connector,
|
|
|
|
&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
|
drm/i915: hdmi detection according by reading edid
According to investigations from windows team ,hw team,
and our test results on all 4x platofrms available
(gm45, g45b, q45, g45a, g45c, g41a, and g41), we find
currently Hot plug live status and Hot plug interrupt
detection are not reliable, sometime the results from
the two approaches are contradicts. So we chose edid
detection for hdmi output.
Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-16 03:23:09 -06:00
|
|
|
|
2009-05-05 10:52:46 -06:00
|
|
|
if (edid) {
|
2009-06-21 23:14:55 -06:00
|
|
|
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
|
2009-05-05 10:52:46 -06:00
|
|
|
status = connector_status_connected;
|
2010-08-04 06:50:23 -06:00
|
|
|
intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
|
2010-09-09 20:39:40 -06:00
|
|
|
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
|
2009-05-05 10:52:46 -06:00
|
|
|
}
|
2010-03-29 01:57:42 -06:00
|
|
|
connector->display_info.raw_edid = NULL;
|
2009-05-05 10:52:46 -06:00
|
|
|
kfree(edid);
|
2009-04-01 23:13:26 -06:00
|
|
|
}
|
2009-06-05 01:38:43 -06:00
|
|
|
|
2010-09-19 02:29:33 -06:00
|
|
|
if (status == connector_status_connected) {
|
|
|
|
if (intel_hdmi->force_audio)
|
|
|
|
intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
|
|
|
|
}
|
|
|
|
|
drm/i915: hdmi detection according by reading edid
According to investigations from windows team ,hw team,
and our test results on all 4x platofrms available
(gm45, g45b, q45, g45a, g45c, g41a, and g41), we find
currently Hot plug live status and Hot plug interrupt
detection are not reliable, sometime the results from
the two approaches are contradicts. So we chose edid
detection for hdmi output.
Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-16 03:23:09 -06:00
|
|
|
return status;
|
2009-01-02 14:33:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_get_modes(struct drm_connector *connector)
|
|
|
|
{
|
2010-09-09 09:20:55 -06:00
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
2010-07-20 16:44:45 -06:00
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
2009-01-02 14:33:00 -07:00
|
|
|
|
|
|
|
/* We should parse the EDID data and find out if it's an HDMI sink so
|
|
|
|
* we can send audio to it.
|
|
|
|
*/
|
|
|
|
|
2010-07-20 16:44:45 -06:00
|
|
|
return intel_ddc_get_modes(connector,
|
|
|
|
&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
|
2009-01-02 14:33:00 -07:00
|
|
|
}
|
|
|
|
|
2011-02-09 11:46:58 -07:00
|
|
|
static bool
|
|
|
|
intel_hdmi_detect_audio(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
|
|
struct edid *edid;
|
|
|
|
bool has_audio = false;
|
|
|
|
|
|
|
|
edid = drm_get_edid(connector,
|
|
|
|
&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
|
|
|
|
if (edid) {
|
|
|
|
if (edid->input & DRM_EDID_INPUT_DIGITAL)
|
|
|
|
has_audio = drm_detect_monitor_audio(edid);
|
|
|
|
|
|
|
|
connector->display_info.raw_edid = NULL;
|
|
|
|
kfree(edid);
|
|
|
|
}
|
|
|
|
|
|
|
|
return has_audio;
|
|
|
|
}
|
|
|
|
|
2010-09-19 02:29:33 -06:00
|
|
|
static int
|
|
|
|
intel_hdmi_set_property(struct drm_connector *connector,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t val)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
2011-02-21 15:23:52 -07:00
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
2010-09-19 02:29:33 -06:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = drm_connector_property_set_value(connector, property, val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-05-12 15:17:24 -06:00
|
|
|
if (property == dev_priv->force_audio_property) {
|
2011-02-09 11:46:58 -07:00
|
|
|
int i = val;
|
|
|
|
bool has_audio;
|
|
|
|
|
|
|
|
if (i == intel_hdmi->force_audio)
|
2010-09-19 02:29:33 -06:00
|
|
|
return 0;
|
|
|
|
|
2011-02-09 11:46:58 -07:00
|
|
|
intel_hdmi->force_audio = i;
|
2010-09-19 02:29:33 -06:00
|
|
|
|
2011-02-09 11:46:58 -07:00
|
|
|
if (i == 0)
|
|
|
|
has_audio = intel_hdmi_detect_audio(connector);
|
|
|
|
else
|
|
|
|
has_audio = i > 0;
|
|
|
|
|
|
|
|
if (has_audio == intel_hdmi->has_audio)
|
2010-09-19 02:29:33 -06:00
|
|
|
return 0;
|
|
|
|
|
2011-02-09 11:46:58 -07:00
|
|
|
intel_hdmi->has_audio = has_audio;
|
2010-09-19 02:29:33 -06:00
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2011-02-21 15:23:52 -07:00
|
|
|
if (property == dev_priv->broadcast_rgb_property) {
|
|
|
|
if (val == !!intel_hdmi->color_range)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2010-09-19 02:29:33 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
done:
|
|
|
|
if (intel_hdmi->base.base.crtc) {
|
|
|
|
struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
|
|
|
|
drm_crtc_helper_set_mode(crtc, &crtc->mode,
|
|
|
|
crtc->x, crtc->y,
|
|
|
|
crtc->fb);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-01-02 14:33:00 -07:00
|
|
|
static void intel_hdmi_destroy(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
drm_sysfs_connector_remove(connector);
|
|
|
|
drm_connector_cleanup(connector);
|
2010-03-29 01:57:42 -06:00
|
|
|
kfree(connector);
|
2009-01-02 14:33:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
|
|
|
|
.dpms = intel_hdmi_dpms,
|
|
|
|
.mode_fixup = intel_hdmi_mode_fixup,
|
|
|
|
.prepare = intel_encoder_prepare,
|
|
|
|
.mode_set = intel_hdmi_mode_set,
|
|
|
|
.commit = intel_encoder_commit,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
|
2009-05-30 21:42:28 -06:00
|
|
|
.dpms = drm_helper_connector_dpms,
|
2009-01-02 14:33:00 -07:00
|
|
|
.detect = intel_hdmi_detect,
|
|
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
2010-09-19 02:29:33 -06:00
|
|
|
.set_property = intel_hdmi_set_property,
|
2009-01-02 14:33:00 -07:00
|
|
|
.destroy = intel_hdmi_destroy,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
|
|
|
|
.get_modes = intel_hdmi_get_modes,
|
|
|
|
.mode_valid = intel_hdmi_mode_valid,
|
2010-09-09 09:20:55 -06:00
|
|
|
.best_encoder = intel_best_encoder,
|
2009-01-02 14:33:00 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
|
2010-08-04 06:50:23 -06:00
|
|
|
.destroy = intel_encoder_destroy,
|
2009-01-02 14:33:00 -07:00
|
|
|
};
|
|
|
|
|
2010-09-19 02:29:33 -06:00
|
|
|
static void
|
|
|
|
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
|
|
|
|
{
|
2011-05-12 15:17:24 -06:00
|
|
|
intel_attach_force_audio_property(connector);
|
2011-02-21 15:23:52 -07:00
|
|
|
intel_attach_broadcast_rgb_property(connector);
|
2010-09-19 02:29:33 -06:00
|
|
|
}
|
|
|
|
|
2009-01-02 14:33:00 -07:00
|
|
|
void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_connector *connector;
|
2010-03-25 12:11:14 -06:00
|
|
|
struct intel_encoder *intel_encoder;
|
2010-03-29 01:57:42 -06:00
|
|
|
struct intel_connector *intel_connector;
|
2010-08-04 06:50:23 -06:00
|
|
|
struct intel_hdmi *intel_hdmi;
|
2011-09-21 23:46:00 -06:00
|
|
|
int i;
|
2009-01-02 14:33:00 -07:00
|
|
|
|
2010-08-04 06:50:23 -06:00
|
|
|
intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
|
|
|
|
if (!intel_hdmi)
|
2009-01-02 14:33:00 -07:00
|
|
|
return;
|
2010-03-29 01:57:42 -06:00
|
|
|
|
|
|
|
intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
|
|
|
|
if (!intel_connector) {
|
2010-08-04 06:50:23 -06:00
|
|
|
kfree(intel_hdmi);
|
2010-03-29 01:57:42 -06:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-08-04 06:50:23 -06:00
|
|
|
intel_encoder = &intel_hdmi->base;
|
2010-09-15 05:03:59 -06:00
|
|
|
drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS);
|
|
|
|
|
2010-03-29 01:57:42 -06:00
|
|
|
connector = &intel_connector->base;
|
2009-01-02 14:33:00 -07:00
|
|
|
drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
|
2009-09-23 13:08:29 -06:00
|
|
|
DRM_MODE_CONNECTOR_HDMIA);
|
2009-01-02 14:33:00 -07:00
|
|
|
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
|
|
|
|
|
2010-03-25 12:11:14 -06:00
|
|
|
intel_encoder->type = INTEL_OUTPUT_HDMI;
|
2009-01-02 14:33:00 -07:00
|
|
|
|
2010-05-07 00:42:51 -06:00
|
|
|
connector->polled = DRM_CONNECTOR_POLL_HPD;
|
2012-01-28 06:49:26 -07:00
|
|
|
connector->interlace_allowed = 1;
|
2009-01-02 14:33:00 -07:00
|
|
|
connector->doublescan_allowed = 0;
|
2011-09-02 13:54:37 -06:00
|
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
2009-01-02 14:33:00 -07:00
|
|
|
|
|
|
|
/* Set up the DDC bus. */
|
2009-08-23 23:50:24 -06:00
|
|
|
if (sdvox_reg == SDVOB) {
|
2010-03-25 12:11:14 -06:00
|
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
|
2010-07-20 16:44:45 -06:00
|
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
|
2009-12-11 12:07:17 -07:00
|
|
|
dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
|
2009-08-23 23:50:24 -06:00
|
|
|
} else if (sdvox_reg == SDVOC) {
|
2010-03-25 12:11:14 -06:00
|
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
|
2010-07-20 16:44:45 -06:00
|
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
|
2009-12-11 12:07:17 -07:00
|
|
|
dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
|
2009-08-23 23:50:24 -06:00
|
|
|
} else if (sdvox_reg == HDMIB) {
|
2010-03-25 12:11:14 -06:00
|
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
|
2010-07-20 16:44:45 -06:00
|
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
|
2009-12-11 12:07:17 -07:00
|
|
|
dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
|
2009-08-23 23:50:24 -06:00
|
|
|
} else if (sdvox_reg == HDMIC) {
|
2010-03-25 12:11:14 -06:00
|
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
|
2010-07-20 16:44:45 -06:00
|
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
|
2009-12-11 12:07:17 -07:00
|
|
|
dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
|
2009-08-23 23:50:24 -06:00
|
|
|
} else if (sdvox_reg == HDMID) {
|
2010-03-25 12:11:14 -06:00
|
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
|
2010-07-20 16:44:45 -06:00
|
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
|
2009-12-11 12:07:17 -07:00
|
|
|
dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
|
2009-08-23 23:50:24 -06:00
|
|
|
}
|
2009-01-02 14:33:00 -07:00
|
|
|
|
2010-08-04 06:50:23 -06:00
|
|
|
intel_hdmi->sdvox_reg = sdvox_reg;
|
2009-01-02 14:33:00 -07:00
|
|
|
|
2011-09-21 23:46:00 -06:00
|
|
|
if (!HAS_PCH_SPLIT(dev)) {
|
2011-08-03 10:22:55 -06:00
|
|
|
intel_hdmi->write_infoframe = i9xx_write_infoframe;
|
2011-09-21 23:46:00 -06:00
|
|
|
I915_WRITE(VIDEO_DIP_CTL, 0);
|
|
|
|
} else {
|
2011-08-03 10:22:55 -06:00
|
|
|
intel_hdmi->write_infoframe = ironlake_write_infoframe;
|
2011-09-21 23:46:00 -06:00
|
|
|
for_each_pipe(i)
|
|
|
|
I915_WRITE(TVIDEO_DIP_CTL(i), 0);
|
|
|
|
}
|
2011-08-03 10:22:55 -06:00
|
|
|
|
2010-09-09 08:14:28 -06:00
|
|
|
drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
|
2009-01-02 14:33:00 -07:00
|
|
|
|
2010-09-19 02:29:33 -06:00
|
|
|
intel_hdmi_add_properties(intel_hdmi, connector);
|
|
|
|
|
2010-09-09 09:20:55 -06:00
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
2009-01-02 14:33:00 -07:00
|
|
|
drm_sysfs_connector_add(connector);
|
|
|
|
|
|
|
|
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
|
|
|
|
* 0xd. Failure to do so will result in spurious interrupts being
|
|
|
|
* generated on the port when a cable is not attached.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev) && !IS_GM45(dev)) {
|
|
|
|
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
|
|
|
|
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
|
|
|
|
}
|
|
|
|
}
|