2008-02-19 15:43:25 -07:00
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/*
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2005-04-16 16:20:36 -06:00
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* @file op_model_ppro.h
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2008-08-18 06:50:31 -06:00
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* Family 6 perfmon and architectural perfmon MSR operations
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2005-04-16 16:20:36 -06:00
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*
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* @remark Copyright 2002 OProfile authors
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2008-08-18 06:50:31 -06:00
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* @remark Copyright 2008 Intel Corporation
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2005-04-16 16:20:36 -06:00
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* @remark Read the file COPYING
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*
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* @author John Levon
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* @author Philippe Elie
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* @author Graydon Hoare
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2008-08-18 06:50:31 -06:00
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* @author Andi Kleen
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2009-05-25 07:10:32 -06:00
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* @author Robert Richter <robert.richter@amd.com>
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2005-04-16 16:20:36 -06:00
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*/
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#include <linux/oprofile.h>
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2008-08-18 06:50:31 -06:00
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#include <linux/slab.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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#include <asm/apic.h>
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2006-06-26 05:57:01 -06:00
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#include <asm/nmi.h>
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2008-02-19 15:43:25 -07:00
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2005-04-16 16:20:36 -06:00
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#include "op_x86_model.h"
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#include "op_counter.h"
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2008-08-18 06:50:31 -06:00
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static int num_counters = 2;
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static int counter_width = 32;
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2005-04-16 16:20:36 -06:00
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2009-05-25 07:10:32 -06:00
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#define MSR_PPRO_EVENTSEL_RESERVED ((0xFFFFFFFFULL<<32)|(1ULL<<21))
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2005-04-16 16:20:36 -06:00
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2011-08-01 09:08:59 -06:00
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static u64 reset_value[OP_MAX_COUNTER];
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2008-02-19 15:43:25 -07:00
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2010-03-23 13:01:54 -06:00
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static void ppro_shutdown(struct op_msrs const * const msrs)
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{
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int i;
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for (i = 0; i < num_counters; ++i) {
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if (!msrs->counters[i].addr)
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continue;
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release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
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release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
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}
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}
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2010-02-26 09:20:55 -07:00
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static int ppro_fill_in_addresses(struct op_msrs * const msrs)
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2005-04-16 16:20:36 -06:00
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{
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2006-09-26 02:52:26 -06:00
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int i;
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2008-08-18 06:50:31 -06:00
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for (i = 0; i < num_counters; i++) {
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2010-03-23 12:33:21 -06:00
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if (!reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
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2010-02-26 09:20:55 -07:00
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goto fail;
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2010-03-23 12:33:21 -06:00
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if (!reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) {
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release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
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2010-02-26 09:20:55 -07:00
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goto fail;
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2010-03-23 12:33:21 -06:00
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}
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/* both registers must be reserved */
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msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
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msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
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2010-02-26 09:20:55 -07:00
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continue;
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fail:
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if (!counter_config[i].enabled)
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continue;
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op_x86_warn_reserved(i);
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ppro_shutdown(msrs);
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return -EBUSY;
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2006-09-26 02:52:26 -06:00
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}
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2010-02-26 09:20:55 -07:00
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return 0;
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2005-04-16 16:20:36 -06:00
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}
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2009-05-25 11:31:44 -06:00
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static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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2005-04-16 16:20:36 -06:00
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{
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2009-05-25 07:10:32 -06:00
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u64 val;
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2005-04-16 16:20:36 -06:00
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int i;
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2016-03-29 09:41:54 -06:00
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if (boot_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
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2008-08-18 06:50:31 -06:00
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union cpuid10_eax eax;
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eax.full = cpuid_eax(0xa);
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2009-02-19 09:34:03 -07:00
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/*
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* For Core2 (family 6, model 15), don't reset the
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* counter width:
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*/
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if (!(eax.split.version_id == 0 &&
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2010-12-18 08:30:05 -07:00
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__this_cpu_read(cpu_info.x86) == 6 &&
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__this_cpu_read(cpu_info.x86_model) == 15)) {
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2009-02-19 09:34:03 -07:00
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if (counter_width < eax.split.bit_width)
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counter_width = eax.split.bit_width;
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}
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2008-08-18 06:50:31 -06:00
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}
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2005-04-16 16:20:36 -06:00
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/* clear all counters */
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2009-07-07 11:25:39 -06:00
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for (i = 0; i < num_counters; ++i) {
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2010-02-26 09:20:55 -07:00
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if (!msrs->controls[i].addr)
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2006-09-26 02:52:26 -06:00
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continue;
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2009-05-25 07:10:32 -06:00
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rdmsrl(msrs->controls[i].addr, val);
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2010-03-01 06:21:23 -07:00
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if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
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2010-02-23 10:14:58 -07:00
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op_x86_warn_in_use(i);
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2009-05-25 07:10:32 -06:00
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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2010-03-23 12:33:21 -06:00
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/*
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* avoid a false detection of ctr overflows in NMI *
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* handler
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*/
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2008-08-18 06:50:31 -06:00
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wrmsrl(msrs->counters[i].addr, -1LL);
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2005-04-16 16:20:36 -06:00
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}
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/* enable active counters */
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2008-08-18 06:50:31 -06:00
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for (i = 0; i < num_counters; ++i) {
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2009-06-03 18:36:44 -06:00
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if (counter_config[i].enabled && msrs->counters[i].addr) {
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2005-04-16 16:20:36 -06:00
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reset_value[i] = counter_config[i].count;
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2008-08-18 06:50:31 -06:00
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wrmsrl(msrs->counters[i].addr, -reset_value[i]);
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2009-05-25 07:10:32 -06:00
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[i]);
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wrmsrl(msrs->controls[i].addr, val);
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2006-09-26 02:52:26 -06:00
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} else {
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reset_value[i] = 0;
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2005-04-16 16:20:36 -06:00
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}
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}
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}
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2008-02-19 15:43:25 -07:00
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2005-04-16 16:20:36 -06:00
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static int ppro_check_ctrs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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2008-11-07 06:02:49 -07:00
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u64 val;
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2005-04-16 16:20:36 -06:00
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int i;
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2008-02-19 15:43:25 -07:00
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2009-07-07 11:25:39 -06:00
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for (i = 0; i < num_counters; ++i) {
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2006-09-26 02:52:26 -06:00
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if (!reset_value[i])
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continue;
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2008-11-07 06:02:49 -07:00
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rdmsrl(msrs->counters[i].addr, val);
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2009-05-25 09:59:06 -06:00
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if (val & (1ULL << (counter_width - 1)))
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continue;
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oprofile_add_sample(regs, i);
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wrmsrl(msrs->counters[i].addr, -reset_value[i]);
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2005-04-16 16:20:36 -06:00
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}
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/* Only P6 based Pentium M need to re-unmask the apic vector but it
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* doesn't hurt other P6 variant */
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apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
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/* We can't work out if we really handled an interrupt. We
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* might have caught a *second* counter just after overflowing
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* the interrupt for this counter then arrives
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* and we don't find a counter that's overflowed, so we
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* would return 0 and get dazed + confused. Instead we always
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* assume we found an overflow. This sucks.
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*/
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return 1;
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}
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2008-02-19 15:43:25 -07:00
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2005-04-16 16:20:36 -06:00
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static void ppro_start(struct op_msrs const * const msrs)
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{
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2009-05-25 10:11:52 -06:00
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u64 val;
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2006-09-29 03:00:01 -06:00
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int i;
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2006-09-26 02:52:26 -06:00
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2008-08-18 06:50:31 -06:00
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for (i = 0; i < num_counters; ++i) {
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2006-09-29 03:00:01 -06:00
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if (reset_value[i]) {
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2009-05-25 10:11:52 -06:00
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rdmsrl(msrs->controls[i].addr, val);
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2010-03-01 06:21:23 -07:00
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val |= ARCH_PERFMON_EVENTSEL_ENABLE;
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2009-05-25 10:11:52 -06:00
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wrmsrl(msrs->controls[i].addr, val);
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2006-09-29 03:00:01 -06:00
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}
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2006-09-26 02:52:26 -06:00
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}
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2005-04-16 16:20:36 -06:00
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}
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static void ppro_stop(struct op_msrs const * const msrs)
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{
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2009-05-25 10:11:52 -06:00
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u64 val;
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2006-09-29 03:00:01 -06:00
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int i;
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2006-09-26 02:52:26 -06:00
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2008-08-18 06:50:31 -06:00
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for (i = 0; i < num_counters; ++i) {
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2006-09-29 03:00:01 -06:00
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if (!reset_value[i])
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continue;
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2009-05-25 10:11:52 -06:00
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rdmsrl(msrs->controls[i].addr, val);
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2010-03-01 06:21:23 -07:00
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val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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2009-05-25 10:11:52 -06:00
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wrmsrl(msrs->controls[i].addr, val);
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2006-09-26 02:52:26 -06:00
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}
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}
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2009-07-09 07:12:35 -06:00
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struct op_x86_model_spec op_ppro_spec = {
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2009-05-14 09:10:52 -06:00
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.num_counters = 2,
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.num_controls = 2,
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2009-05-25 07:10:32 -06:00
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.reserved = MSR_PPRO_EVENTSEL_RESERVED,
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2008-10-15 14:19:41 -06:00
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.fill_in_addresses = &ppro_fill_in_addresses,
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.setup_ctrs = &ppro_setup_ctrs,
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.check_ctrs = &ppro_check_ctrs,
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.start = &ppro_start,
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.stop = &ppro_stop,
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.shutdown = &ppro_shutdown
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2008-08-18 06:50:31 -06:00
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};
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/*
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* Architectural performance monitoring.
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*
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* Newer Intel CPUs (Core1+) have support for architectural
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* events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
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* The advantage of this is that it can be done without knowing about
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* the specific CPU.
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*/
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2008-10-12 13:12:34 -06:00
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static void arch_perfmon_setup_counters(void)
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2008-08-18 06:50:31 -06:00
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{
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union cpuid10_eax eax;
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eax.full = cpuid_eax(0xa);
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/* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
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2017-11-07 10:53:07 -07:00
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if (eax.split.version_id == 0 && boot_cpu_data.x86 == 6 &&
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boot_cpu_data.x86_model == 15) {
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2008-08-18 06:50:31 -06:00
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eax.split.version_id = 2;
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2010-03-29 10:36:50 -06:00
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eax.split.num_counters = 2;
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2008-08-18 06:50:31 -06:00
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eax.split.bit_width = 40;
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}
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2011-08-16 15:39:53 -06:00
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num_counters = min((int)eax.split.num_counters, OP_MAX_COUNTER);
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2008-08-18 06:50:31 -06:00
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op_arch_perfmon_spec.num_counters = num_counters;
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op_arch_perfmon_spec.num_controls = num_counters;
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}
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2008-10-12 13:12:34 -06:00
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static int arch_perfmon_init(struct oprofile_operations *ignore)
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{
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arch_perfmon_setup_counters();
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return 0;
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}
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2008-08-18 06:50:31 -06:00
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struct op_x86_model_spec op_arch_perfmon_spec = {
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2009-05-25 07:10:32 -06:00
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.reserved = MSR_PPRO_EVENTSEL_RESERVED,
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2008-10-12 13:12:34 -06:00
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.init = &arch_perfmon_init,
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2008-08-18 06:50:31 -06:00
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/* num_counters/num_controls filled in at runtime */
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2008-09-05 09:12:36 -06:00
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.fill_in_addresses = &ppro_fill_in_addresses,
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2008-08-18 06:50:31 -06:00
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/* user space does the cpuid check for available events */
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2008-09-05 09:12:36 -06:00
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.setup_ctrs = &ppro_setup_ctrs,
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.check_ctrs = &ppro_check_ctrs,
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.start = &ppro_start,
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.stop = &ppro_stop,
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.shutdown = &ppro_shutdown
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2005-04-16 16:20:36 -06:00
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};
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