2012-05-10 08:16:00 -06:00
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Based on "omap4.dtsi"
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*/
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2013-05-31 06:32:56 -06:00
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#include <dt-bindings/gpio/gpio.h>
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2013-05-31 06:32:57 -06:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2013-05-31 06:32:59 -06:00
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#include <dt-bindings/pinctrl/omap.h>
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2012-05-10 08:16:00 -06:00
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2013-05-31 06:32:55 -06:00
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#include "skeleton.dtsi"
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2012-05-10 08:16:00 -06:00
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/ {
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2013-02-12 03:27:55 -07:00
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#address-cells = <1>;
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#size-cells = <1>;
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2012-05-10 08:16:00 -06:00
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compatible = "ti,omap5";
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interrupt-parent = <&gic>;
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aliases {
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2013-10-16 14:21:03 -06:00
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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i2c4 = &i2c5;
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2012-05-10 08:16:00 -06:00
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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};
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cpus {
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2013-04-18 11:35:59 -06:00
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#address-cells = <1>;
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#size-cells = <0>;
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2013-10-16 09:39:04 -06:00
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cpu0: cpu@0 {
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2013-04-18 11:35:59 -06:00
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device_type = "cpu";
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2012-05-10 08:16:00 -06:00
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compatible = "arm,cortex-a15";
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2013-04-18 11:35:59 -06:00
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reg = <0x0>;
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2013-10-16 09:39:06 -06:00
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operating-points = <
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/* kHz uV */
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500000 880000
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1000000 1060000
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1500000 1250000
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>;
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2014-01-29 11:19:17 -07:00
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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2013-08-16 09:30:47 -06:00
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/* cooling options */
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cooling-min-level = <0>;
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cooling-max-level = <2>;
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#cooling-cells = <2>; /* min followed by max */
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2012-05-10 08:16:00 -06:00
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};
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cpu@1 {
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2013-04-18 11:35:59 -06:00
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device_type = "cpu";
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2012-05-10 08:16:00 -06:00
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compatible = "arm,cortex-a15";
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2013-04-18 11:35:59 -06:00
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reg = <0x1>;
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2012-05-10 08:16:00 -06:00
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};
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};
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2013-08-16 10:01:02 -06:00
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thermal-zones {
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#include "omap4-cpu-thermal.dtsi"
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#include "omap5-gpu-thermal.dtsi"
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#include "omap5-core-thermal.dtsi"
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};
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2013-02-10 09:10:19 -07:00
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timer {
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compatible = "arm,armv7-timer";
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2013-05-31 06:32:57 -06:00
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/* PPI secure/nonsecure IRQ */
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
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2013-02-10 09:10:19 -07:00
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};
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2014-03-19 09:45:53 -06:00
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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};
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2013-02-12 03:27:55 -07:00
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gic: interrupt-controller@48211000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48211000 0x1000>,
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2013-02-19 04:59:24 -07:00
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<0x48212000 0x1000>,
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<0x48214000 0x2000>,
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<0x48216000 0x2000>;
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2013-02-12 03:27:55 -07:00
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};
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2012-05-10 08:16:00 -06:00
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/*
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2014-03-28 04:11:37 -06:00
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* The soc node represents the soc top level view. It is used for IPs
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2012-05-10 08:16:00 -06:00
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu";
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};
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};
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/*
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* XXX: Use a flat representation of the OMAP3 interconnect.
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* The real OMAP interconnect network is quite complex.
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2014-03-28 04:11:39 -06:00
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* Since it will not bring real advantage to represent that in DT for
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2012-05-10 08:16:00 -06:00
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "ti,omap4-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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2013-02-26 05:06:14 -07:00
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reg = <0x44000000 0x2000>,
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<0x44800000 0x3000>,
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<0x45000000 0x4000>;
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2013-05-31 06:32:57 -06:00
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 08:16:00 -06:00
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2013-07-18 08:09:29 -06:00
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prm: prm@4ae06000 {
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compatible = "ti,omap5-prm";
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reg = <0x4ae06000 0x3000>;
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prm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prm_clockdomains: clockdomains {
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};
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};
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cm_core_aon: cm_core_aon@4a004000 {
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compatible = "ti,omap5-cm-core-aon";
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reg = <0x4a004000 0x2000>;
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cm_core_aon_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_aon_clockdomains: clockdomains {
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};
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};
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scrm: scrm@4ae0a000 {
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compatible = "ti,omap5-scrm";
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reg = <0x4ae0a000 0x2000>;
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scrm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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scrm_clockdomains: clockdomains {
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};
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};
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cm_core: cm_core@4a008000 {
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compatible = "ti,omap5-cm-core";
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reg = <0x4a008000 0x3000>;
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cm_core_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_clockdomains: clockdomains {
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};
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};
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2012-11-01 08:12:23 -06:00
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counter32k: counter@4ae04000 {
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compatible = "ti,omap-counter32k";
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reg = <0x4ae04000 0x40>;
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ti,hwmods = "counter_32k";
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};
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2012-10-04 05:57:27 -06:00
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omap5_pmx_core: pinmux@4a002840 {
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compatible = "ti,omap4-padconf", "pinctrl-single";
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reg = <0x4a002840 0x01b6>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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omap5_pmx_wkup: pinmux@4ae0c840 {
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compatible = "ti,omap4-padconf", "pinctrl-single";
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reg = <0x4ae0c840 0x0038>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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2014-02-19 07:56:40 -07:00
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omap5_padconf_global: tisyscon@4a002da0 {
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compatible = "syscon";
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reg = <0x4A002da0 0xec>;
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};
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pbias_regulator: pbias_regulator {
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compatible = "ti,pbias-omap";
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reg = <0x60 0x4>;
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syscon = <&omap5_padconf_global>;
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pbias_mmc_reg: pbias_mmc_omap5 {
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regulator-name = "pbias_mmc_omap5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3000000>;
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};
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};
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2012-04-26 12:47:59 -06:00
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sdma: dma-controller@4a056000 {
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compatible = "ti,omap4430-sdma";
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reg = <0x4a056000 0x1000>;
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2013-05-31 06:32:57 -06:00
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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2012-04-26 12:47:59 -06:00
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#dma-cells = <1>;
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#dma-channels = <32>;
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#dma-requests = <127>;
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};
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2012-05-10 08:16:00 -06:00
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gpio1: gpio@4ae10000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 02:37:09 -06:00
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reg = <0x4ae10000 0x200>;
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2013-05-31 06:32:57 -06:00
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 08:16:00 -06:00
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ti,hwmods = "gpio1";
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2013-04-04 14:16:16 -06:00
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ti,gpio-always-on;
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2012-05-10 08:16:00 -06:00
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 14:44:39 -07:00
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#interrupt-cells = <2>;
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2012-05-10 08:16:00 -06:00
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};
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gpio2: gpio@48055000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 02:37:09 -06:00
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reg = <0x48055000 0x200>;
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2013-05-31 06:32:57 -06:00
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 08:16:00 -06:00
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ti,hwmods = "gpio2";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 14:44:39 -07:00
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#interrupt-cells = <2>;
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2012-05-10 08:16:00 -06:00
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};
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gpio3: gpio@48057000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 02:37:09 -06:00
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reg = <0x48057000 0x200>;
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2013-05-31 06:32:57 -06:00
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 08:16:00 -06:00
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ti,hwmods = "gpio3";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 14:44:39 -07:00
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#interrupt-cells = <2>;
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2012-05-10 08:16:00 -06:00
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};
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gpio4: gpio@48059000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 02:37:09 -06:00
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reg = <0x48059000 0x200>;
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2013-05-31 06:32:57 -06:00
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 08:16:00 -06:00
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ti,hwmods = "gpio4";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 14:44:39 -07:00
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#interrupt-cells = <2>;
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2012-05-10 08:16:00 -06:00
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};
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gpio5: gpio@4805b000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 02:37:09 -06:00
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reg = <0x4805b000 0x200>;
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2013-05-31 06:32:57 -06:00
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 08:16:00 -06:00
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ti,hwmods = "gpio5";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 14:44:39 -07:00
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#interrupt-cells = <2>;
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2012-05-10 08:16:00 -06:00
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};
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gpio6: gpio@4805d000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 02:37:09 -06:00
|
|
|
reg = <0x4805d000 0x200>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "gpio6";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-07 14:44:39 -07:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 08:16:00 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio7: gpio@48051000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 02:37:09 -06:00
|
|
|
reg = <0x48051000 0x200>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "gpio7";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-07 14:44:39 -07:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 08:16:00 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio8: gpio@48053000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 02:37:09 -06:00
|
|
|
reg = <0x48053000 0x200>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "gpio8";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-07 14:44:39 -07:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 08:16:00 -06:00
|
|
|
};
|
|
|
|
|
|
2013-02-22 14:33:31 -07:00
|
|
|
gpmc: gpmc@50000000 {
|
|
|
|
|
compatible = "ti,omap4430-gpmc";
|
|
|
|
|
reg = <0x50000000 0x1000>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-22 14:33:31 -07:00
|
|
|
gpmc,num-cs = <8>;
|
|
|
|
|
gpmc,num-waitpins = <4>;
|
|
|
|
|
ti,hwmods = "gpmc";
|
2014-02-26 03:38:09 -07:00
|
|
|
clocks = <&l3_iclk_div>;
|
|
|
|
|
clock-names = "fck";
|
2013-02-22 14:33:31 -07:00
|
|
|
};
|
|
|
|
|
|
2012-07-24 23:27:58 -06:00
|
|
|
i2c1: i2c@48070000 {
|
|
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 02:37:10 -06:00
|
|
|
reg = <0x48070000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-24 23:27:58 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@48072000 {
|
|
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 02:37:10 -06:00
|
|
|
reg = <0x48072000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-24 23:27:58 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c3: i2c@48060000 {
|
|
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 02:37:10 -06:00
|
|
|
reg = <0x48060000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-24 23:27:58 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c3";
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-23 02:37:10 -06:00
|
|
|
i2c4: i2c@4807a000 {
|
2012-07-24 23:27:58 -06:00
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 02:37:10 -06:00
|
|
|
reg = <0x4807a000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-24 23:27:58 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c4";
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-23 02:37:10 -06:00
|
|
|
i2c5: i2c@4807c000 {
|
2012-07-24 23:27:58 -06:00
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 02:37:10 -06:00
|
|
|
reg = <0x4807c000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-24 23:27:58 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c5";
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-10 15:15:34 -06:00
|
|
|
hwspinlock: spinlock@4a0f6000 {
|
|
|
|
|
compatible = "ti,omap4-hwspinlock";
|
|
|
|
|
reg = <0x4a0f6000 0x1000>;
|
|
|
|
|
ti,hwmods = "spinlock";
|
2014-01-13 17:26:45 -07:00
|
|
|
#hwlock-cells = <1>;
|
2013-10-10 15:15:34 -06:00
|
|
|
};
|
|
|
|
|
|
2013-02-13 02:28:36 -07:00
|
|
|
mcspi1: spi@48098000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x48098000 0x200>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-13 02:28:36 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi1";
|
|
|
|
|
ti,spi-num-cs = <4>;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 35>,
|
|
|
|
|
<&sdma 36>,
|
|
|
|
|
<&sdma 37>,
|
|
|
|
|
<&sdma 38>,
|
|
|
|
|
<&sdma 39>,
|
|
|
|
|
<&sdma 40>,
|
|
|
|
|
<&sdma 41>,
|
|
|
|
|
<&sdma 42>;
|
|
|
|
|
dma-names = "tx0", "rx0", "tx1", "rx1",
|
|
|
|
|
"tx2", "rx2", "tx3", "rx3";
|
2013-02-13 02:28:36 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi2: spi@4809a000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x4809a000 0x200>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-13 02:28:36 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi2";
|
|
|
|
|
ti,spi-num-cs = <2>;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 43>,
|
|
|
|
|
<&sdma 44>,
|
|
|
|
|
<&sdma 45>,
|
|
|
|
|
<&sdma 46>;
|
|
|
|
|
dma-names = "tx0", "rx0", "tx1", "rx1";
|
2013-02-13 02:28:36 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi3: spi@480b8000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x480b8000 0x200>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-13 02:28:36 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi3";
|
|
|
|
|
ti,spi-num-cs = <2>;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 15>, <&sdma 16>;
|
|
|
|
|
dma-names = "tx0", "rx0";
|
2013-02-13 02:28:36 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi4: spi@480ba000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x480ba000 0x200>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-13 02:28:36 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi4";
|
|
|
|
|
ti,spi-num-cs = <1>;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 70>, <&sdma 71>;
|
|
|
|
|
dma-names = "tx0", "rx0";
|
2013-02-13 02:28:36 -07:00
|
|
|
};
|
|
|
|
|
|
2012-05-10 08:16:00 -06:00
|
|
|
uart1: serial@4806a000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 02:37:11 -06:00
|
|
|
reg = <0x4806a000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "uart1";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart2: serial@4806c000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 02:37:11 -06:00
|
|
|
reg = <0x4806c000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "uart2";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart3: serial@48020000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 02:37:11 -06:00
|
|
|
reg = <0x48020000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "uart3";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart4: serial@4806e000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 02:37:11 -06:00
|
|
|
reg = <0x4806e000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "uart4";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart5: serial@48066000 {
|
2012-10-23 02:37:11 -06:00
|
|
|
compatible = "ti,omap4-uart";
|
|
|
|
|
reg = <0x48066000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "uart5";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart6: serial@48068000 {
|
2012-10-23 02:37:11 -06:00
|
|
|
compatible = "ti,omap4-uart";
|
|
|
|
|
reg = <0x48068000 0x100>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 08:16:00 -06:00
|
|
|
ti,hwmods = "uart6";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
2012-08-07 01:18:21 -06:00
|
|
|
|
|
|
|
|
mmc1: mmc@4809c000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 02:37:12 -06:00
|
|
|
reg = <0x4809c000 0x400>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 01:18:21 -06:00
|
|
|
ti,hwmods = "mmc1";
|
|
|
|
|
ti,dual-volt;
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 61>, <&sdma 62>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-02-19 07:56:40 -07:00
|
|
|
pbias-supply = <&pbias_mmc_reg>;
|
2012-08-07 01:18:21 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc2: mmc@480b4000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 02:37:12 -06:00
|
|
|
reg = <0x480b4000 0x400>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 01:18:21 -06:00
|
|
|
ti,hwmods = "mmc2";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 47>, <&sdma 48>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 01:18:21 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc3: mmc@480ad000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 02:37:12 -06:00
|
|
|
reg = <0x480ad000 0x400>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 01:18:21 -06:00
|
|
|
ti,hwmods = "mmc3";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 77>, <&sdma 78>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 01:18:21 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc4: mmc@480d1000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 02:37:12 -06:00
|
|
|
reg = <0x480d1000 0x400>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 01:18:21 -06:00
|
|
|
ti,hwmods = "mmc4";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 57>, <&sdma 58>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 01:18:21 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc5: mmc@480d5000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 02:37:12 -06:00
|
|
|
reg = <0x480d5000 0x400>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 01:18:21 -06:00
|
|
|
ti,hwmods = "mmc5";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 12:47:59 -06:00
|
|
|
dmas = <&sdma 59>, <&sdma 60>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 01:18:21 -06:00
|
|
|
};
|
2012-07-24 23:33:27 -06:00
|
|
|
|
2014-03-05 17:24:19 -07:00
|
|
|
mmu_dsp: mmu@4a066000 {
|
|
|
|
|
compatible = "ti,omap4-iommu";
|
|
|
|
|
reg = <0x4a066000 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
ti,hwmods = "mmu_dsp";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmu_ipu: mmu@55082000 {
|
|
|
|
|
compatible = "ti,omap4-iommu";
|
|
|
|
|
reg = <0x55082000 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
ti,hwmods = "mmu_ipu";
|
|
|
|
|
ti,iommu-bus-err-back;
|
|
|
|
|
};
|
|
|
|
|
|
2012-07-24 23:33:27 -06:00
|
|
|
keypad: keypad@4ae1c000 {
|
|
|
|
|
compatible = "ti,omap4-keypad";
|
2013-01-23 07:23:30 -07:00
|
|
|
reg = <0x4ae1c000 0x400>;
|
2012-07-24 23:33:27 -06:00
|
|
|
ti,hwmods = "kbd";
|
|
|
|
|
};
|
2012-08-29 07:31:04 -06:00
|
|
|
|
2012-08-29 07:31:07 -06:00
|
|
|
mcpdm: mcpdm@40132000 {
|
|
|
|
|
compatible = "ti,omap4-mcpdm";
|
|
|
|
|
reg = <0x40132000 0x7f>, /* MPU private access */
|
|
|
|
|
<0x49032000 0x7f>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 07:31:07 -06:00
|
|
|
ti,hwmods = "mcpdm";
|
2013-03-11 01:50:21 -06:00
|
|
|
dmas = <&sdma 65>,
|
|
|
|
|
<&sdma 66>;
|
|
|
|
|
dma-names = "up_link", "dn_link";
|
2014-01-24 01:19:04 -07:00
|
|
|
status = "disabled";
|
2012-08-29 07:31:07 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dmic: dmic@4012e000 {
|
|
|
|
|
compatible = "ti,omap4-dmic";
|
|
|
|
|
reg = <0x4012e000 0x7f>, /* MPU private access */
|
|
|
|
|
<0x4902e000 0x7f>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 07:31:07 -06:00
|
|
|
ti,hwmods = "dmic";
|
2013-03-11 01:50:21 -06:00
|
|
|
dmas = <&sdma 67>;
|
|
|
|
|
dma-names = "up_link";
|
2014-01-24 01:19:04 -07:00
|
|
|
status = "disabled";
|
2012-08-29 07:31:07 -06:00
|
|
|
};
|
|
|
|
|
|
2012-08-29 07:31:04 -06:00
|
|
|
mcbsp1: mcbsp@40122000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40122000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49022000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 07:31:04 -06:00
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp1";
|
2013-03-11 01:50:21 -06:00
|
|
|
dmas = <&sdma 33>,
|
|
|
|
|
<&sdma 34>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-01-24 01:19:04 -07:00
|
|
|
status = "disabled";
|
2012-08-29 07:31:04 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcbsp2: mcbsp@40124000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40124000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49024000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 07:31:04 -06:00
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp2";
|
2013-03-11 01:50:21 -06:00
|
|
|
dmas = <&sdma 17>,
|
|
|
|
|
<&sdma 18>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-01-24 01:19:04 -07:00
|
|
|
status = "disabled";
|
2012-08-29 07:31:04 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcbsp3: mcbsp@40126000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40126000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49026000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 07:31:04 -06:00
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp3";
|
2013-03-11 01:50:21 -06:00
|
|
|
dmas = <&sdma 19>,
|
|
|
|
|
<&sdma 20>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-01-24 01:19:04 -07:00
|
|
|
status = "disabled";
|
2012-08-29 07:31:04 -06:00
|
|
|
};
|
2012-11-01 08:09:51 -06:00
|
|
|
|
2014-04-22 16:23:35 -06:00
|
|
|
mailbox: mailbox@4a0f4000 {
|
|
|
|
|
compatible = "ti,omap4-mailbox";
|
|
|
|
|
reg = <0x4a0f4000 0x200>;
|
|
|
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
ti,hwmods = "mailbox";
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-01 08:09:51 -06:00
|
|
|
timer1: timer@4ae18000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x4ae18000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer1";
|
|
|
|
|
ti,timer-alwon;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer2: timer@48032000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x48032000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer3: timer@48034000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x48034000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer3";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer4: timer@48036000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x48036000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer4";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer5: timer@40138000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x40138000 0x80>,
|
|
|
|
|
<0x49038000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer5";
|
|
|
|
|
ti,timer-dsp;
|
2013-04-17 17:23:15 -06:00
|
|
|
ti,timer-pwm;
|
2012-11-01 08:09:51 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer6: timer@4013a000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x4013a000 0x80>,
|
|
|
|
|
<0x4903a000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer6";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer7: timer@4013c000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x4013c000 0x80>,
|
|
|
|
|
<0x4903c000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer7";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer8: timer@4013e000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x4013e000 0x80>,
|
|
|
|
|
<0x4903e000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer8";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer9: timer@4803e000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x4803e000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer9";
|
2013-04-17 17:23:15 -06:00
|
|
|
ti,timer-pwm;
|
2012-11-01 08:09:51 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer10: timer@48086000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x48086000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer10";
|
2013-04-17 17:23:15 -06:00
|
|
|
ti,timer-pwm;
|
2012-11-01 08:09:51 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer11: timer@48088000 {
|
2013-03-19 11:38:18 -06:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 08:09:51 -06:00
|
|
|
reg = <0x48088000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 08:09:51 -06:00
|
|
|
ti,hwmods = "timer11";
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
2012-11-05 05:52:51 -07:00
|
|
|
|
2013-02-26 23:24:45 -07:00
|
|
|
wdt2: wdt@4ae14000 {
|
|
|
|
|
compatible = "ti,omap5-wdt", "ti,omap3-wdt";
|
|
|
|
|
reg = <0x4ae14000 0x80>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-26 23:24:45 -07:00
|
|
|
ti,hwmods = "wd_timer2";
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-17 03:02:21 -07:00
|
|
|
dmm@4e000000 {
|
|
|
|
|
compatible = "ti,omap5-dmm";
|
|
|
|
|
reg = <0x4e000000 0x800>;
|
|
|
|
|
interrupts = <0 113 0x4>;
|
|
|
|
|
ti,hwmods = "dmm";
|
|
|
|
|
};
|
|
|
|
|
|
2013-07-22 04:52:37 -06:00
|
|
|
emif1: emif@4c000000 {
|
2012-11-05 05:52:51 -07:00
|
|
|
compatible = "ti,emif-4d5";
|
|
|
|
|
ti,hwmods = "emif1";
|
2013-10-15 01:07:50 -06:00
|
|
|
ti,no-idle-on-init;
|
2012-11-05 05:52:51 -07:00
|
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
|
|
|
reg = <0x4c000000 0x400>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-05 05:52:51 -07:00
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
|
};
|
|
|
|
|
|
2013-07-22 04:52:37 -06:00
|
|
|
emif2: emif@4d000000 {
|
2012-11-05 05:52:51 -07:00
|
|
|
compatible = "ti,emif-4d5";
|
|
|
|
|
ti,hwmods = "emif2";
|
2013-10-15 01:07:50 -06:00
|
|
|
ti,no-idle-on-init;
|
2012-11-05 05:52:51 -07:00
|
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
|
|
|
reg = <0x4d000000 0x400>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-05 05:52:51 -07:00
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
|
};
|
2013-03-07 06:35:17 -07:00
|
|
|
|
2013-10-03 09:12:37 -06:00
|
|
|
omap_control_usb2phy: control-phy@4a002300 {
|
|
|
|
|
compatible = "ti,control-phy-usb2";
|
|
|
|
|
reg = <0x4a002300 0x4>;
|
|
|
|
|
reg-names = "power";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
omap_control_usb3phy: control-phy@4a002370 {
|
|
|
|
|
compatible = "ti,control-phy-pipe3";
|
|
|
|
|
reg = <0x4a002370 0x4>;
|
|
|
|
|
reg-names = "power";
|
2013-03-07 06:35:17 -07:00
|
|
|
};
|
2013-03-07 06:35:18 -07:00
|
|
|
|
2013-08-21 08:31:32 -06:00
|
|
|
usb3: omap_dwc3@4a020000 {
|
2013-03-07 06:35:20 -07:00
|
|
|
compatible = "ti,dwc3";
|
|
|
|
|
ti,hwmods = "usb_otg_ss";
|
2013-08-21 08:31:30 -06:00
|
|
|
reg = <0x4a020000 0x10000>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
2013-03-07 06:35:20 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
utmi-mode = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
dwc3@4a030000 {
|
2013-07-02 12:20:24 -06:00
|
|
|
compatible = "snps,dwc3";
|
2013-08-21 08:31:30 -06:00
|
|
|
reg = <0x4a030000 0x10000>;
|
2013-05-31 06:32:57 -06:00
|
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
2014-03-03 04:38:15 -07:00
|
|
|
phys = <&usb2_phy>, <&usb3_phy>;
|
|
|
|
|
phy-names = "usb2-phy", "usb3-phy";
|
2013-10-10 04:49:54 -06:00
|
|
|
dr_mode = "peripheral";
|
2013-03-07 06:35:20 -07:00
|
|
|
tx-fifo-resize;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-08-21 08:31:31 -06:00
|
|
|
ocp2scp@4a080000 {
|
2013-03-07 06:35:18 -07:00
|
|
|
compatible = "ti,omap-ocp2scp";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2013-08-21 08:31:31 -06:00
|
|
|
reg = <0x4a080000 0x20>;
|
2013-03-07 06:35:18 -07:00
|
|
|
ranges;
|
|
|
|
|
ti,hwmods = "ocp2scp1";
|
2013-03-07 06:35:19 -07:00
|
|
|
usb2_phy: usb2phy@4a084000 {
|
|
|
|
|
compatible = "ti,omap-usb2";
|
|
|
|
|
reg = <0x4a084000 0x7c>;
|
2013-10-03 09:12:37 -06:00
|
|
|
ctrl-module = <&omap_control_usb2phy>;
|
2014-05-05 03:54:42 -06:00
|
|
|
clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
|
|
|
|
|
clock-names = "wkupclk", "refclk";
|
2014-03-03 04:38:15 -07:00
|
|
|
#phy-cells = <0>;
|
2013-03-07 06:35:19 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb3_phy: usb3phy@4a084400 {
|
|
|
|
|
compatible = "ti,omap-usb3";
|
|
|
|
|
reg = <0x4a084400 0x80>,
|
|
|
|
|
<0x4a084800 0x64>,
|
|
|
|
|
<0x4a084c00 0x40>;
|
|
|
|
|
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
2013-10-03 09:12:37 -06:00
|
|
|
ctrl-module = <&omap_control_usb3phy>;
|
2014-04-01 04:37:27 -06:00
|
|
|
clocks = <&usb_phy_cm_clk32k>,
|
|
|
|
|
<&sys_clkin>,
|
|
|
|
|
<&usb_otg_ss_refclk960m>;
|
|
|
|
|
clock-names = "wkupclk",
|
|
|
|
|
"sysclk",
|
|
|
|
|
"refclk";
|
2014-03-03 04:38:15 -07:00
|
|
|
#phy-cells = <0>;
|
2013-03-07 06:35:19 -07:00
|
|
|
};
|
2013-03-07 06:35:18 -07:00
|
|
|
};
|
2013-06-07 07:22:48 -06:00
|
|
|
|
|
|
|
|
usbhstll: usbhstll@4a062000 {
|
|
|
|
|
compatible = "ti,usbhs-tll";
|
|
|
|
|
reg = <0x4a062000 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
ti,hwmods = "usb_tll_hs";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbhshost: usbhshost@4a064000 {
|
|
|
|
|
compatible = "ti,usbhs-host";
|
|
|
|
|
reg = <0x4a064000 0x800>;
|
|
|
|
|
ti,hwmods = "usb_host_hs";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
2014-02-27 07:18:26 -07:00
|
|
|
clocks = <&l3init_60m_fclk>,
|
|
|
|
|
<&xclk60mhsp1_ck>,
|
|
|
|
|
<&xclk60mhsp2_ck>;
|
|
|
|
|
clock-names = "refclk_60m_int",
|
|
|
|
|
"refclk_60m_ext_p1",
|
|
|
|
|
"refclk_60m_ext_p2";
|
2013-06-07 07:22:48 -06:00
|
|
|
|
|
|
|
|
usbhsohci: ohci@4a064800 {
|
2014-02-27 07:18:30 -07:00
|
|
|
compatible = "ti,ohci-omap3";
|
2013-06-07 07:22:48 -06:00
|
|
|
reg = <0x4a064800 0x400>;
|
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbhsehci: ehci@4a064c00 {
|
2014-02-27 07:18:30 -07:00
|
|
|
compatible = "ti,ehci-omap";
|
2013-06-07 07:22:48 -06:00
|
|
|
reg = <0x4a064c00 0x400>;
|
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-06-18 20:36:38 -06:00
|
|
|
|
2013-08-16 10:01:02 -06:00
|
|
|
bandgap: bandgap@4a0021e0 {
|
2013-06-18 20:36:38 -06:00
|
|
|
reg = <0x4a0021e0 0xc
|
|
|
|
|
0x4a00232c 0xc
|
|
|
|
|
0x4a002380 0x2c
|
|
|
|
|
0x4a0023C0 0x3c>;
|
|
|
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
compatible = "ti,omap5430-bandgap";
|
2013-08-16 10:01:02 -06:00
|
|
|
|
|
|
|
|
#thermal-sensor-cells = <1>;
|
2013-06-18 20:36:38 -06:00
|
|
|
};
|
2014-04-23 11:35:33 -06:00
|
|
|
|
|
|
|
|
omap_control_sata: control-phy@4a002374 {
|
|
|
|
|
compatible = "ti,control-phy-pipe3";
|
|
|
|
|
reg = <0x4a002374 0x4>;
|
|
|
|
|
reg-names = "power";
|
|
|
|
|
clocks = <&sys_clkin>;
|
|
|
|
|
clock-names = "sysclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* OCP2SCP3 */
|
|
|
|
|
ocp2scp@4a090000 {
|
|
|
|
|
compatible = "ti,omap-ocp2scp";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
reg = <0x4a090000 0x20>;
|
|
|
|
|
ranges;
|
|
|
|
|
ti,hwmods = "ocp2scp3";
|
|
|
|
|
sata_phy: phy@4a096000 {
|
|
|
|
|
compatible = "ti,phy-pipe3-sata";
|
|
|
|
|
reg = <0x4A096000 0x80>, /* phy_rx */
|
|
|
|
|
<0x4A096400 0x64>, /* phy_tx */
|
|
|
|
|
<0x4A096800 0x40>; /* pll_ctrl */
|
|
|
|
|
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
|
|
|
|
ctrl-module = <&omap_control_sata>;
|
|
|
|
|
clocks = <&sys_clkin>;
|
|
|
|
|
clock-names = "sysclk";
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sata: sata@4a141100 {
|
|
|
|
|
compatible = "snps,dwc-ahci";
|
|
|
|
|
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
|
|
|
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
phys = <&sata_phy>;
|
|
|
|
|
phy-names = "sata-phy";
|
|
|
|
|
clocks = <&sata_ref_clk>;
|
|
|
|
|
ti,hwmods = "sata";
|
|
|
|
|
};
|
|
|
|
|
|
2014-03-07 03:45:54 -07:00
|
|
|
dss: dss@58000000 {
|
|
|
|
|
compatible = "ti,omap5-dss";
|
|
|
|
|
reg = <0x58000000 0x80>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
ti,hwmods = "dss_core";
|
|
|
|
|
clocks = <&dss_dss_clk>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
dispc@58001000 {
|
|
|
|
|
compatible = "ti,omap5-dispc";
|
|
|
|
|
reg = <0x58001000 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
ti,hwmods = "dss_dispc";
|
|
|
|
|
clocks = <&dss_dss_clk>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dsi1: encoder@58004000 {
|
|
|
|
|
compatible = "ti,omap5-dsi";
|
|
|
|
|
reg = <0x58004000 0x200>,
|
|
|
|
|
<0x58004200 0x40>,
|
|
|
|
|
<0x58004300 0x40>;
|
|
|
|
|
reg-names = "proto", "phy", "pll";
|
|
|
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
ti,hwmods = "dss_dsi1";
|
|
|
|
|
clocks = <&dss_dss_clk>, <&dss_sys_clk>;
|
|
|
|
|
clock-names = "fck", "sys_clk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dsi2: encoder@58005000 {
|
|
|
|
|
compatible = "ti,omap5-dsi";
|
|
|
|
|
reg = <0x58009000 0x200>,
|
|
|
|
|
<0x58009200 0x40>,
|
|
|
|
|
<0x58009300 0x40>;
|
|
|
|
|
reg-names = "proto", "phy", "pll";
|
|
|
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
ti,hwmods = "dss_dsi2";
|
|
|
|
|
clocks = <&dss_dss_clk>, <&dss_sys_clk>;
|
|
|
|
|
clock-names = "fck", "sys_clk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hdmi: encoder@58060000 {
|
|
|
|
|
compatible = "ti,omap5-hdmi";
|
|
|
|
|
reg = <0x58040000 0x200>,
|
|
|
|
|
<0x58040200 0x80>,
|
|
|
|
|
<0x58040300 0x80>,
|
|
|
|
|
<0x58060000 0x19000>;
|
|
|
|
|
reg-names = "wp", "pll", "phy", "core";
|
|
|
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
ti,hwmods = "dss_hdmi";
|
|
|
|
|
clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
|
|
|
|
|
clock-names = "fck", "sys_clk";
|
2014-05-12 03:12:26 -06:00
|
|
|
dmas = <&sdma 76>;
|
|
|
|
|
dma-names = "audio_tx";
|
2014-03-07 03:45:54 -07:00
|
|
|
};
|
|
|
|
|
};
|
2012-05-10 08:16:00 -06:00
|
|
|
};
|
|
|
|
|
};
|
2013-07-18 08:09:29 -06:00
|
|
|
|
|
|
|
|
/include/ "omap54xx-clocks.dtsi"
|
